coreboot-gerrit July 2024

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[XS] Change in coreboot[main]: src/device/Kconfig: Enable eSOL config with libgfx and uGOP
by Jayvik Desai (Code Review) 31 Jul '24

31 Jul '24

Jayvik Desai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83705?usp=email ) Change subject: src/device/Kconfig: Enable eSOL config with libgfx and uGOP ...................................................................... src/device/Kconfig: Enable eSOL config with libgfx and uGOP This patch enables the eSOL config option when libgfx is enabled for early graphics initialization. BUG=NA TEST=Able to build google/rex and google/tivviks Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950 Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/83705/1 diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index b0cbc67..d3dbfac 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -15,6 +15,7 @@ select CHROMEOS_NVS if ACPI_SOC_NVS select VPD select VBOOT_SLOTS_RW_AB + select CHROMEOS_ENABLES_ESOL if MAINBOARD_HAS_EARLY_LIBGFXINIT || SOC_INTEL_METEORLAKE_SIGN_OF_LIFE help Enable ChromeOS specific features like the GPIO sub table in the coreboot table. NOTE: Enabling this option on an unsupported @@ -81,6 +82,7 @@ config CHROMEOS_ENABLES_ESOL def_bool n + depends on MAINBOARD_HAS_EARLY_LIBGFXINIT || SOC_INTEL_METEORLAKE_SIGN_OF_LIFE help Enabled if the platform has an early sign of life feature. -- To view, visit https://review.coreboot.org/c/coreboot/+/83705?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8fe4ca5234de7f8e579f950f6ccbf750f4c7950 Gerrit-Change-Number: 83705 Gerrit-PatchSet: 1 Gerrit-Owner: Jayvik Desai <jayvik(a)google.com>

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[XS] Change in coreboot[main]: vc/google/chromeos/Kconfig: Enable config to determine eSOL status
by Jayvik Desai (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai. Jayvik Desai has uploaded a new patch set (#4) to the change originally created by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/83667?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vc/google/chromeos/Kconfig: Enable config to determine eSOL status ...................................................................... vc/google/chromeos/Kconfig: Enable config to determine eSOL status The patch adds a config CHROMEOS_ENABLES_ESOL to determine whether eSOL is enabled. BUG=NA TEST=Able to build google/rex and google/tivviks Change-Id: I68aca8033cf843e8a569339ab1af85fab104b36a Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Signed-off-by: Jayvik Desai <jayvik(a)google.com> --- M src/vendorcode/google/chromeos/Kconfig 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/83667/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/83667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I68aca8033cf843e8a569339ab1af85fab104b36a Gerrit-Change-Number: 83667 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com>

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[XL] Change in coreboot[main]: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148
by Subrata Banik (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Appukuttan V K, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83636?usp=email ) Change subject: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148 ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: Please submit the code which is required to compile. For example: who is the consimer for GpioConfig.h in coreboot ? Ideally you just need to push below file (if you need any more files for PTL then I wish to know the reason) 1. FirmwareVersionInfo.h 2. FspmUpd.h 3. FspsUpd.h 4. FspProducerDataHeader.h 5. FspUpd.h 6. MenInfoHob.h -- To view, visit https://review.coreboot.org/c/coreboot/+/83636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ef76d6fc76b2e87daeb44af8df471d20c2e43f6 Gerrit-Change-Number: 83636 Gerrit-PatchSet: 20 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 12:51:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 31: (8 comments) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83354/comment/9a31e5a5_ccb35894?us… : PS30, Line 141: 0xfe02c000 > what is the reason behind changing the UART base address ? We have matched with PTL FSP base address. This setting ensures the FSP's setting right IRQ to LPSS will be used by the coreboot. File src/soc/intel/pantherlake/include/soc/iomap.h: https://review.coreboot.org/c/coreboot/+/83354/comment/d7709d76_7b2acca4?us… : PS30, Line 17: > ``` […] Acknowledged https://review.coreboot.org/c/coreboot/+/83354/comment/e2064711_4db9587d?us… : PS30, Line 18: 0xfa000000 > as per FAS "SAFBAR will be moved to above 4GB", I could see the BAR is above 4GB as per FAS Corrected. https://review.coreboot.org/c/coreboot/+/83354/comment/1fd2ad5f_9eff9365?us… : PS30, Line 18: > use tab Acknowledged https://review.coreboot.org/c/coreboot/+/83354/comment/fbdcd0aa_b4b87d5e?us… : PS30, Line 19: > same Acknowledged https://review.coreboot.org/c/coreboot/+/83354/comment/eae218e9_4e2df62b?us… : PS30, Line 46: > use tab Acknowledged File src/soc/intel/pantherlake/include/soc/pcr_ids.h: https://review.coreboot.org/c/coreboot/+/83354/comment/c4a54516_0afeeedd?us… : PS30, Line 6: ids > IDs? Acknowledged File src/soc/intel/pantherlake/include/soc/pm.h: https://review.coreboot.org/c/coreboot/+/83354/comment/9c655af8_88044c28?us… : PS30, Line 7: WAK_STS BIT(15) : #define PCIEXPWAK_STS BIT(14) : #define PRBTNOR_STS BIT(11) : #define RTC_STS BIT(10) : #define PWRBTN_STS BIT(8) : #define GBL_STS BIT(5) : #define BM_STS BIT(4) : #define TMROF_STS BIT(0) > use one space to start with because these are the bit fields of PM1_STS […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 31 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 12:34:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83354?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/bootblock/bootblock.c A src/soc/intel/pantherlake/bootblock/pcd.c A src/soc/intel/pantherlake/bootblock/report_platform.c A src/soc/intel/pantherlake/espi.c A src/soc/intel/pantherlake/include/soc/bootblock.h A src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pci_devs.h A src/soc/intel/pantherlake/include/soc/pcr_ids.h A src/soc/intel/pantherlake/include/soc/pm.h A src/soc/intel/pantherlake/include/soc/smbus.h A src/soc/intel/pantherlake/include/soc/soc_info.h A src/soc/intel/pantherlake/soc_info.c 15 files changed, 1,271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 31 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XL] Change in coreboot[main]: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Appukuttan V K, Saurabh Mishra. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83636?usp=email to look at the new patch set (#20). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148 ...................................................................... vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148 Change-Id: I7ef76d6fc76b2e87daeb44af8df471d20c2e43f6 Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspProducerDataHeader.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/FsptUpd.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/GpioConfig.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/GpioSampleDef.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/HobUsageDataHob.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/SmbiosCacheInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/pantherlake/SmbiosProcessorInfoHob.h 12 files changed, 2,291 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/83636/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/83636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ef76d6fc76b2e87daeb44af8df471d20c2e43f6 Gerrit-Change-Number: 83636 Gerrit-PatchSet: 20 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com>

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[L] Change in coreboot[main]: mb/hp: Add Compaq Elite 8300 CMT port
by Nicholas Chin (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Paul Menzel, Riku Viitanen. Nicholas Chin has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/79745?usp=email ) Change subject: mb/hp: Add Compaq Elite 8300 CMT port ...................................................................... Patch Set 14: (1 comment) File src/mainboard/hp/compaq_elite_8300_cmt/early_init.c: https://review.coreboot.org/c/coreboot/+/79745/comment/4e7180b0_0e8c476f?us… : PS14, Line 11: { 1, 0, 0 }, : { 1, 0, 0 }, : { 1, 0, 1 }, : { 1, 0, 1 }, : { 1, 0, 2 }, : { 1, 0, 2 }, : { 1, 0, 3 }, : { 1, 0, 3 }, : { 1, 0, 4 }, : { 1, 0, 4 }, : { 1, 0, 6 }, : { 1, 0, 5 }, : { 1, 0, 5 }, : { 1, 0, 6 }, Move to devicetree, refer to commit c36b5ea18983 (mb/*: Copy bd82x6x boards' USB port config into devicetree) and the rest of that patch train -- To view, visit https://review.coreboot.org/c/coreboot/+/79745?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363 Gerrit-Change-Number: 79745 Gerrit-PatchSet: 14 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 31 Jul 2024 12:28:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Subrata Banik (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 30: (1 comment) Patchset: PS19: > Sure, i have already pushed the patch (Intel-Internal) > > 83636: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148 | https://review.coreboot.org/c/coreboot/+/83636 > > I have opened it now. Please follow my comments in the FSP vendorcode CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 30 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 12:07:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148
by Subrata Banik (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Appukuttan V K, Saurabh Mishra. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83636?usp=email ) Change subject: vc/intel/fsp2_0: Add UPDs into the FSP partial header version 7148 ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: you need to push other required files as well as part of PTL vendorcode. like MemInfoHob.h that your FSP-M requires. Kindly push CLs with code compiled locally to catch those issue ? -- To view, visit https://review.coreboot.org/c/coreboot/+/83636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ef76d6fc76b2e87daeb44af8df471d20c2e43f6 Gerrit-Change-Number: 83636 Gerrit-PatchSet: 19 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 12:06:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

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