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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 30:
(8 comments)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/f5eb8305_af247d34?us… :
PS30, Line 141: 0xfe02c000
what is the reason behind changing the UART base address ?
File src/soc/intel/pantherlake/include/soc/iomap.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/884e4381_ab964f02?us… :
PS30, Line 17:
```
/* System Agent Fabric (SAF) */
```
https://review.coreboot.org/c/coreboot/+/83354/comment/767e58c3_55b9b0ea?us… :
PS30, Line 18:
use tab
https://review.coreboot.org/c/coreboot/+/83354/comment/00df8362_a132c470?us… :
PS30, Line 18: 0xfa000000
as per FAS "SAFBAR will be moved to above 4GB", I could see the BAR is above 4GB as per FAS
https://review.coreboot.org/c/coreboot/+/83354/comment/42be9ae7_65df5112?us… :
PS30, Line 19:
same
https://review.coreboot.org/c/coreboot/+/83354/comment/b10c341f_d0d5a80c?us… :
PS30, Line 46:
use tab
File src/soc/intel/pantherlake/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/2953dbea_2c765bc6?us… :
PS30, Line 6: ids
IDs?
File src/soc/intel/pantherlake/include/soc/pm.h:
https://review.coreboot.org/c/coreboot/+/83354/comment/f1bed429_8751b925?us… :
PS30, Line 7: WAK_STS BIT(15)
: #define PCIEXPWAK_STS BIT(14)
: #define PRBTNOR_STS BIT(11)
: #define RTC_STS BIT(10)
: #define PWRBTN_STS BIT(8)
: #define GBL_STS BIT(5)
: #define BM_STS BIT(4)
: #define TMROF_STS BIT(0)
use one space to start with because these are the bit fields of PM1_STS
same for rest of the macros
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Change subject: mb/google/brox: Create jubilant variant
......................................................................
mb/google/brox: Create jubilant variant
Create the jubilant variant of the brox reference board by copying
the template files to a new directory named for the variant.
BUG=b:348543712
TEST=util/abuild/abuild -p none -t google/brox -x -a
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---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/Kconfig.name
A src/mainboard/google/brox/variants/jubilant/Makefile.mk
A src/mainboard/google/brox/variants/jubilant/data.vbt
A src/mainboard/google/brox/variants/jubilant/gpio.c
A src/mainboard/google/brox/variants/jubilant/include/variant/ec.h
A src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h
A src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h
A src/mainboard/google/brox/variants/jubilant/memory.c
A src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk
A src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/jubilant/overridetree.cb
A src/mainboard/google/brox/variants/jubilant/ramstage.c
A src/mainboard/google/brox/variants/jubilant/variant.c
15 files changed, 1,003 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83212/26
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Change subject: mb/google/brox: Create jubilant variant
......................................................................
mb/google/brox: Create jubilant variant
Create the jubilant variant of the brox reference board by copying
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BUG=b:348543712
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---
M src/mainboard/google/brox/Kconfig
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A src/mainboard/google/brox/variants/jubilant/Makefile.mk
A src/mainboard/google/brox/variants/jubilant/data.vbt
A src/mainboard/google/brox/variants/jubilant/gpio.c
A src/mainboard/google/brox/variants/jubilant/include/variant/ec.h
A src/mainboard/google/brox/variants/jubilant/include/variant/gpio.h
A src/mainboard/google/brox/variants/jubilant/include/variant/hda_verb.h
A src/mainboard/google/brox/variants/jubilant/memory.c
A src/mainboard/google/brox/variants/jubilant/memory/Makefile.mk
A src/mainboard/google/brox/variants/jubilant/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/jubilant/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/jubilant/overridetree.cb
A src/mainboard/google/brox/variants/jubilant/ramstage.c
A src/mainboard/google/brox/variants/jubilant/variant.c
15 files changed, 1,004 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/83212/25
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS19:
> Hi Subrata, we are using same for PTL as well, "UDK_202302_BINDING"
But the build is still unhappy about the FSP header. If you don't have any FSP header available for PTL yet, you can consider adding an empty file for now. That should get the build passing and allow further progress.
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/867b44a1_9e057380?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> Good catch. Will update.
Done
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
soc/intel/xeon_sp: Add acpigen_write_pci_root_port
acpigen_write_pci_root_port writes SSDT device objects for PCIe
root port, _ADR and _BBN are provided. SSDT objects for direct
subordinate devices will also be created (if detected), _ADR and
_SUN are provided.
TEST=Build and boot on intel/archercity CRB
Change-Id: I434fea7880a463c2027abfa22ba2b3bb985815c0
Signed-off-by: Lu, Pen-ChunX <pen-chunx.lu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
2 files changed, 55 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/82252/7
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/c8467d52_f5485fc9?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> Can the check be dropped?
Good catch. Will update.
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