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Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
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Patch Set 9: Code-Review+2
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Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
Patch Set 31:
(1 comment)
File src/soc/intel/pantherlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/83354/comment/3663416d_45997d07?us… :
PS14, Line 67: ~1KiB)
> Sure, let me cross confirm with FSP Team.
Hi Subrata, i have checked with FSP Team, as per the MTL FSP Integration guide, the FSP Stack and Heap requirement for CAR is given below:
MTL: FSP's stack usage starts from the current stack pointer. The minimum stack size requirement for FSP-M
is 256KB.
The boot loader must provide at minimum 256KB of stack and 128KB of HOB heap to execute
FSP on this platform.
The external released FSP Integration guide for MTL should also contains the same information.
For PTL, as per PTL FSP Integration guide, the boot loader must provide at minimum 256KB of stack and 160KB of HOB heap to execute FSP on this platform.
PTL:
Below are the heap and stack requirements for FSP on this platform:
HOB Heap requirement:
HOB Heap | UPD | Setting
---------|-------------------------------|----------------------------------------------------
Base |FSPM_UPD.FspmArchUpd.StackBase |Any non-conflict CAR region (0xFEF17F00 as default)
Size |FSPM_UPD.FspmArchUpd.StackSize |at least 128KB
Stack requirement:
FSP's stack usage starts from the current stack pointer. The minimum stack size requirement for FSP-M
is 256KB.
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Hello Angel Pons, Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83018?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+2 by Angel Pons, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: util/superiotool/fintek: Add missing F81804 name for 0x0215 id
......................................................................
util/superiotool/fintek: Add missing F81804 name for 0x0215 id
"0x1502 F81804 chipset ID, same for F81966" in
https://web.archive.org/web/20240628153609/https://github.com/torvalds/
linux/blob/master/drivers/gpio/gpio-f7188x.c
Change-Id: I6889ad8ad861465316333ff997956a05b74c5855
Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com>
---
M util/superiotool/fintek.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/83018/9
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Change subject: soc/intel/xeon_sp: Add PCIe root port driver
......................................................................
Patch Set 9: Code-Review+1
(2 comments)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/81567/comment/cc3295ca_0efa1cda?us… :
PS9, Line 116: pcie_device_set_acpi_name
Is this going to be called from other parts as well?
If there's only one caller (like a PCI driver), can this be made static instead?
File src/soc/intel/xeon_sp/uncore.c:
https://review.coreboot.org/c/coreboot/+/81567/comment/eab3aa22_7c880843?us… :
PS9, Line 474:
would be nice to have this in a separate file
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Change subject: mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_config
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Patch Set 5: Code-Review+1
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Change subject: soc/amd/common/smi_util: add PSP SMI helper functions
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83702/comment/5d5dcf6d_6ddad5e5?us… :
PS2, Line 12: to its
> *in* its?
Done
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