coreboot-gerrit July 2024

coreboot-gerrit@coreboot.org

1 participants
3025 discussions

[M] Change in coreboot[main]: mb/google/brox/var/greenbayupoc: update ALC236 verb table
by Shelley Chen (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Derek Huang, Garen Wu, Karthik Ramasubramanian, Subrata Banik. Shelley Chen has posted comments on this change by Garen Wu. ( https://review.coreboot.org/c/coreboot/+/83465?usp=email ) Change subject: mb/google/brox/var/greenbayupoc: update ALC236 verb table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83465?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9a8248c4a437fd204f40918d801a4a010a5c4df Gerrit-Change-Number: 83465 Gerrit-PatchSet: 1 Gerrit-Owner: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:54:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83354?usp=email to look at the new patch set (#32). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock List of changes: 1. Add required Pather Lake SoC programming till bootblock. 2. Include only required headers into include/soc. 3. Include PTL related DID, BDF. 4. Ref: Processor EDS documents vol0.51 #815002 BUG=b:348678529 TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard. Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com> --- A src/soc/intel/pantherlake/Kconfig A src/soc/intel/pantherlake/Makefile.mk A src/soc/intel/pantherlake/bootblock/bootblock.c A src/soc/intel/pantherlake/bootblock/pcd.c A src/soc/intel/pantherlake/bootblock/report_platform.c A src/soc/intel/pantherlake/espi.c A src/soc/intel/pantherlake/include/soc/bootblock.h A src/soc/intel/pantherlake/include/soc/iomap.h A src/soc/intel/pantherlake/include/soc/p2sb.h A src/soc/intel/pantherlake/include/soc/pci_devs.h A src/soc/intel/pantherlake/include/soc/pcr_ids.h A src/soc/intel/pantherlake/include/soc/pm.h A src/soc/intel/pantherlake/include/soc/smbus.h A src/soc/intel/pantherlake/include/soc/soc_info.h A src/soc/intel/pantherlake/soc_info.c 15 files changed, 1,271 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 32 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

1 0

[XS] Change in coreboot[main]: mb/google/brox/var/brox: Enable Class-D calibration
by Shelley Chen (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Karthik Ramasubramanian, Paul Menzel, Subrata Banik, Terry Cheong. Shelley Chen has posted comments on this change by Terry Cheong. ( https://review.coreboot.org/c/coreboot/+/82794?usp=email ) Change subject: mb/google/brox/var/brox: Enable Class-D calibration ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82794?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I776f5c24ce3c829cbd64840957c1431608cf2b85 Gerrit-Change-Number: 82794 Gerrit-PatchSet: 7 Gerrit-Owner: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Terry Cheong <htcheong(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:54:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Subrata Banik (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun. Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 31: (1 comment) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83354/comment/0ef3b3ca_f84a1f3d?us… : PS14, Line 67: ~1KiB) > The stack allocated by the bootloader must be large enough for both FSP-M as well as any other parent function calls that are still on the stack at the point when FspMemoryInit() is called. > Keeping this, it would be best to have FSP-M stack in CAR larger than 256KB. I would request to update the fsp integration guide to actual numbers rather keeping something that is never tested. I ran into boot issue with stack size < 512KB with RMT being enabled. this is the exact doc issue we have seen with ADL, MTL and now with PTL. I have asked FSP team to share the max stack req rather saying what is minimum req -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 31 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:30:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove USB Type-C port setting
by Pranava Y N (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik. Pranava Y N has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/83707?usp=email ) Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/nova/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83707/comment/0fddc1c4_8063196e?us… : PS1, Line 37: > we should keep other tcss ports also disable or empty? I guess there are 4 ports. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:29:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove USB Type-C port setting
by Pranava Y N (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Rishika Raj, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83707?usp=email to look at the new patch set (#2). Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting ...................................................................... mb/google/brya/var/nova: Remove USB Type-C port setting Update the devicetree to remove USB Type-C port related setting as the design doesn't include a USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 9 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83707/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 2 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
by Saurabh Mishra (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun. Saurabh Mishra has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email ) Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock ...................................................................... Patch Set 31: (1 comment) File src/soc/intel/pantherlake/Kconfig: https://review.coreboot.org/c/coreboot/+/83354/comment/6d75fd49_c0c0dd29?us… : PS14, Line 67: ~1KiB) > Hi Subrata, i have checked with FSP Team, as per the MTL FSP Integration guide, the FSP Stack and He […] The stack allocated by the bootloader must be large enough for both FSP-M as well as any other parent function calls that are still on the stack at the point when FspMemoryInit() is called. Keeping this, it would be best to have FSP-M stack in CAR larger than 256KB. -- To view, visit https://review.coreboot.org/c/coreboot/+/83354?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca Gerrit-Change-Number: 83354 Gerrit-PatchSet: 31 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Sanju Jose Thottan <sanjujose.thottan(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-CC: Vikrant L Jadeja <vikrant.l.jadeja(a)intel.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Saurabh Mishra <mishra.saurabh(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove USB Type-C port setting
by Subrata Banik (Code Review) 31 Jul '24

31 Jul '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Rishika Raj. Subrata Banik has posted comments on this change by Pranava Y N. ( https://review.coreboot.org/c/coreboot/+/83707?usp=email ) Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/nova/overridetree.cb: https://review.coreboot.org/c/coreboot/+/83707/comment/0692d3f0_c7687a42?us… : PS1, Line 37: we should keep other tcss ports also disable or empty? I guess there are 4 ports. -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 31 Jul 2024 15:14:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: soc/intel, pci_ids: Add Intel UHD Graphics 610 DID
by Maxim (Code Review) 31 Jul '24

31 Jul '24

Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83708?usp=email ) Change subject: soc/intel, pci_ids: Add Intel UHD Graphics 610 DID ...................................................................... soc/intel, pci_ids: Add Intel UHD Graphics 610 DID https://web.archive.org/web/20240731145507/https:// linux-hardware.org/?id=pci:8086-9ba8-103c-8768 Test: $ cbmem -c * * * [DEBUG] CPU: Intel(R) Celeron(R) G5905 CPU @ 3.50GHz [DEBUG] CPU: ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 9b73 (rev 03) is CometLake-S G0/G1 (2+2) [DEBUG] PCH: device id 0687 (rev 00) is Cometlake-H Q470 [DEBUG] IGD: device id 9ba8 (rev 03) is CometLake ULT GT1 * * * Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83708/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8b2de41..fdbff82 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4174,6 +4174,7 @@ #define PCI_DID_INTEL_CML_GT2_ULT_2 0x9B4A #define PCI_DID_INTEL_CML_GT1_ULT_3 0x9B2B #define PCI_DID_INTEL_CML_GT1_ULT_4 0x9B2C +#define PCI_DID_INTEL_CML_GT1_ULT_6 0x9BA8 #define PCI_DID_INTEL_CML_GT2_ULT_5 0x9BAA #define PCI_DID_INTEL_CML_GT2_ULT_8 0x9BAC #define PCI_DID_INTEL_CML_GT2_ULT_6 0x9BCA diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index c062746..02ec8b3 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -136,6 +136,7 @@ { PCI_DID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" }, { PCI_DID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" }, + { PCI_DID_INTEL_CML_GT1_ULT_6, "CometLake ULT GT1" }, { PCI_DID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f1e7d7e..6024cf3 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -393,6 +393,7 @@ PCI_DID_INTEL_CML_GT2_ULT_2, PCI_DID_INTEL_CML_GT1_ULT_3, PCI_DID_INTEL_CML_GT1_ULT_4, + PCI_DID_INTEL_CML_GT1_ULT_6, PCI_DID_INTEL_CML_GT2_ULT_5, PCI_DID_INTEL_CML_GT2_ULT_6, PCI_DID_INTEL_CML_GT2_ULT_7, -- To view, visit https://review.coreboot.org/c/coreboot/+/83708?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Gerrit-Change-Number: 83708 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim <max.senia.poliak(a)gmail.com>

1 0

[S] Change in coreboot[main]: mb/google/brya/var/nova: Remove USB Type-C port setting
by Pranava Y N (Code Review) 31 Jul '24

31 Jul '24

Pranava Y N has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83707?usp=email ) Change subject: mb/google/brya/var/nova: Remove USB Type-C port setting ...................................................................... mb/google/brya/var/nova: Remove USB Type-C port setting Update the devicetree to remove USB Type-C port related setting as the design doesn't include a USB-C port. BUG=b:348332200 TEST=Able to build google/nova Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Signed-off-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 8 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/83707/1 diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index 950bb9b..e68ea1d 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -5,6 +5,7 @@ register "sagv" = "SaGv_Enabled" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Genesys USB2 Hub register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 @@ -30,6 +31,10 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Disable Type-A port register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port + register "tcss_ports[0]" = "TCSS_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -247,42 +252,16 @@ device ref gspi1 off end device ref pch_espi on chip ec/google/chromeec - use conn0 as mux_conn[0] device pnp 0c09.0 on end end end - device ref pmc hidden - chip drivers/intel/pmc_mux - device generic 0 on - chip drivers/intel/pmc_mux/conn - use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port - device generic 0 alias conn0 on end - end - end - end - end - device ref tcss_xhci on - chip drivers/usb/acpi - device ref tcss_root_hub on - chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" - device ref tcss_usb3_port1 on end - end - end - end - end + device ref pmc hidden end device ref xhci on chip drivers/usb/acpi device ref xhci_root_hub on chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C0 (MLB)"" - register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(1, 0))" + register "desc" = ""USB2 Genesys Hub"" + register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/83707?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b4025bea41f67224ac35ff2077b1394f2c3e380 Gerrit-Change-Number: 83707 Gerrit-PatchSet: 1 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com>

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
303
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2024