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Change subject: mb/lenovo/t420: Use vendor default power limits
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Do we know if Lenovo always used the same numbers? i.e. irrespective […]
Would be good to check the values when using a dual-core CPU and a quad-core CPU
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Change subject: mb: source site-local mainboard Kconfig.name and Kconfig files
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Patch Set 2: Code-Review+2
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Change subject: mb/lenovo/t420: Use vendor default power limits
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Do we know if Lenovo always used the same numbers? i.e. irrespective
of the installed CPU model?
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Change subject: cpu/intel/model_206ax: Allow turbo boost ratio limit configuration
......................................................................
Patch Set 5: Code-Review+1
(3 comments)
File src/cpu/intel/model_206ax/chip.h:
https://review.coreboot.org/c/coreboot/+/83271/comment/4e1a817f_e1408818?us… :
PS5, Line 63: int turbo_ratio_limit_4c; /* Turbo Ratio Limit for 4 cores acrive */
An array might look better?
File src/cpu/intel/model_206ax/model_206ax.h:
https://review.coreboot.org/c/coreboot/+/83271/comment/101ab793_7f0894e0?us… :
PS5, Line 49:
The tabs are spurious at this point, please remove.
Alternatively, how about shortening the name? e.g.
`PLATFORM_INFO_SET_TURBO_LIMITS` seems to fit.
File src/cpu/intel/model_206ax/model_206ax_init.c:
https://review.coreboot.org/c/coreboot/+/83271/comment/0bd80844_233a284d?us… :
PS5, Line 333: BIOS_NOTICE
It's expected to be like this on most processors, isn't it? Then it should
be `BIOS_INFO` at most.
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Change subject: Make Ada a first class citizen
......................................................................
Patch Set 16:
(1 comment)
File Makefile.inc:
https://review.coreboot.org/c/coreboot/+/13044/comment/b9864717_1c68a715?us… :
PS16, Line 362: +=
> isn't `ADAFLAGS_common := -gnatg -gnatp`?
I don't understand the question.
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Change subject: mb/protectli/vault_adl_p: Add initial support for VP6630/VP6650/VP6670
......................................................................
Patch Set 8: Code-Review+1
(2 comments)
File src/mainboard/protectli/vault_adl_p/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/3f791baa_3ca990e8?us… :
PS7, Line 41: polarity << pin
> Prepared a patch with a generic ITE SIo GPIO driver: CB:83355
Acknowledged
File src/mainboard/protectli/vault_adl_p/mainboard.c:
https://review.coreboot.org/c/coreboot/+/80501/comment/1a3f907b_c1febd63?us… :
PS7, Line 29: }
> Exported it to a header file as static inline function
Why inline, though? We can add as many C files as we want. Inline only bloats
the binary.
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Change subject: soc/intel/alderlake/tcss: Add definition of IOM_READY bit
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Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Any idea where this is documented? I wonder why nobody else ran into this yet.
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