Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83700?usp=email )
Change subject: soc/amd/common/psp_smm: introduce and use send_psp_command_smm
......................................................................
soc/amd/common/psp_smm: introduce and use send_psp_command_smm
When sending mailbox commands to the PSP from SMM, the SMM flag needs to
be set right before sending the mailbox command and cleared right after
the command is sent. In order to not have this code duplicated, factor
it out into a function.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83700
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/psp/psp_smm.c
1 file changed, 13 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index eecdf02..8fcf80f 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -47,6 +47,17 @@
smm_flag = 0;
}
+static int send_psp_command_smm(u32 command, void *buffer)
+{
+ int cmd_status;
+
+ set_smm_flag();
+ cmd_status = send_psp_command(command, buffer);
+ clear_smm_flag();
+
+ return cmd_status;
+}
+
/*
* The MBOX_BIOS_CMD_SMM_INFO PSP mailbox command doesn't necessarily need be sent from SMM,
* but doing so allows the linker to sort out the addresses of c2p_buffer, p2c_buffer and
@@ -83,9 +94,7 @@
printk(BIOS_DEBUG, "PSP: Notify SMM info... ");
- set_smm_flag();
- cmd_status = send_psp_command(MBOX_BIOS_CMD_SMM_INFO, &buffer);
- clear_smm_flag();
+ cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SMM_INFO, &buffer);
/* buffer's status shouldn't change but report it if it does */
psp_print_cmd_status(cmd_status, &buffer.header);
@@ -113,9 +122,7 @@
buffer->sleep_type = sleep_type;
- set_smm_flag();
- cmd_status = send_psp_command(MBOX_BIOS_CMD_SX_INFO, buffer);
- clear_smm_flag();
+ cmd_status = send_psp_command_smm(MBOX_BIOS_CMD_SX_INFO, buffer);
/* buffer's status shouldn't change but report it if it does */
psp_print_cmd_status(cmd_status, &buffer->header);
--
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Gerrit-Change-Id: I3628463dece9d11703d5a068fe7c604108b69c1f
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83699?usp=email )
Change subject: soc/amd/common/psp_smm: add comments to psp_notify_smm
......................................................................
soc/amd/common/psp_smm: add comments to psp_notify_smm
The reasoning behind this and the positive side effects of this aren't
too clear from the code, so point those out in a comment.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4f4121031fc1ef600cdf5551f61f1ef4e03b56a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83699
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/psp/psp_smm.c
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
Matt DeVillier: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index 114cf12..eecdf02 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -47,6 +47,13 @@
smm_flag = 0;
}
+/*
+ * The MBOX_BIOS_CMD_SMM_INFO PSP mailbox command doesn't necessarily need be sent from SMM,
+ * but doing so allows the linker to sort out the addresses of c2p_buffer, p2c_buffer and
+ * smm_flag without us needing to pass this info between ramstage and smm. In the PSP gen2 case
+ * this will also make sure that the PSP MMIO base will be cached in SMM before the OS takes
+ * over so no SMN accesses will be needed during OS runtime.
+ */
int psp_notify_smm(void)
{
msr_t msr;
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83698?usp=email )
Change subject: soc/amd/common/psp_smm: add/improve comments to buffers and flags
......................................................................
soc/amd/common/psp_smm: add/improve comments to buffers and flags
Since it's not exactly obvious what 'c2p_buffer', 'p2c_buffer' and
'smm_flag' are used for, add comments to those.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4ec092a92fe9f0686ffb7103e441802fc05381f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83698
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
---
M src/soc/amd/common/block/psp/psp_smm.c
1 file changed, 14 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Matt DeVillier: Looks good to me, approved
diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c
index 2112e86..114cf12 100644
--- a/src/soc/amd/common/block/psp/psp_smm.c
+++ b/src/soc/amd/common/block/psp/psp_smm.c
@@ -14,15 +14,28 @@
#define C2P_BUFFER_MAXSIZE 0xc00 /* Core-to-PSP buffer */
#define P2C_BUFFER_MAXSIZE 0xc00 /* PSP-to-core buffer */
+/*
+ * When sending PSP mailbox commands to the PSP from the SMI handler after the boot done
+ * command was sent, the corresponding data buffer needs to be placed in this core to PSP (C2P)
+ * buffer.
+ */
struct {
u8 buffer[C2P_BUFFER_MAXSIZE];
} __aligned(32) c2p_buffer;
+/*
+ * When the PSP sends mailbox commands to the host, it will update the PSP to core (P2C) buffer
+ * and then send an SMI to the host to process the request.
+ */
struct {
u8 buffer[P2C_BUFFER_MAXSIZE];
} __aligned(32) p2c_buffer;
-static uint32_t smm_flag; /* Non-zero for SMM, clear when not */
+/*
+ * When sending PSP mailbox commands to the PSP from the SMI handler, the SMM flag needs to be
+ * set for the PSP to accept it. Otherwise it should be cleared.
+ */
+static uint32_t smm_flag;
static void set_smm_flag(void)
{
--
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Attention is currently required from: Jeremy Soller, Tim Crawford.
Hello Jeremy Soller, build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61410?usp=email
to look at the new patch set (#7).
The following approvals got outdated and were removed:
Code-Review+2 by coreboot org, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: mb/system76/bonw14: Enable TAS5825M smart amp
......................................................................
mb/system76/bonw14: Enable TAS5825M smart amp
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer.
Smart AMP data was collected using a logic analyzer connected to the IC
during system start on proprietary firmware. This data is then used to
generate a C file [1].
[1]: https://github.com/system76/smart-amp
Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9
Signed-off-by: Tim Crawford <tcrawford(a)system76.com>
---
M src/mainboard/system76/bonw14/Kconfig
M src/mainboard/system76/bonw14/Makefile.mk
M src/mainboard/system76/bonw14/devicetree.cb
A src/mainboard/system76/bonw14/tas5825m-normal.c
A src/mainboard/system76/bonw14/tas5825m-sub.c
A src/mainboard/system76/bonw14/tas5825m.c
6 files changed, 2,507 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/61410/7
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Elyes Haouas has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/63716?usp=email )
Change subject: [RFC]util/cbfstool: Rewrite trampoline in C
......................................................................
Patch Set 4:
(2 comments)
File util/cbfstool/x86_linux_trampoline.c:
https://review.coreboot.org/c/coreboot/+/63716/comment/dee880b4_b74a9826?us… :
PS4, Line 5: <stdint.h>
duplicated as <types.h> provides stdint
https://review.coreboot.org/c/coreboot/+/63716/comment/63d00e6e_30ee89b6?us… :
PS4, Line 6: <commonlib/bsd/compiler.h>
is always automatically included in all compilation units.
See `git grep -F 'compiler.h' $(find -type f -name "*.mk")`
`nano +893 Documentation/contributing/coding_style.md`
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Change subject: mb/google/dedede/var/awasuki: Disable SD card
......................................................................
Patch Set 1: Code-Review+2
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Sean Rhodes has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83621?usp=email )
Change subject: mb/starlabs/*: Add the subsystem ids for HDA
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83621/comment/3e0888c6_433b6032?us… :
PS1, Line 9: so
: set these to allow the driver to install.
> fix wrapping
Done
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Hello Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83621?usp=email
to look at the new patch set (#2).
Change subject: mb/starlabs/*: Add the subsystem ids for HDA
......................................................................
mb/starlabs/*: Add the subsystem ids for HDA
The Windows drivers require the subsystem ID to match on the PCI
device, so set these to allow the driver to install.
Change-Id: I01b36554d5322018efc72734a8e749cc06263577
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
---
M src/mainboard/starlabs/lite/variants/glk/devicetree.cb
M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb
M src/mainboard/starlabs/starbook/variants/adl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/cml/devicetree.cb
M src/mainboard/starlabs/starbook/variants/kbl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/rpl/devicetree.cb
M src/mainboard/starlabs/starbook/variants/tgl/devicetree.cb
7 files changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83621/2
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Change subject: mb/google/dedede/var/awasuki: Enable ELAN touchscreen with fw_config
......................................................................
Patch Set 5:
(3 comments)
File src/mainboard/google/dedede/variants/awasuki/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83704/comment/73083ec5_3b43d640?us… :
PS5, Line 1: fw_config
: field TOUCH 5
: option TOUCH_ABSENT 0
: option TOUCH_PRESENT 1
: end
: end
Please move this to variants/baseboard/devicetree.cb along with other fw_config. In dedede, all the programs shared the same FW_CONFIG bitfields.
Also please rename TOUCH as TOUCHSCREEN for clarity.
File src/mainboard/google/dedede/variants/awasuki/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83704/comment/e96d4b24_3bb5fe3a?us… :
PS5, Line 9: /* H4 : AP_I2C_TS_SDA */
: PAD_NC(GPP_H4, NONE),
: /* H5 : AP_I2C_TS_SCL */
: PAD_NC(GPP_H5, NONE),
Also you need to configure ENABLE, Reset and Stop/Report GPIOs as NC so that they are not floating or leaking power.
https://review.coreboot.org/c/coreboot/+/83704/comment/e8dc9046_5106d6f6?us… :
PS5, Line 24: if (!fw_config_probe(FW_CONFIG(TOUCH, TOUCH_PRESENT))) {
: cfg->SerialIoI2cMode[PchSerialIoIndexI2C2] = PchSerialIoDisabled;
: }
:
: if (!fw_config_probe(FW_CONFIG(TOUCH, TOUCH_PRESENT))) {
: printk(BIOS_INFO, "Disable TS GPIO pins.\n");
: gpio_configure_pads(ts_disable_pad, ARRAY_SIZE(ts_disable_pad));
: }
Both the if blocks can be combined into one.
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