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Change subject: mb/starlabs/starbook/rpl: Disconnect SCI/SMI GPIOs
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Patch Set 2: Code-Review+2
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Change subject: mb/starlabs/starbook/rpl: Disconnect wireless GPIOs
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Patch Set 2: Code-Review+2
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Change subject: mb/starlabs/starbook/rpl: Set I2C0 speed to fast
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Patch Set 2: Code-Review+2
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Change subject: ec/starlabs/merlin: Remove ITE mirror functionality
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Patch Set 1: Code-Review+2
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Change subject: soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83686/comment/254ef735_c9afe00e?us… :
PS2, Line 9: The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
: enabled and the system is currently booting from the RO section.
> We are intentionally initiating the synchronization process to validate the upstream process, even when the current CSE version matches the CBFS-stored CSE version, hence its `enforcing`.
>
> Please let me know if you would like me to rephrase the description.
We are intentionally initiating the CSE sync process to validate the coreboot update/downgrade logic, even when the current CSE RW version matches the CBFS-stored CSE version, hence its enforcement.
There could be scenarios where CSE updater logic in coreboot has been modified, but for in-field devices, we are not upreving the CSE RW FW. In practice, we are only able to test CSE updater logic when we have different CSE blobs (a version uprev/downgrade). Now assume that the CSE blob has not been changed between months, but the code logic that manages the uprev has been updated. How can we ensure that the modified CSE logic in coreboot will be able to handle any future CSE uprev scenario unless it is tested? This CL introduces a GBB that ensures that we are primarily testing two cases:
1. coreboot CSE update logic, as we modify cse_lite.c much more frequently than we actually uprev the CSE blob
2. The ability to boot to the OS after a successful erase/write/read of the CSE RW partition.
Can we add a detailed commit msg and test steps like this to ensure reviewers follow what this CL tries to achieve?
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Change subject: soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
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Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83686/comment/f0c55d59_5c7ef96c?us… :
PS2, Line 7: src:
> Wrong prefix?
Acknowledged
https://review.coreboot.org/c/coreboot/+/83686/comment/b0f2272d_1b4882fe?us… :
PS2, Line 9: The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
: enabled and the system is currently booting from the RO section.
> Why is enforcing this the right thing to do?
We are intentionally initiating the synchronization process to validate the upstream process, even when the current CSE version matches the CBFS-stored CSE version, hence its `enforcing`.
Please let me know if you would like me to rephrase the description.
https://review.coreboot.org/c/coreboot/+/83686/comment/c5ac6544_f5cfa31d?us… :
PS2, Line 13: CL:5705989
> It’s not marked up in the upstream Gerrit. Please add a URL.
This is a downstream patch. I took out the CL details from the description because the existing description and patch comments has sufficient information.
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Change subject: soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
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Patch Set 3:
(1 comment)
Patchset:
PS1:
> there should be vboot dependency. we need to land the other changes in vboot repo then uprev the vboot git as part of coreboot to land this CL.
i could see vboot CL has landed now. can you please now push a vboot uprev CL in submodules then i assume this CL will able to pass build test.
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83686?usp=email
to look at the new patch set (#3).
Change subject: soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
......................................................................
soc/intel/common/block/cse: Enforce CSE sync with pertinent GBB flag
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
enabled and the system is currently booting from the RO section.
Additionally, it integrates forced CSE sync into eSOL decision-making.
BUG=b:353053317
TEST=Verified forced CSE sync on rex0 with GBB 0x200000
Cq-Depend: chromium:5718196
Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 30 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83686/3
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