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Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ia390035cdd591c1d31fd2e28ad53e63d16e91a37
Signed-off-by: Bharath N <quic_bharn(a)quicinc.com>
---
M sc7180/qtiseclib/Release_Notes.txt
M sc7180/qtiseclib/libqtisec.a
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/05/83305/2
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Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
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Change subject: soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83314/comment/da3724d3_bc8a2dd7?us… :
PS3, Line 8:
Please add the source for these ids, like datasheet name, revision.
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/c52920c1_3f887865?us… :
PS4, Line 100: This structure holds the DLL configuration
: register values that will be programmed by RC.
: Those policies should be used by platform if default values
: provided by RC are not sufficient to provide stable operation
: at all supported speed modes. RC will blindly set the DLL values
: as provided in this structure.
Line breaks make it harder to read.
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/a64c824b_66b3bbbf?us… :
PS4, Line 29: This file is automatically generated. Please do NOT modify !!!
Please add to the commit message, how it was generated.
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Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
Patch Set 4:
(1 comment)
File src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h:
https://review.coreboot.org/c/coreboot/+/83192/comment/e8c0b16f_c4081f84?us… :
PS4, Line 3: Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
Is that up to date?
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Bharath N has uploaded this change for review. ( https://review.coreboot.org/c/qc_blobs/+/83348?usp=email )
Change subject: sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
......................................................................
sc7180/qtiseclib: Update qtiseclib blobs binaries and release notes from 69 to 71
TEST=Validated on qualcomm sc7180 development board
Change-Id: I5eaac050198effac681d3f87cb868ad92eebe622
Signed-off-by: Bharath N <bharn(a)qualcomm.corp-partner.google.com>
---
M sc7180/qtiseclib/Release_Notes.txt
M sc7180/qtiseclib/libqtisec.a
2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/qc_blobs refs/changes/48/83348/1
diff --git a/sc7180/qtiseclib/Release_Notes.txt b/sc7180/qtiseclib/Release_Notes.txt
index 018797c..f10e15d 100644
--- a/sc7180/qtiseclib/Release_Notes.txt
+++ b/sc7180/qtiseclib/Release_Notes.txt
@@ -1,4 +1,21 @@
-=================== Release 00050 ================================
+=================== Release 00071 ================================
+This Release Notes file covers these blobs:
+ * libqtisec.a
+
+Version : 00071
+
+Release Date : June 26, 2024
+
+Supported Silicon : SC7180
+
+Changes since last version :
+ * Support for ACR and NSACR in SMMU
+
+No special instructions, requirements or dependencies, files must be
+present in this folder to be pulled in during coreboot build
+
+Errata : Nothing to report
+=================== Release 00069 ================================
This Release Notes file covers these blobs:
* libqtisec.a
diff --git a/sc7180/qtiseclib/libqtisec.a b/sc7180/qtiseclib/libqtisec.a
index 2ab2c7b..8751fbd 100644
--- a/sc7180/qtiseclib/libqtisec.a
+++ b/sc7180/qtiseclib/libqtisec.a
Binary files differ
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Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/brya/variants/bujia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/83302/comment/4a98454d_010b999c?us… :
PS4, Line 86: CHARGER
> Any reason for removing Charger control (throttling input charging current) in new code change?
modify done. thanks
https://review.coreboot.org/c/coreboot/+/83302/comment/99b906d7_d0afdeac?us… :
PS4, Line 66: CPU
> Any reason for changing the sensor0 name from DRAM to CPU? We have DPTF_CPU available and used in ac […]
got it, i modify to that add new two tsr
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Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shon Wang, Subrata Banik.
Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83302?usp=email
to look at the new patch set (#8).
Change subject: mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
......................................................................
mb/google/brask/var/bujia: Hook up two missing sensors for wireless and memory
Bujia has 4 thermal sensors, so add two missing sensors settings.
BUG=b:327549688
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/bujia/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/83302/8
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