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Change subject: acpi/acpigen_ps2_keybd: Fix keymaps size calculation
......................................................................
Patch Set 8:
This change is ready for review.
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Change subject: soc/intel/xeon_sp: Add acpigen_write_pci_root_port
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/82252/comment/f65f6cd1_bbd8e3e2?us… :
PS6, Line 192: PCI_SECONDARY_BUS
> I checked the SPR log, the empty but enabled root port will also be assigned with secondary bus numb […]
Can the check be dropped?
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Change subject: commonlib/device_tree.c: Fix results length check
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83085/comment/ef051de5_0b3f2265?us… :
PS4, Line 11:
Paste the wrong warning and mention the board you saw this with?
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Change subject: mb/system76/mtl: darp10: Add TCSS configs
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83696/comment/a8453bbe_751f9f44?us… :
PS1, Line 10:
Any other log messages from Linux or so?
File src/mainboard/system76/mtl/variants/darp10/ramstage.c:
https://review.coreboot.org/c/coreboot/+/83696/comment/56f2bce1_b70513d0?us… :
PS1, Line 10: BIT 6 is orientational
So it’s 0 below in 0x82. What orientation is it?
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Change subject: device/path: rename domain path struct element to 'domain_id'
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Patch Set 3: Code-Review+1
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Change subject: mb/google/nissa: Create teliks variant
......................................................................
Patch Set 18:
(1 comment)
File src/mainboard/google/brya/variants/teliks/overridetree.cb:
PS18:
> Should this be left out in the beginning and only later add it, or is it already so similar to *anra […]
Yes, teliks is the successor of anraggar, the biggest difference is the CPU model. The GPIO configuration has not changed.
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Hello Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83354?usp=email
to look at the new patch set (#30).
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Verified+1 by build bot (Jenkins)
Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
......................................................................
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=verified on Panther Lake Simics PSS using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh(a)intel.com>
---
A src/soc/intel/pantherlake/Kconfig
A src/soc/intel/pantherlake/Makefile.mk
A src/soc/intel/pantherlake/bootblock/bootblock.c
A src/soc/intel/pantherlake/bootblock/pcd.c
A src/soc/intel/pantherlake/bootblock/report_platform.c
A src/soc/intel/pantherlake/espi.c
A src/soc/intel/pantherlake/include/soc/bootblock.h
A src/soc/intel/pantherlake/include/soc/iomap.h
A src/soc/intel/pantherlake/include/soc/p2sb.h
A src/soc/intel/pantherlake/include/soc/pci_devs.h
A src/soc/intel/pantherlake/include/soc/pcr_ids.h
A src/soc/intel/pantherlake/include/soc/pm.h
A src/soc/intel/pantherlake/include/soc/smbus.h
A src/soc/intel/pantherlake/include/soc/soc_info.h
A src/soc/intel/pantherlake/soc_info.c
15 files changed, 1,270 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83354/30
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Change subject: mb/google/brox/var/brox: Enable Class-D calibration
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82794/comment/ec4d9253_c51cdab9?us… :
PS2, Line 10: based
: on the updated verb table provided by Realtek
> Included the bug and comment number as well.
Done
https://review.coreboot.org/c/coreboot/+/82794/comment/8eb65d4a_1a338ce8?us… :
PS2, Line 15: TEST=Verify DC offset of speaker amplier is less than 3mV
> How? And what value did you measure?
Actually it is DC offset value of the speaker output pins, we directly pull those out in hardware and measured with multimeter. Added description in the test field.
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Change subject: soc/amd/common/smi_util: add PSP SMI helper functions
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83702/comment/98a61ec9_cb329946?us… :
PS2, Line 12: to its
*in* its?
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