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Change subject: security/vboot: Include new gbb flag to enforce CSE sync
......................................................................
Patch Set 2: Code-Review+2
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Change subject: src: Enforce CSE sync with pertinent GBB flag
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83686/comment/5105fd91_fce9491d?us… :
PS1, Line 13: CB
> `CL` […]
Acknowledged
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/83686/comment/0461b9fc_19a0adc6?us… :
PS1, Line 776: - CSE Update not required
> This condition is not handled here, so please either move the condition here, or remove this line of […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/83686/comment/8ff70742_48038e7c?us… :
PS1, Line 1068: if (is_cse_sync_enforced()) {
> Is this supposed to be called only if `cse_compare_sub_part_version` returns 0 (as we're doing in th […]
The parent function `is_cse_fw_update_required()` determines if cse sync is needed, if yes then it displays `ealry sign of life screen`.
At this particular point, we are not worried if its a downgrade, upgrade or a forced cse sync.
So first we verify if `is_cse_sync_enforced()` is true. If so, there's no need to compare CSE versions.
However, during the CSE sync process, we assess if it's a downgrade or upgrade by comparing the stored RO and CBFS CSE versions.
If the versions match (ret == 0), we then check the possibility of an enforced CSE sync.
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Hello Julius Werner, Subrata Banik, Yu-Ping Wu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83685?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: security/vboot: Include new gbb flag to enforce CSE sync
......................................................................
security/vboot: Include new gbb flag to enforce CSE sync
This patch adds a GBB flag to coreboot, which, when enabled, enforces
CSE sync even if the current CSE version matches the version in CBFS.
The CSME sync GBB and flag are designed to enhance autotest
functionalities and are not intended or recommended for use in
developing any other features.
BUG=b:353053317
TEST=futility gbb --help
Cq-Depend: chromium:5718196
Change-Id: I6352959e1e898a90b4c6e12a22f8d6513f90ded9
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/security/vboot/Kconfig
M src/security/vboot/Makefile.mk
2 files changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/83685/2
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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83686?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: src: Enforce CSE sync with pertinent GBB flag
......................................................................
src: Enforce CSE sync with pertinent GBB flag
The patch enforces CSE sync when the GBB flag GBB_FLAG_FORCE_CSE_SYNC is
enabled and the system is currently booting from the RO section.
Additionally, it integrates forced CSE sync into eSOL decision-making.
This patch is an enhancement of CL:5705989 featuring the new GBB flag.
BUG=b:353053317
TEST=Verified forced CSE sync on rex0 with GBB 0x200000
Cq-Depend: chromium:5718196
Change-Id: I228bc8ebf58719776f6c39e0bfbb7ad53d9bfb7f
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 30 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83686/2
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Anil Kumar K has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/81920?usp=email )
Change subject: drivers/soundwire: Support Realtek ALC722 codec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> > Agree with refactor suggestion !! […]
thanks Subrata. will check and update this CL
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83695?usp=email )
Change subject: mb/google/trulo: Keep ISH default enable
......................................................................
mb/google/trulo: Keep ISH default enable
This patch drops fw_config probing for ISH because ISH IP should
remains on by default for all Trulo variants.
Additionally, removed the redundant ISH entries from variant
override devicetree.
BUG=b:354607924
TEST=Able to verify ISH PCI Device is available while booting eMMC sku.
```
lspci
00:00.0 Host bridge: Intel Corporation Device 461c
...
00:12.0 Serial controller: Intel Corporation Device 54fc
...
00:1a.0 SD Host controller: Intel Corporation Device 54c4
```
Also, able to enter S0ix with this patch.
```
> suspend_stress_test -c 1 --ignore_s0ix_substates
At AP console:
s0ix errors: 0
s0ix substate errors: 0
s0ix pc10 errors: 0
At EC console:
power state 5 = S0ix, in 0x38d87
```
Change-Id: Ic1e415ec848ac91a9bbf21b26597f4e6b5f7a1f5
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83695
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: V Sowmya <v.sowmya(a)intel.com>
Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
M src/mainboard/google/brya/variants/orisa/overridetree.cb
M src/mainboard/google/brya/variants/trulo/overridetree.cb
3 files changed, 6 insertions(+), 16 deletions(-)
Approvals:
Amanda Hwang: Looks good to me, approved
build bot (Jenkins): Verified
V Sowmya: Looks good to me, approved
Eric Lai: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
index f048dbb..8e1093a 100644
--- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
+++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
@@ -45,6 +45,12 @@
device ref igpu on end
device ref dtt on end
device ref tcss_xhci on end
+ device ref ish on
+ chip drivers/intel/ish
+ register "add_acpi_dma_property" = "true"
+ device generic 0 on end
+ end
+ end
device ref xhci on end
device ref shared_sram on end
device ref heci1 on end
diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb
index 92909ab..0a58b3d 100644
--- a/src/mainboard/google/brya/variants/orisa/overridetree.cb
+++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb
@@ -512,14 +512,6 @@
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_EMMC
end
- device ref ish on
- chip drivers/intel/ish
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
- end
- probe STORAGE STORAGE_UNKNOWN
- probe STORAGE STORAGE_UFS
- end
device ref ufs on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb
index 3ae9f85..d7fca12 100644
--- a/src/mainboard/google/brya/variants/trulo/overridetree.cb
+++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb
@@ -518,14 +518,6 @@
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_EMMC
end
- device ref ish on
- chip drivers/intel/ish
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
- end
- probe STORAGE STORAGE_UNKNOWN
- probe STORAGE STORAGE_UFS
- end
device ref ufs on
probe STORAGE STORAGE_UNKNOWN
probe STORAGE STORAGE_UFS
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