coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3527 discussions

[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Jan Philipp Groß (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Jan Philipp Groß. Hello Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82760?usp=email to look at the new patch set (#2). Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) This is a rudimentary port of this board. It was done with Haswell Autoport, wherein some adjustments for Broadwell were made (Thanks to Angel Pons!). The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version 2.20 of the vendor firmware. Working: - Broadwell MRC.bin - Libgfxinit - HDMI - DVI-I - Rear USB ports (with the exception of the top-most USB-2-port) - mPCIe SSD - mPCIe WiFi slot - x16 PCIe slot - edk2 Not yet tested: - SATA ports - Ethernet - DisplayPort - PS/2 keyboard/mouse - USB 2.0 header - USB 3.0 header - Audio header Not working: - Broadwell CPUs (refer to Angel Pons Z97 Extreme 6 port for further info) Special thanks to Angel Pons for guiding me through the process of porting this board and pushing it to Gerrit! Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z97e-itx_ac/Kconfig A src/mainboard/asrock/z97e-itx_ac/Kconfig.name A src/mainboard/asrock/z97e-itx_ac/Makefile.mk A src/mainboard/asrock/z97e-itx_ac/acpi/ec.asl A src/mainboard/asrock/z97e-itx_ac/acpi/platform.asl A src/mainboard/asrock/z97e-itx_ac/acpi/superio.asl A src/mainboard/asrock/z97e-itx_ac/board_info.txt A src/mainboard/asrock/z97e-itx_ac/bootblock.c A src/mainboard/asrock/z97e-itx_ac/data.vbt A src/mainboard/asrock/z97e-itx_ac/devicetree.cb A src/mainboard/asrock/z97e-itx_ac/dsdt.asl A src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads A src/mainboard/asrock/z97e-itx_ac/gpio.c A src/mainboard/asrock/z97e-itx_ac/hda_verb.c A src/mainboard/asrock/z97e-itx_ac/romstage.c 15 files changed, 473 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/82760/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org>

1 0

[S] Change in coreboot[main]: sconfig: Provide simple constants for aliased devices
by Nico Huber (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Martin L Roth. Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82764?usp=email ) Change subject: sconfig: Provide simple constants for aliased devices ...................................................................... sconfig: Provide simple constants for aliased devices Expose aliased PCI and PNP devices as `pci_/pnp_devfn_t` constants in <static_devices.h>. They will be named `_sdev_<alias>` to have a underscore prefix for consistency and to not collide with the `struct device` objects (with `_dev_` prefix). Change-Id: I2d1cfe12b1e7309f8235c84dd220bd090ebfe1b5 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M util/sconfig/main.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/82764/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 04f78a4..741859f 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -1288,6 +1288,10 @@ /* Only devices on root bus here. */ if (ptr->bustype == PCI && ptr->parent->dev->bustype == DOMAIN) { + if (ptr->alias) { + fprintf(head, "static const pci_devfn_t _sdev_%s = PCI_DEV(%d, %d, %d);\n", + ptr->alias, ptr->parent->dev->path_a, ptr->path_a, ptr->path_b); + } fprintf(head, "extern DEVTREE_CONST struct device *const __pci_%d_%02x_%d;\n", ptr->parent->dev->path_a, ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *const __pci_%d_%02x_%d = &%s;\n", @@ -1303,6 +1307,10 @@ } if (ptr->bustype == PNP) { + if (ptr->alias) { + fprintf(head, "static const pnp_devfn_t _sdev_%s = PNP_DEV(0x%02x, 0x%04x);\n", + ptr->alias, ptr->path_a, ptr->path_b); + } fprintf(head, "extern DEVTREE_CONST struct device *const __pnp_%04x_%02x;\n", ptr->path_a, ptr->path_b); fprintf(fil, "DEVTREE_CONST struct device *const __pnp_%04x_%02x = &%s;\n", @@ -1917,6 +1925,8 @@ { fprintf(dev, "#ifndef __STATIC_DEVICES_H\n"); fprintf(dev, "#define __STATIC_DEVICES_H\n\n"); + fprintf(dev, "#include <device/pci_type.h>\n"); + fprintf(dev, "#include <device/pnp_type.h>\n"); fprintf(dev, "#include <device/device.h>\n\n"); fprintf(dev, "/* expose_device_names */\n"); walk_device_tree(gen, dev, &base_root_dev, expose_device_names); -- To view, visit https://review.coreboot.org/c/coreboot/+/82764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d1cfe12b1e7309f8235c84dd220bd090ebfe1b5 Gerrit-Change-Number: 82764 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[XS] Change in coreboot[main]: sb/intel/smbus: Implement smbus_send_byte()
by Nico Huber (Code Review) 02 Jun '24

02 Jun '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82763?usp=email ) Change subject: sb/intel/smbus: Implement smbus_send_byte() ...................................................................... sb/intel/smbus: Implement smbus_send_byte() Change-Id: Ic368ef379039b104064c9a91474b188646388dd2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/common/smbus.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/82763/1 diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index 1594e68..944e360 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -253,7 +253,8 @@ host_outb(base, SMBHSTCMD, address); /* Set the data bytes... */ - host_outb(base, SMBHSTDAT0, data & 0xff); + if (ctrl >= I801_BYTE_DATA) + host_outb(base, SMBHSTDAT0, data & 0xff); if (ctrl == I801_WORD_DATA) host_outb(base, SMBHSTDAT1, data >> 8); @@ -354,6 +355,11 @@ return smbus_read_cmd(base, I801_WORD_DATA, device, address); } +int do_smbus_send_byte(uintptr_t base, u8 device, u8 data) +{ + return smbus_write_cmd(base, I801_BYTE, device, data, 0x00); +} + int do_smbus_write_byte(uintptr_t base, u8 device, u8 address, u8 data) { return smbus_write_cmd(base, I801_BYTE_DATA, device, address, data); -- To view, visit https://review.coreboot.org/c/coreboot/+/82763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic368ef379039b104064c9a91474b188646388dd2 Gerrit-Change-Number: 82763 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

[S] Change in coreboot[main]: console/i2c_smbus: Allow to send data w/o register offset
by Nico Huber (Code Review) 02 Jun '24

02 Jun '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82762?usp=email ) Change subject: console/i2c_smbus: Allow to send data w/o register offset ...................................................................... console/i2c_smbus: Allow to send data w/o register offset Not every I2C target requires a register address. Not sending one for every console char saves us a lot of overhead. Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/console/Kconfig M src/drivers/smbus/i2c_smbus_console.c 2 files changed, 16 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/82762/1 diff --git a/src/console/Kconfig b/src/console/Kconfig index 30b2862..db71204 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -318,8 +318,16 @@ help I2C address of the device which logs the data. +config CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER + bool "Write to a specific data register" + default y if SC16IS7XX_INIT + help + Select this to provide a register address that will + be sent before every data byte. + config CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER hex "Data register address of the I2C logging device" + depends on CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER default 0x00 if SC16IS7XX_INIT help This an 8-bit data register. diff --git a/src/drivers/smbus/i2c_smbus_console.c b/src/drivers/smbus/i2c_smbus_console.c index d651790..00b5393 100644 --- a/src/drivers/smbus/i2c_smbus_console.c +++ b/src/drivers/smbus/i2c_smbus_console.c @@ -13,7 +13,12 @@ void i2c_smbus_console_tx_byte(unsigned char c) { - do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, - CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, - CONFIG_CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER, c); + if (CONFIG(CONSOLE_I2C_SMBUS_HAVE_DATA_REGISTER)) { + do_smbus_write_byte(CONFIG_FIXED_SMBUS_IO_BASE, + CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, + CONFIG_CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER, c); + } else { + do_smbus_send_byte(CONFIG_FIXED_SMBUS_IO_BASE, + CONFIG_CONSOLE_I2C_SMBUS_SLAVE_ADDRESS, c); + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/82762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c714768fdd4aea4885e40a85d21fa42414ce32c Gerrit-Change-Number: 82762 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

[XS] Change in coreboot[main]: console: Fix I2C/SMBus console if it's the only slow one
by Nico Huber (Code Review) 02 Jun '24

02 Jun '24

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82761?usp=email ) Change subject: console: Fix I2C/SMBus console if it's the only slow one ...................................................................... console: Fix I2C/SMBus console if it's the only slow one Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/console/console.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/82761/1 diff --git a/src/include/console/console.h b/src/include/console/console.h index 7e9a439..8d1a5c5 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -72,7 +72,8 @@ #define HAS_ONLY_FAST_CONSOLES !(CONFIG(SPKMODEM) || CONFIG(CONSOLE_QEMU_DEBUGCON) || \ CONFIG(CONSOLE_SERIAL) || CONFIG(CONSOLE_NE2K) || CONFIG(CONSOLE_USB) || \ CONFIG(EM100PRO_SPI_CONSOLE) || CONFIG(CONSOLE_SPI_FLASH) || \ - CONFIG(CONSOLE_SYSTEM76_EC) || CONFIG(CONSOLE_AMD_SIMNOW)) + CONFIG(CONSOLE_SYSTEM76_EC) || CONFIG(CONSOLE_AMD_SIMNOW) || \ + CONFIG(CONSOLE_I2C_SMBUS)) #else static inline int get_log_level(void) { return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/82761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie44fdac6904a4467e408882bb8a5e08e6ff73f32 Gerrit-Change-Number: 82761 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Angel Pons (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Jan Philipp Groß. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82760?usp=email ) Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: Welcome to coreboot Gerrit! -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Comment-Date: Sun, 02 Jun 2024 22:40:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Jan Philipp Groß (Code Review) 02 Jun '24

02 Jun '24

Jan Philipp Groß has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82760?usp=email ) Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Signed-off-by: Jan Philipp Groß <jeangrande(a)mailbox.org> --- A src/mainboard/asrock/z97e-itx_ac/Kconfig A src/mainboard/asrock/z97e-itx_ac/Kconfig.name A src/mainboard/asrock/z97e-itx_ac/Makefile.mk A src/mainboard/asrock/z97e-itx_ac/acpi/ec.asl A src/mainboard/asrock/z97e-itx_ac/acpi/platform.asl A src/mainboard/asrock/z97e-itx_ac/acpi/superio.asl A src/mainboard/asrock/z97e-itx_ac/board_info.txt A src/mainboard/asrock/z97e-itx_ac/bootblock.c A src/mainboard/asrock/z97e-itx_ac/data.vbt A src/mainboard/asrock/z97e-itx_ac/devicetree.cb A src/mainboard/asrock/z97e-itx_ac/dsdt.asl A src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads A src/mainboard/asrock/z97e-itx_ac/gpio.c A src/mainboard/asrock/z97e-itx_ac/hda_verb.c A src/mainboard/asrock/z97e-itx_ac/romstage.c 15 files changed, 473 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/82760/1 diff --git a/src/mainboard/asrock/z97e-itx_ac/Kconfig b/src/mainboard/asrock/z97e-itx_ac/Kconfig new file mode 100644 index 0000000..13a4a45 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/Kconfig @@ -0,0 +1,24 @@ +if BOARD_ASROCK_Z97E_ITX_AC + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select USE_BROADWELL_MRC if !USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + default "asrock/z97e-itx_ac" + +config MAINBOARD_PART_NUMBER + default "Z97E-ITX/ac" + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/asrock/z97e-itx_ac/Kconfig.name b/src/mainboard/asrock/z97e-itx_ac/Kconfig.name new file mode 100644 index 0000000..7d87119 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z97E_ITX_AC + bool "Z97E-ITX/ac" diff --git a/src/mainboard/asrock/z97e-itx_ac/Makefile.mk b/src/mainboard/asrock/z97e-itx_ac/Makefile.mk new file mode 100644 index 0000000..513c347 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z97e-itx_ac/acpi/ec.asl b/src/mainboard/asrock/z97e-itx_ac/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z97e-itx_ac/acpi/platform.asl b/src/mainboard/asrock/z97e-itx_ac/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z97e-itx_ac/acpi/superio.asl b/src/mainboard/asrock/z97e-itx_ac/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z97e-itx_ac/board_info.txt b/src/mainboard/asrock/z97e-itx_ac/board_info.txt new file mode 100644 index 0000000..10ca265 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z97E-ITXac/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2014 diff --git a/src/mainboard/asrock/z97e-itx_ac/bootblock.c b/src/mainboard/asrock/z97e-itx_ac/bootblock.c new file mode 100644 index 0000000..1cec5c4 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/bootblock.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/lynxpoint/pch.h> + +/* FIXME: remove this if not needed */ +void mainboard_config_superio(void) +{ +} diff --git a/src/mainboard/asrock/z97e-itx_ac/data.vbt b/src/mainboard/asrock/z97e-itx_ac/data.vbt new file mode 100644 index 0000000..5f2f92b --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z97e-itx_ac/devicetree.cb b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb new file mode 100644 index 0000000..6804b17 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/devicetree.cb @@ -0,0 +1,96 @@ +chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx + register "ec_present" = "false" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "usb_xhci_on_resume" = "false" + + chip cpu/intel/haswell + device cpu_cluster 0x0 on + ops haswell_cpu_bus_ops + end + end + + device domain 0x0 on + ops haswell_pci_domain_ops + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gen4_dec" = "0x00000000" + register "gpe0_en_1" = "0x40002046" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8cb1 + end + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a1 + subsystemid 0x1849 0x15a1 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8cad + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1150 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1849 0x8c90 + end + device pci 1c.1 on # PCIe Port #2 + end + device pci 1c.2 on # PCIe Port #3 + end + device pci 1c.3 on # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 + end + device pci 1c.5 on # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 + end + device pci 1c.7 on # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8ca6 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8cc4 + end + device pci 1f.2 on # SATA Controller (AHCI) + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8ca2 + end + device pci 1f.5 off # SATA Controller (Legacy) + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 + subsystemid 0x1849 0x0c01 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + end +end diff --git a/src/mainboard/asrock/z97e-itx_ac/dsdt.asl b/src/mainboard/asrock/z97e-itx_ac/dsdt.asl new file mode 100644 index 0000000..e8c6e53 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + /* FIXME: remove this if the board doesn't have backlight. */ + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads b/src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z97e-itx_ac/gpio.c b/src/mainboard/asrock/z97e-itx_ac/gpio.c new file mode 100644 index 0000000..6c1c6cc --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/gpio.c @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_NATIVE, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z97e-itx_ac/hda_verb.c b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c new file mode 100644 index 0000000..8a3c78f --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491150, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491150), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z97e-itx_ac/romstage.c b/src/mainboard/asrock/z97e-itx_ac/romstage.c new file mode 100644 index 0000000..fde45ca --- /dev/null +++ b/src/mainboard/asrock/z97e-itx_ac/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + /* FIXME: check this */ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0110, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0140, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org>

1 0

[M] Change in coreboot[main]: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions
by Paul Menzel (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Nicholas Chin, Vladimir Serbinenko. Paul Menzel has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82722/comment/23b854d7_470d99f2?us… : PS7, Line 8: > Not really related. I did it for volteer chromebook and will upload new vbt after I test it. […] Thank you for replying so quickly. I meant, you also had to upgrade due to the FSP update, and FSP not supporting the older VBT version 240? -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 8 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Jun 2024 21:14:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Vladimir Serbinenko <phcoder(a)gmail.com>

1 0

[M] Change in coreboot[main]: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions
by Paul Menzel (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Nicholas Chin, Vladimir Serbinenko. Paul Menzel has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: Add a tool to upgrade VBT files to newer versions ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82722/comment/de8a7e7d_b5b56b72?us… : PS8, Line 8: Am I understanding the code correctly, that currently two versions are supported? 240 and 250? -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 8 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Jun 2024 19:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: superio/ite/it8728f: Support setting power state after power failure
by Paul Menzel (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Felix Held, Joel Linn, Nicholas Sudsgaard, Vladimir Serbinenko. Paul Menzel has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82737?usp=email ) Change subject: superio/ite/it8728f: Support setting power state after power failure ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3dcc4f032bc5f629fb916c4122beb8dc096bab20 Gerrit-Change-Number: 82737 Gerrit-PatchSet: 3 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Sun, 02 Jun 2024 19:32:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2024