coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell)
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Jan Philipp Groß, Máté Kukri, Nicholas Chin. Angel Pons has posted comments on this change by Jan Philipp Groß. ( https://review.coreboot.org/c/coreboot/+/82760?usp=email ) Change subject: mb/asrock: Add Z97E-ITX/ac (Haswell/Broadwell) ...................................................................... Patch Set 2: Code-Review+1 (28 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82760/comment/fffc03dc_160989e0?us… : PS2, Line 9: This is a rudimentary port of this board. It was done with Haswell Autoport, wherein some adjustments for Broadwell were made (Thanks to Angel Pons!). nit: Commit message lines should be at most 72 characters long, wrap long lines to fit. https://review.coreboot.org/c/coreboot/+/82760/comment/36a3c5e9_2f07fc5c?us… : PS2, Line 34: - Broadwell CPUs (refer to Angel Pons Z97 Extreme 6 port for further info) You could reference the commit in question: ``` - Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6: Add new mainboard) ``` https://review.coreboot.org/c/coreboot/+/82760/comment/6455d868_a7fc7047?us… : PS2, Line 36: nit: One empty line is enough to separate paragraphs https://review.coreboot.org/c/coreboot/+/82760/comment/6a8495d9_ee804673?us… : PS2, Line 39: nit: One empty line is enough to separate paragraphs File src/mainboard/asrock/z97e-itx_ac/Kconfig: https://review.coreboot.org/c/coreboot/+/82760/comment/7f34137f_ec3b5d81?us… : PS2, Line 5: select BOARD_ROMSIZE_KB_8192 Add this and check if DVI-to-VGA works ```suggestion select BOARD_ROMSIZE_KB_8192 select GFX_GMA_ANALOG_I2C_HDMI_B ``` File src/mainboard/asrock/z97e-itx_ac/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82760/comment/5a582ac7_1349cff8?us… : PS2, Line 1: chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx : register "ec_present" = "false" Remove this line: ```suggestion chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx ``` https://review.coreboot.org/c/coreboot/+/82760/comment/f7f32dfb_bfea0c96?us… : PS2, Line 7: : register "usb_xhci_on_resume" = "false" Remove this line: ```suggestion register "gpu_dp_d_hotplug" = "4" ``` https://review.coreboot.org/c/coreboot/+/82760/comment/e7a972f0_9974957d?us… : PS2, Line 16: device domain 0x0 on ```suggestion device domain 0 on ``` https://review.coreboot.org/c/coreboot/+/82760/comment/3050e861_4f258228?us… : PS2, Line 19: : register "docking_supported" = "0" 1. Fix the comment 2. Remove the `docking_supported` line ```suggestion chip southbridge/intel/lynxpoint # Intel 9 Series Lynx Point PCH ``` https://review.coreboot.org/c/coreboot/+/82760/comment/66999d34_859c6694?us… : PS2, Line 23: : register "gen4_dec" = "0x00000000" ```suggestion register "gen3_dec" = "0x000c0251" ``` https://review.coreboot.org/c/coreboot/+/82760/comment/04a0cb9e_be42c17f?us… : PS2, Line 25: : register "gpe0_en_2" = "0x0" ```suggestion register "gpe0_en_1" = "0x40002046" ``` https://review.coreboot.org/c/coreboot/+/82760/comment/44a7d1f8_91cab1c9?us… : PS2, Line 33: device pci 16.0 off # Management Engine Interface 1 : end I presume the ME wasn't working properly when you ran autoport? This device should be enabled (coreboot will disable it if the ME isn't working). Also, you can shorten the comment. And if there's nothing inside a device, you can write it on a single line (use tabs so that comments align): ```suggestion device pci 16.0 on end # MEI #1 ``` https://review.coreboot.org/c/coreboot/+/82760/comment/58c18193_e5d67a91?us… : PS2, Line 35: device pci 16.1 off # Management Engine Interface 2 : end This one should remain disabled, but you can still do the cosmetic clean-up: ```suggestion device pci 16.1 off end # MEI #2 ``` https://review.coreboot.org/c/coreboot/+/82760/comment/4b274294_d33db5c1?us… : PS2, Line 37: device pci 16.2 off # Management Engine IDE-R : end : device pci 16.3 off # Management Engine KT : end IIRC, coreboot complains about these devices not existing. I believe they only exist on Corporate (big) ME firmware SKUs (used by B-prefix and Q-prefix PCHs), whereas Z97 uses Consumer (small) ME firmware without AMT. TL;DR you can remove these. If unsure, send me a coreboot log *before* removing the devices. https://review.coreboot.org/c/coreboot/+/82760/comment/b4c97a39_c2d9b8b8?us… : PS2, Line 41: device pci 19.0 on # Intel Gigabit Ethernet Unsupported PCI device 8086:15a1 ```suggestion device pci 19.0 on # Intel Gigabit Ethernet ``` https://review.coreboot.org/c/coreboot/+/82760/comment/2066e128_a57bf308?us… : PS2, Line 50: device pci 1c.0 on # PCIe Port #1 : subsystemid 0x1849 0x8c90 : end : device pci 1c.1 on # PCIe Port #2 : end : device pci 1c.2 on # PCIe Port #3 : end : device pci 1c.3 on # PCIe Port #4 : end : device pci 1c.4 on # PCIe Port #5 : end : device pci 1c.5 on # PCIe Port #6 : end : device pci 1c.6 on # PCIe Port #7 : end : device pci 1c.7 on # PCIe Port #8 : end I find it really odd that only the first root port has a subsystem ID. The two hex numbers are "subsystem vendor ID" and "subsystem device ID", respectively. Looks like Asrock programs subsystem IDs so that subsystem vendor ID is "Asrock" and subsystem device ID is the same as the PCI device ID of the device. For the root ports, the IDs are sequential, incrementing by 2 each time. So: ```suggestion device pci 1c.0 on # PCIe Port #1 subsystemid 0x1849 0x8c90 end device pci 1c.1 on # PCIe Port #2 subsystemid 0x1849 0x8c92 end device pci 1c.2 on # PCIe Port #3 subsystemid 0x1849 0x8c94 end device pci 1c.3 on # PCIe Port #4 subsystemid 0x1849 0x8c96 end device pci 1c.4 on # PCIe Port #5 subsystemid 0x1849 0x8c98 end device pci 1c.5 on # PCIe Port #6 subsystemid 0x1849 0x8c9a end device pci 1c.6 on # PCIe Port #7 subsystemid 0x1849 0x8c9c end device pci 1c.7 on # PCIe Port #8 subsystemid 0x1849 0x8c9e end ``` But I know at least one of these root ports has to be off because `device pci 19.0` is enabled, which takes away one of the chipset's eight lanes. More investigation needed Also, if you have the time, figuring out which root ports correspond to what connectors would be nice. `lspci -nntv` is quite useful for this. Of course, you need to plug devices in. https://review.coreboot.org/c/coreboot/+/82760/comment/954f3118_b12dd373?us… : PS2, Line 86: device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 ```suggestion device pci 01.0 on # PEG ``` https://review.coreboot.org/c/coreboot/+/82760/comment/c79e1455_0ffd8bf5?us… : PS2, Line 89: device pci 02.0 on # Internal graphics VGA controller ```suggestion device pci 02.0 on # iGPU ``` https://review.coreboot.org/c/coreboot/+/82760/comment/eff3ab69_9e17a5ba?us… : PS2, Line 82: : device pci 00.0 on # Desktop Host bridge : subsystemid 0x1849 0x0c00 : end : device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0c01 : subsystemid 0x1849 0x0c01 : end : device pci 02.0 on # Internal graphics VGA controller : subsystemid 0x1849 0x0412 : end : device pci 03.0 on # Mini-HD audio : subsystemid 0x1849 0x0c0c : end Move these devices above `chip southbridge/intel/lynxpoint` They're *north*bridge devices, so they should be "north of" (above) *south*bridge devices 😄 File src/mainboard/asrock/z97e-itx_ac/dsdt.asl: https://review.coreboot.org/c/coreboot/+/82760/comment/6010fa6a_62d53ae1?us… : PS2, Line 3: nit: Remove one blank line https://review.coreboot.org/c/coreboot/+/82760/comment/5d3b995c_a5a661bd?us… : PS2, Line 12: 0x20141018 /* OEM revision */ Please get rid of this autoport nonsense: ```suggestion 0x20141018 ``` https://review.coreboot.org/c/coreboot/+/82760/comment/bfd35b3c_ce8e8081?us… : PS2, Line 24: : #include <northbridge/intel/haswell/acpi/hostbridge.asl> : /* FIXME: remove this if the board doesn't have backlight. */ : #include <drivers/intel/gma/acpi/default_brightness_levels.asl> Fix the FIXME: ```suggestion { #include <northbridge/intel/haswell/acpi/hostbridge.asl> ``` File src/mainboard/asrock/z97e-itx_ac/gma-mainboard.ads: https://review.coreboot.org/c/coreboot/+/82760/comment/b8f52803_7c5843c5?us… : PS2, Line 11: -- FIXME: check this : ports : constant Port_List := : (DP1, : DP2, : DP3, : HDMI1, : HDMI2, : HDMI3, : Analog, : LVDS, : eDP); Try this: ```suggestion ports : constant Port_List := (DP2, -- DP HDMI1, -- DVI-I HDMI2, -- DP HDMI3, -- HDMI Analog, -- DVI-I others => Disabled); ``` It's the same port mapping as Z97 Extreme6, we know Asrock used the same port mapping for another board already. File src/mainboard/asrock/z97e-itx_ac/hda_verb.c: https://review.coreboot.org/c/coreboot/+/82760/comment/4086b4d0_9ee8d480?us… : PS2, Line 20: nit: Drop blank line File src/mainboard/asrock/z97e-itx_ac/romstage.c: https://review.coreboot.org/c/coreboot/+/82760/comment/0e616ae8_02f2f6bb?us… : PS2, Line 3: #include <stdint.h> Elyes said in another change that this doesn't seem to be used, so remove the line. https://review.coreboot.org/c/coreboot/+/82760/comment/f5cb685f_5a139b3c?us… : PS2, Line 10: : : /* FIXME: called after romstage_common, remove it if not used */ : void mb_late_romstage_setup(void) : { : } : We won't need this: ```suggestion } ``` https://review.coreboot.org/c/coreboot/+/82760/comment/48064939_dd228e02?us… : PS2, Line 18: : /* FIXME: check this */ : spdi->addresses[0] = 0x50; : spdi->addresses[1] = 0x51; : spdi->addresses[2] = 0x52; : spdi->addresses[3] = 0x53; Since there's two slots, the mapping should probably be this: ```suggestion { spdi->addresses[0] = 0x50; spdi->addresses[2] = 0x52; ``` You can check using something like `decode-dimms` https://review.coreboot.org/c/coreboot/+/82760/comment/12e27f67_0066c27a?us… : PS2, Line 27: /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ If USB ports work, I would remove the FIXME. The values seem reasonable. -- To view, visit https://review.coreboot.org/c/coreboot/+/82760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540 Gerrit-Change-Number: 82760 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Jan Philipp Groß <jeangrande(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 08:37:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: tree: Remove duplicated <arch/mmio.h>
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82693?usp=email to look at the new patch set (#2). Change subject: tree: Remove duplicated <arch/mmio.h> ...................................................................... tree: Remove duplicated <arch/mmio.h> <device/mmio.h> is supposed to chain-include <arch/mmio.h> Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/sifive/fu740/gpio.c M src/soc/sifive/fu740/sdram.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/82693/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66 Gerrit-Change-Number: 82693 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[L] Change in coreboot[main]: mb/dell: Add Latitude E6430 (Ivy Bridge)
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Felix Singer, Martin L Roth, Nicholas Chin, Paul Menzel. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/77444?usp=email ) Change subject: mb/dell: Add Latitude E6430 (Ivy Bridge) ...................................................................... Patch Set 14: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/77444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908 Gerrit-Change-Number: 77444 Gerrit-PatchSet: 14 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Iru Cai <mytbk920423(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 06:41:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Subrata Banik (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Subrata Banik has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/81038?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/81038/comment/d5c7b391_469ad0cb?us… : PS1, Line 113: select MRC_CACHE_USING_MRC_VERSION > currently ADL-N use FSP headers from 3rdpart repo. which dose not have FspProducerDataHeader.h file. without that ADL-N can't select this Kconfig. We will select this under SOC_INTEL_ALDERLAKE_PCH_N, once header is available in 3rdpart repo. inside `config SOC_INTEL_ALDERLAKE` ``` select MRC_CACHE_USING_MRC_VERSION if SOC_INTEL_ALDERLAKE_PCH_N ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 06:37:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[L] Change in coreboot[main]: mb/asrock: Add Z87E-ITX (Haswell)
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Máté Kukri, Nicholas Chin. Elyes Haouas has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/81022?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/asrock: Add Z87E-ITX (Haswell) ...................................................................... Patch Set 4: (1 comment) File src/mainboard/asrock/z87e-itx/romstage.c: https://review.coreboot.org/c/coreboot/+/81022/comment/bf8d74c5_9a45119f?us… : PS4, Line 3: #include <stdint.h> maybe stdint IS not used -- To view, visit https://review.coreboot.org/c/coreboot/+/81022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Gerrit-Change-Number: 81022 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 06:33:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: lib/device_tree.c: Fix wrong check for FDT validity
by Elyes Haouas (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Maximilian Brune. Elyes Haouas has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/82773?usp=email ) Change subject: lib/device_tree.c: Fix wrong check for FDT validity ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77c0e187b841e60965daac17025110181bdd32bc Gerrit-Change-Number: 82773 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 06:24:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox/var/lotso: Update gpio setting
by Jian Tong (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Eric Lai, Jian Tong, Kun Liu, Paul Menzel, Wentao Qin. Hello Eric Lai, Kun Liu, Wentao Qin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82573?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox/var/lotso: Update gpio setting ...................................................................... mb/google/brox/var/lotso: Update gpio setting Based on lotso EVT schematics update gpio settings. BUG=b:333494257 TEST=emerge-brox coreboot chromeos-bootimage and boot on Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Signed-off-by: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> --- A src/mainboard/google/brox/variants/lotso/Makefile.mk A src/mainboard/google/brox/variants/lotso/gpio.c 2 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82573/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/82573?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I13485cc7ccd8b15352f5e21ad9336aa2b3d35749 Gerrit-Change-Number: 82573 Gerrit-PatchSet: 13 Gerrit-Owner: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jian Tong <tongjian(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Attention: Wentao Qin <qinwentao(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/trulo/var/orisa: Configure TPM IRQ for orisa
by Eric Lai (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Amanda Hwang, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/82717?usp=email ) Change subject: mb/google/trulo/var/orisa: Configure TPM IRQ for orisa ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Gerrit-Change-Number: 82717 Gerrit-PatchSet: 3 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 05:43:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: chromeec: supporting reading long battery strings
by Peter Marheine (Code Review) 03 Jun '24

03 Jun '24

Peter Marheine has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82775?usp=email ) Change subject: chromeec: supporting reading long battery strings ...................................................................... chromeec: supporting reading long battery strings The Chrome EC currently supports two ways to read battery strings on ACPI platforms: * Read up to 8 bytes from EC shared memory BMFG, BMOD, ... * Send a EC_CMD_BATTERY_GET_STATIC host command and read strings from the response. This is assumed to be exclusively controlled by the OS, because host commands' use of buffers is prone to race conditions. To support readout of longer strings via ACPI mechanisms, this change adds support for EC_ACPI_MEM_STRINGS_FIFO (https://crrev.com/c/5581473) and allows ACPI firmware to read strings of arbitrary length (currently limited to 64 characters in the implementation) from the EC and to determine whether this function is supported by the EC (falling back to shared memory if not). BUG=b:339171261 TEST=on yaviks, the EC console logs FIFO readout messages when used in ACPI and correct strings are shown in the OS. If EC support is removed, correct strings are still shown in the OS. BRANCH=nissa Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04 Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> --- M src/ec/google/chromeec/acpi/battery.asl M src/ec/google/chromeec/acpi/ec.asl 2 files changed, 80 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/82775/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 5344111..b508995 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -54,6 +54,79 @@ Return (Local0) } +// Cached flag for BSRF FIFO readout support from EC. +Name(BRSS, 0xff) + +// Read extended battery strings from the selected battery. +// Arg0 = string index +// +// If supported by the EC, strings of arbitrary length are read using the +// FIFO readout method. Otherwise short (no more than 8 bytes) strings are +// read from the EC shared memory map. The desired battery index should be +// selected with BTSW before calling this method. +Method(BRSX, 1, Serialized) +{ + // It doesn't make sense to read the FIFO support indicator. + if (Arg0 == 0) + { + Return ("") + } + + If (BRSS == 0xff) + { + // Write 0 to BSRF to read back a support indicator; nonzero and + // non-0xFF if FIFO readout is supported, assuming minimum v1 support + // for strings 1 through 3. + BSRF = 0 + BRSS = BSRF + + // 0xff readback also means no support for FIFO readout, when the EC + // doesn't even know what this command is. + if (BRSS == 0xff) + { + BRSS = 0 + } + } + + // If FIFO readout through BSRF is not supported, fall back to reading + // the short strings in EMEM. + If (BRSS == 0) + { + If (Arg0 == 1) + { + Return (ToString (Concatenate (BMOD, 0))) + } + ElseIf (Arg0 == 2) + { + Return (ToString (Concatenate (BSER, 0))) + } + ElseIf (Arg0 == 3) + { + Return (ToString (Concatenate (BMFG, 0))) + } + Else + { + Return ("") + } + } + + // Select requested parameter to read + BSRF = Arg0 + + // Read to end of string, or up to a reasonable maximum length. Reads of + // BSRF consume bytes from the FIFO, so take care to read it only once + // per byte of data. + Local0 = "" + Local1 = BSRF + While (Local1 != 0 && SizeOf (Local0) < 32) + { + Local0 = Concatenate (Local0, ToString (Local1)) + Local1 = BSRF + } + + Return (Local0) +} + // _BIF implementation. // Arg0 = battery index // Arg1 = PBIF @@ -86,9 +159,9 @@ Arg1[6] = Local2 // Get battery info from mainboard - Arg1[9] = ToString(Concatenate(BMOD, 0x00)) - Arg1[10] = ToString(Concatenate(BSER, 0x00)) - Arg1[12] = ToString(Concatenate(BMFG, 0x00)) + Arg1[9] = BRSX (1) + Arg1[10] = BRSX (2) + Arg1[12] = BRSX (3) Release (^BATM) Return (Arg1) @@ -129,9 +202,9 @@ Arg1[8] = BTCC // Get battery info from mainboard - Arg1[16] = ToString(Concatenate(BMOD, 0x00)) - Arg1[17] = ToString(Concatenate(BSER, 0x00)) - Arg1[19] = ToString(Concatenate(BMFG, 0x00)) + Arg1[16] = BRSX (1) + Arg1[17] = BRSX (2) + Arg1[19] = BRSX (3) Release (^BATM) Return (Arg1) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index d6d33b2..741ad59 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -100,6 +100,7 @@ USPP, 8, // USB Port Power RFWU, 8, // Retimer Firmware Update PBOK, 8, // Power source change count from dptf + BSRF, 8, // Battery string readout FIFO } #if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) -- To view, visit https://review.coreboot.org/c/coreboot/+/82775?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia29cacb7d86402490f9ac458f0be50e3f2192b04 Gerrit-Change-Number: 82775 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Marheine <pmarheine(a)chromium.org>

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[XS] Change in coreboot[main]: mb/google/trulo/var/orisa: Configure TPM IRQ for orisa
by Amanda Hwang (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro. Amanda Hwang has posted comments on this change by Amanda Hwang. ( https://review.coreboot.org/c/coreboot/+/82717?usp=email ) Change subject: mb/google/trulo/var/orisa: Configure TPM IRQ for orisa ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/82717/comment/84ebb333_2e15b792?us… : PS1, Line 690: default 13 if !BOARD_GOOGLE_BASEBOARD_HADES && !BOARD_GOOGLE_ORISA # GPE0_DW0_13 (GPP_A13_IRQ) > Wondering if change the order can help or not? Does Kconfig return the first match? Yes, it looks like Kconfig does indeed return the first match. -- To view, visit https://review.coreboot.org/c/coreboot/+/82717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I065fdf2a66036c6df1e16dda3b2a684b5202cccc Gerrit-Change-Number: 82717 Gerrit-PatchSet: 2 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 05:35:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

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