coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Hello Kapil Porwal, Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82780?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00 ...................................................................... vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00 Update generated FSP headers for Alder Lake N from v5021.00 Changes include: - Add FspProducerDataHeader.h header file - Open Usb4CmMode & CnviWifiCore Upd in FspsUpd.h - Update UPD Offset in FspsUpd.h BUG=b:296433836 TEST=Able to build and boot google/nivviks Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspProducerDataHeader.h M src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h 2 files changed, 134 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/82780/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Gerrit-Change-Number: 82780 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T
by Leo Chou (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82782?usp=email to look at the new patch set (#2). Change subject: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T ...................................................................... spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x BRANCH=None BUG=344482259 Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M spd/lp4x/memory_parts.json M spd/lp4x/set-0/parts_spd_manifest.generated.txt M spd/lp4x/set-1/parts_spd_manifest.generated.txt 3 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82782/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb Gerrit-Change-Number: 82782 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[S] Change in coreboot[main]: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T
by Leo Chou (Code Review) 03 Jun '24

03 Jun '24

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82782?usp=email ) Change subject: spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T ...................................................................... spd/lp4x: Add SPD for Zilia SDVB8D8A34XGCL3N3T This adds support for Zilia SDVB8D8A34XGCL3N3T LP4x chips. Generatd SPD data with: util/spd_tools/bin/spd_gen spd/lp4x/memory_parts.json lp4x BRANCH=None BUG=344482259 Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M spd/lp4x/memory_parts.json M spd/lp4x/set-0/parts_spd_manifest.generated.txt M spd/lp4x/set-1/parts_spd_manifest.generated.txt M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/pujjoga/gpio.c M src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h 6 files changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/82782/1 diff --git a/spd/lp4x/memory_parts.json b/spd/lp4x/memory_parts.json index b0ec8b3..d4e0e9a 100644 --- a/spd/lp4x/memory_parts.json +++ b/spd/lp4x/memory_parts.json @@ -399,6 +399,18 @@ "ranksPerChannel": 1, "speedMbps": 4267 } + }, + { + "name": "SDVB8D8A34XGCL3N3T", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] } diff --git a/spd/lp4x/set-0/parts_spd_manifest.generated.txt b/spd/lp4x/set-0/parts_spd_manifest.generated.txt index f82c8bd..004d1bd 100644 --- a/spd/lp4x/set-0/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-0/parts_spd_manifest.generated.txt @@ -34,3 +34,4 @@ K4UCE3Q4AB-MGCL,spd-2.hex CXDB4ABAM-ML,spd-8.hex CXDB4CBAM-ML-A,spd-8.hex +SDVB8D8A34XGCL3N3T,spd-1.hex diff --git a/spd/lp4x/set-1/parts_spd_manifest.generated.txt b/spd/lp4x/set-1/parts_spd_manifest.generated.txt index 3a9201d..1604a11 100644 --- a/spd/lp4x/set-1/parts_spd_manifest.generated.txt +++ b/spd/lp4x/set-1/parts_spd_manifest.generated.txt @@ -34,3 +34,4 @@ K4UCE3Q4AB-MGCL,spd-2.hex CXDB4ABAM-ML,spd-11.hex CXDB4CBAM-ML-A,spd-11.hex +SDVB8D8A34XGCL3N3T,spd-5.hex diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 366d2dd..b1330d2 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -418,6 +418,7 @@ config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/pujjoga/gpio.c b/src/mainboard/google/brya/variants/pujjoga/gpio.c index cf5c9bd..880e3e3 100644 --- a/src/mainboard/google/brya/variants/pujjoga/gpio.c +++ b/src/mainboard/google/brya/variants/pujjoga/gpio.c @@ -35,7 +35,7 @@ /* E21 : NC */ PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG), /* F12 : WWAN_RST_L */ - PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + PAD_CFG_GPO(GPP_F12, 1, DEEP), /* H12 : NC */ PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG), /* H13 : NC */ @@ -89,6 +89,8 @@ PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C1 : SMBDATA ==> USI_RST_L */ PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/pujjoga/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4408e62ab2a15002960c1d9659ab6af45bd7f7bb Gerrit-Change-Number: 82782 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Sowmya Aralguppe (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Angel Pons, Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (4 comments) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/58e25fdc_260d725b?us… : PS10, Line 205: & > > Good point. […] ACK , using logical operator is the correct thing To check if either is 0 1) if (dw1 == 0 || dw2 == 0) or 2) if (!(dw0 && dw1)) IMO ,2 is optimized and hence preferred - please suggest Also will change the print message from debug to error https://review.coreboot.org/c/coreboot/+/82136/comment/3b58e179_ea8f4620?us… : PS10, Line 245: CPU_TRACE_HUB_BASE_ADDRESS > wondering why we are using temp base address here ? and how do we know if this temp access is not be […] We are using temp address because of the Si issue in ADL discussed in Partner isue To make sure fixed addresses does not conflict with the temp address - I have referred to FAS 626540 - section 6.5 (as mentioned in iomap.h) For dynamic allocation I checked PCIe device allocation in the serial log . Any workaround that needs to be done to overcome this issue should be in ADL/RPL only and not in the common code - this was the intention https://review.coreboot.org/c/coreboot/+/82136/comment/8ca51c8a_fa899741?us… : PS10, Line 246: printk(BIOS_DEBUG, "cpu_bar_addr for Crashlog device : 0x%X\n", cpu_bar_addr); > this is hardcoded value so why should we print the additional debug msg here ? ACK - just thought it will helpful for debugging - will remove https://review.coreboot.org/c/coreboot/+/82136/comment/c4f21ee2_fb4c885c?us… : PS10, Line 248: if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR0) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, cpu_bar_addr); : } else if (cpu_cl_devsc_cap.discovery_data.fields.t_bir_q == TEL_DVSEC_TBIR_BAR1) { : pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, cpu_bar_addr); : } else { : printk(BIOS_DEBUG, "invalid discovery data t_bir_q: 0x%x\n", : cpu_cl_devsc_cap.discovery_data.fields.t_bir_q); : return false; : } > WDYT ? […] The intention here is to write the temp address (cpu_bar_addr) in both PCI_BASE_ADDRESS_0 and PCI_BASE ADDRESS_1 so that when it is read back in cl_get_cpu_bar_addr function it reads the hardcoded address -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:42:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82780?usp=email ) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82780/comment/18febc55_c1fbe39c?us… : PS1, Line 12: - Add FspProducerDataHeader.h header file > are we sure, other header files can be reused between FSP uprevs ? I checked the ADLN Uprev task (327996213) no other headers are changed. Give me some time I will double confirm. -- To view, visit https://review.coreboot.org/c/coreboot/+/82780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Gerrit-Change-Number: 82780 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:05:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XL] Change in coreboot[main]: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"
by Subrata Banik (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Ronak Kanabar. Subrata Banik has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82779?usp=email ) Change subject: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files" ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82779/comment/e06e5161_a916f98c?us… : PS2, Line 13: the "IoT/AlderLakeN/" directory for these headers, but it is missing the crucial FspProducerDataHeader.h file. Without this header, the ADL-N platform is unable to utilize the appropriate MRC version needed for updating MRC caches. This patch aims to restore the necessary FSP headers for the ADL-N platform within the vendorcode directory. wrap up texts ? https://review.coreboot.org/c/coreboot/+/82779/comment/c9dc4c66_b63d9a80?us… : PS2, Line 14: missing signoff ? -- To view, visit https://review.coreboot.org/c/coreboot/+/82779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Gerrit-Change-Number: 82779 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:04:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Subrata Banik (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Subrata Banik has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/81038?usp=email ) Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... Patch Set 9: Code-Review+2 (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/81038/comment/9ef68632_8020989b?us… : PS1, Line 113: select MRC_CACHE_USING_MRC_VERSION > > currently ADL-N use FSP headers from 3rdpart repo. which dose not have FspProducerDataHeader. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:03:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Hello Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Subrata Banik, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81038?usp=email to look at the new patch set (#9). Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION This patch introduces support for storing the MRC cache based on the MRC version for both ADL-N and TWL platforms. It select the MRC_CACHE_USING_MRC_VERSION option when SOC_INTEL_ALDERLAKE_PCH_N is chosen. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81038/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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[M] Change in coreboot[main]: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
by Subrata Banik (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Ronak Kanabar. Subrata Banik has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82780?usp=email ) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00 ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82780/comment/2a198921_e0826ebc?us… : PS1, Line 12: - Add FspProducerDataHeader.h header file are we sure, other header files can be reused between FSP uprevs ? -- To view, visit https://review.coreboot.org/c/coreboot/+/82780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Gerrit-Change-Number: 82780 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:03:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Ronak Kanabar, V Sowmya. Hello Dinesh Gehlot, Kapil Porwal, Krishna P Bhat D, Nick Vaccaro, Subrata Banik, V Sowmya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81038?usp=email to look at the new patch set (#8). Change subject: soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION ...................................................................... soc/intel/alderlake: select Kconfig MRC_CACHE_USING_MRC_VERSION This patch is to add support to store MRC cache using MRC version in ADL-N & TWL. select MRC_CACHE_USING_MRC_VERSION if SOC_INTEL_ALDERLAKE_PCH_N selected. BUG=b:296433836 Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81038/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icc7e4ecd84a7d2818d54acc6ac5d0592544bb9ce Gerrit-Change-Number: 81038 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

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