coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3527 discussions

[XS] Change in coreboot[main]: mb/google/dedede/var/bookem: Add new supported memory part
by Leo Chou (Code Review) 03 Jun '24

03 Jun '24

Leo Chou has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82783?usp=email ) Change subject: mb/google/dedede/var/bookem: Add new supported memory part ...................................................................... mb/google/dedede/var/bookem: Add new supported memory part Add bookem new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Zilia SDVB8D8A34XGCL3N3T BUG=b:344482259 TEST=Use part_id_gen to generate related settings Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boten/memory/Makefile.mk M src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/82783/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Gerrit-Change-Number: 82783 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-CC: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: mb/google/dedede/var/boten: Add new supported memory part
by Leo Chou (Code Review) 03 Jun '24

03 Jun '24

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82783?usp=email ) Change subject: mb/google/dedede/var/boten: Add new supported memory part ...................................................................... mb/google/dedede/var/boten: Add new supported memory part Add bookem new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Zilia SDVB8D8A34XGCL3N3T BUG=b:344482259 TEST=Use part_id_gen to generate related settings Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/boten/memory/Makefile.mk M src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/82783/1 diff --git a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk index 892563e..3e34661 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk +++ b/src/mainboard/google/dedede/variants/boten/memory/Makefile.mk @@ -5,3 +5,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE, MT53E512M32D1NP-046 WT:B, K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-5.hex # ID = 1(0b0001) Parts = SDVB8D8A34XGCL3N3T diff --git a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt index 6a92eb9..6bd8527 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/dram_id.generated.txt @@ -9,3 +9,4 @@ H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AB-MGCL 0 (0000) +SDVB8D8A34XGCL3N3T 1 (0001) diff --git a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt index 86b3025..f8d0077 100644 --- a/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/boten/memory/mem_parts_used.txt @@ -3,3 +3,4 @@ H9HCNNNBKMMLXR-NEE MT53E512M32D1NP-046 WT:B K4U6E3S4AB-MGCL +SDVB8D8A34XGCL3N3T -- To view, visit https://review.coreboot.org/c/coreboot/+/82783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1cbf641e2bbe4fd4eea02a1bfa3d6b3c06e567e4 Gerrit-Change-Number: 82783 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>

1 0

[XS] Change in coreboot[main]: lib/device_tree.c: Fix wrong check for FDT validity
by Maximilian Brune (Code Review) 03 Jun '24

03 Jun '24

Maximilian Brune has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82773?usp=email ) Change subject: lib/device_tree.c: Fix wrong check for FDT validity ...................................................................... lib/device_tree.c: Fix wrong check for FDT validity Obviously one should return NULL if a FDT is not valid an not the other way around. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I77c0e187b841e60965daac17025110181bdd32bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/82773 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/lib/device_tree.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/lib/device_tree.c b/src/lib/device_tree.c index aff9e15..4f5cc07 100644 --- a/src/lib/device_tree.c +++ b/src/lib/device_tree.c @@ -608,7 +608,7 @@ const struct fdt_header *header = (const struct fdt_header *)blob; tree->header = header; - if (fdt_is_valid(blob)) + if (!fdt_is_valid(blob)) return NULL; uint32_t struct_offset = be32toh(header->structure_offset); -- To view, visit https://review.coreboot.org/c/coreboot/+/82773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77c0e187b841e60965daac17025110181bdd32bc Gerrit-Change-Number: 82773 Gerrit-PatchSet: 2 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

[S] Change in coreboot[main]: mb/google/brox: Fix CPU crashlog device MMIO memory access
by Angel Pons (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kane Chen, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Paul Menzel, Sowmya Aralguppe, Subrata Banik. Angel Pons has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/82136?usp=email ) Change subject: mb/google/brox: Fix CPU crashlog device MMIO memory access ...................................................................... Patch Set 10: (2 comments) File src/soc/intel/alderlake/crashlog.c: https://review.coreboot.org/c/coreboot/+/82136/comment/f23e4f0f_12e26589?us… : PS10, Line 205: & > ACK , using logical operator is the correct thing […] What if the address is below 4G (the high dword is zero, but the low dword is non-zero)? Is this a valid value? https://review.coreboot.org/c/coreboot/+/82136/comment/ce0c7050_315df61f?us… : PS10, Line 210: cpu_cl_disc_tab.header.data = (((u64)dw0) + ((u64)dw1 << 32)); Since this combines two 32-bit values into a 64-bit value, I would recommend using bitwise-OR `|` instead: ```suggestion cpu_cl_disc_tab.header.data = (((u64)dw0) | ((u64)dw1 << 32)); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82136?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I262254ee8d0eb91efcb3e748d121e13c31e66251 Gerrit-Change-Number: 82136 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:16:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[XS] Change in coreboot[main]: Revert "Makefile: Warn if flexible array members are not at the end"
by Maximilian Brune (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Elyes Haouas, Felix Singer, Jan Samek, Martin L Roth. Maximilian Brune has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82758?usp=email ) Change subject: Revert "Makefile: Warn if flexible array members are not at the end" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb Gerrit-Change-Number: 82758 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jan Samek <samekh(a)email.cz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:16:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82781?usp=email ) Change subject: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > please remove WIP Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Gerrit-Change-Number: 82781 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:12:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XS] Change in coreboot[main]: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82781?usp=email ) Change subject: intel/alderlake/Kconfig: Use vendorcode headers for Client ADL-N FSP ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/82781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ffcc3f284c213ff0533de3a0e228aacf523b380 Gerrit-Change-Number: 82781 Gerrit-PatchSet: 4 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:12:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82780?usp=email ) Change subject: vc/intel/fsp: Update ADL N FSP headers from v3343.05 to v5021.00 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82780/comment/292df209_4bd9ccb7?us… : PS1, Line 12: - Add FspProducerDataHeader.h header file > I checked the ADLN Uprev task (327996213) no other headers are changed. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb4cc8f2f83d8f6e821894f0ec2e56262a25743c Gerrit-Change-Number: 82780 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 11:01:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ronak Kanabar <ronak.kanabar(a)intel.com>

1 0

[XL] Change in coreboot[main]: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Kapil Porwal, Subrata Banik. Ronak Kanabar has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/82779?usp=email ) Change subject: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files" ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82779/comment/0203ceac_0d726d5e?us… : PS2, Line 13: the "IoT/AlderLakeN/" directory for these headers, but it is missing the crucial FspProducerDataHeader.h file. Without this header, the ADL-N platform is unable to utilize the appropriate MRC version needed for updating MRC caches. This patch aims to restore the necessary FSP headers for the ADL-N platform within the vendorcode directory. > wrap up texts ? Done https://review.coreboot.org/c/coreboot/+/82779/comment/2de6b8b7_6761de28?us… : PS2, Line 14: > missing signoff ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Gerrit-Change-Number: 82779 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Mon, 03 Jun 2024 10:59:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[XL] Change in coreboot[main]: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files"
by Ronak Kanabar (Code Review) 03 Jun '24

03 Jun '24

Attention is currently required from: Kapil Porwal, Ronak Kanabar. Hello Kapil Porwal, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82779?usp=email to look at the new patch set (#3). Change subject: Revert "vc/intel/fsp2/alderlake_n: Drop unused header files" ...................................................................... Revert "vc/intel/fsp2/alderlake_n: Drop unused header files" This reverts commit 79503ef515967ffceab7bd2a16a381e6a02c3d30. The Intel FSP repository at https://github.com/intel/FSP.git currently lacks the Client ADL-N headers. The existing coreboot code references the "IoT/AlderLakeN/" directory for these headers, but it is missing the crucial FspProducerDataHeader.h file. Without this header, the ADL-N platform is unable to utilize the appropriate MRC version needed for updating MRC caches. This patch aims to restore the necessary FSP headers for the ADL-N platform within the vendorcode directory. Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/alderlake_n/MemInfoHob.h 5 files changed, 7,655 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/82779/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I99e9d5a07b4ca8d1666e3fd50d3d363ed5d4618e Gerrit-Change-Number: 82779 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2024