coreboot-gerrit June 2024

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[XS] Change in coreboot[main]: tree: Use Wcalloc-transposed-args command option
by Elyes Haouas (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Elyes Haouas. Elyes Haouas has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/82658?usp=email ) Change subject: tree: Use Wcalloc-transposed-args command option ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/82658?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: revert Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I77b6f4d2eda487b087ba5665b588999633c33e8d Gerrit-Change-Number: 82658 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: Revert "tree: Use Wcalloc-transposed-args command option"
by Elyes Haouas (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Felix Singer. Hello Felix Singer, build bot (Jenkins), I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/82759?usp=email to review the following change. Change subject: Revert "tree: Use Wcalloc-transposed-args command option" ...................................................................... Revert "tree: Use Wcalloc-transposed-args command option" This reverts commit b3db3abd6311924930f3250c9f9fc3157fbbf7da. Reason for revert: `Wcalloc-transposed-args` is new command option came with GCC-14. older versions will not support it. Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f --- M Makefile.mk M src/southbridge/intel/common/rcba_pirq.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/82759/1 diff --git a/Makefile.mk b/Makefile.mk index e406702..0358c88 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -502,7 +502,6 @@ CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end -CFLAGS_common += -Wcalloc-transposed-args # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index ce44bc4..c9f1518 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -58,7 +58,7 @@ printk(BIOS_DEBUG, "Generating ACPI PIRQ entries\n"); - pin_irq_map = calloc(MAX_SLOTS * PCI_INT_MAX, sizeof(struct slot_pin_irq_map)); + pin_irq_map = calloc(sizeof(struct slot_pin_irq_map), MAX_SLOTS * PCI_INT_MAX); pirq_map.type = PIRQ_SOURCE_PATH; for (i = 0; i < PIRQ_COUNT; i++) snprintf(pirq_map.source_path[i], sizeof(pirq_map.source_path[i]), -- To view, visit https://review.coreboot.org/c/coreboot/+/82759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74ef8de1f7d38e1e0519c3b41e79fd9b11d8e16f Gerrit-Change-Number: 82759 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: Makefile: Warn if flexible array members are not at the end
by Elyes Haouas (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Elyes Haouas. Elyes Haouas has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/77147?usp=email ) Change subject: Makefile: Warn if flexible array members are not at the end ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/77147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: revert Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib704f7659d3b431ce7eebb4432c5b1a4272de3d2 Gerrit-Change-Number: 77147 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: Revert "Makefile: Warn if flexible array members are not at the end"
by Elyes Haouas (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Felix Singer, Jan Samek, Martin L Roth, Maximilian Brune. Hello Felix Singer, build bot (Jenkins), Martin L Roth, Maximilian Brune, Jan Samek, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/82758?usp=email to review the following change. Change subject: Revert "Makefile: Warn if flexible array members are not at the end" ...................................................................... Revert "Makefile: Warn if flexible array members are not at the end" This reverts commit f4acef92333913c0b7e4cd7813149bfb527c165c. Reason for revert: '-Wflex-array-member-not-at-end' is new command option came with GCC-14. older versions will not support it. Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb --- M Makefile.mk 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/82758/1 diff --git a/Makefile.mk b/Makefile.mk index 0358c88..e642ac7 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -501,7 +501,7 @@ CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie CFLAGS_common += -Wstring-compare ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -Wold-style-declaration -Wflex-array-member-not-at-end +CFLAGS_common += -Wold-style-declaration # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned -- To view, visit https://review.coreboot.org/c/coreboot/+/82758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I179d0bc0db3e863645ae4c87e1534c5c20025dfb Gerrit-Change-Number: 82758 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <samekh(a)email.cz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Jan Samek <samekh(a)email.cz>

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[NoOp] Change in coreboot[main]: mainboard/volteer: Update elemi data.vbt to 2.50
by Vladimir Serbinenko (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Nick Vaccaro. Hello Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82757?usp=email to look at the new patch set (#2). Change subject: mainboard/volteer: Update elemi data.vbt to 2.50 ...................................................................... mainboard/volteer: Update elemi data.vbt to 2.50 I used my vbt upgrader and then tested on my elemi and got graphics in payload with the latest FSP Change-Id: I47e97ee940f5678bbac5054e23a4569f0a0ff4b2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/google/volteer/variants/elemi/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/82757/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82757?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47e97ee940f5678bbac5054e23a4569f0a0ff4b2 Gerrit-Change-Number: 82757 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

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[NoOp] Change in coreboot[main]: mainboard/volteer: Update elemi data.vbt to 2.50
by Vladimir Serbinenko (Code Review) 02 Jun '24

02 Jun '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82757?usp=email ) Change subject: mainboard/volteer: Update elemi data.vbt to 2.50 ...................................................................... mainboard/volteer: Update elemi data.vbt to 2.50 I used my vbt upgrader and then tested on my elemi and got graphics in payload with the latest FSP Change-Id: I47e97ee940f5678bbac5054e23a4569f0a0ff4b2 --- M src/mainboard/google/volteer/variants/elemi/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/82757/1 diff --git a/src/mainboard/google/volteer/variants/elemi/data.vbt b/src/mainboard/google/volteer/variants/elemi/data.vbt index f3597e28..458bf46 100644 --- a/src/mainboard/google/volteer/variants/elemi/data.vbt +++ b/src/mainboard/google/volteer/variants/elemi/data.vbt Binary files differ -- To view, visit https://review.coreboot.org/c/coreboot/+/82757?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I47e97ee940f5678bbac5054e23a4569f0a0ff4b2 Gerrit-Change-Number: 82757 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com>

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[S] Change in coreboot[main]: mb/asus/p8z77-m: Update USB current map to match vendor
by Keith Hui (Code Review) 02 Jun '24

02 Jun '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82756?usp=email ) Change subject: mb/asus/p8z77-m: Update USB current map to match vendor ...................................................................... mb/asus/p8z77-m: Update USB current map to match vendor This board has used the USB current map from asus/p8z77-m_pro since it first landed in coreboot, which actually doesn't match vendor firmware. Apply values obtained from hardware while running vendor firmware to both native and MRC config. Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 2 files changed, 23 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/82756/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c index 47c5cb3..4656617 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/early_init.c @@ -14,16 +14,16 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { /* {enable, current, oc_pin} */ - {1, 2, 0}, /* Port 0: USB3 front internal header, top */ - {1, 2, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 8, 0}, /* Port 0: USB3 front internal header, top */ + {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ {1, 2, 1}, /* Port 2: USB3 rear, top */ {1, 2, 1}, /* Port 3: USB3 rear, bottom */ {1, 2, 2}, /* Port 4: USB2 rear, PS2 top */ {1, 2, 2}, /* Port 5: USB2 rear, PS2 bottom */ {1, 2, 3}, /* Port 6: USB2 rear, ETH, top */ {1, 2, 3}, /* Port 7: USB2 rear, ETH, bottom */ - {1, 2, 4}, /* Port 8: USB2 internal header USB910, top */ - {1, 2, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb index b3d05fe..45ad0e1 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb @@ -2,14 +2,30 @@ chip northbridge/intel/sandybridge register "usb_port_config" = "{ - {1, 0, 0x0080}, {1, 0, 0x0080}, {1, 1, 0x0080}, {1, 1, 0x0080}, {1, 2, 0x0080}, - {1, 2, 0x0080}, {1, 3, 0x0080}, {1, 3, 0x0080}, {1, 4, 0x0080}, {1, 4, 0x0080}, - {1, 6, 0x0080}, {1, 5, 0x0080}, {1, 5, 0x0080}, {1, 6, 0x0080} + {1, 0, 0x0040}, {1, 0, 0x0040}, {1, 1, 0x0130}, {1, 1, 0x0130}, {1, 2, 0x0130}, + {1, 2, 0x0130}, {1, 3, 0x0130}, {1, 3, 0x0130}, {1, 4, 0x0080}, {1, 4, 0x0080}, + {1, 6, 0x0130}, {1, 5, 0x0130}, {1, 5, 0x0130}, {1, 6, 0x0130} }" device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + {1, 8, 0}, /* Port 0: USB3 front internal header, top */ + {1, 8, 0}, /* Port 1: USB3 front internal header, bottom */ + {1, 2, 1}, /* Port 2: USB3 rear, top */ + {1, 2, 1}, /* Port 3: USB3 rear, bottom */ + {1, 2, 2}, /* Port 4: USB2 rear PS2, top */ + {1, 2, 2}, /* Port 5: USB2 rear PS2, bottom */ + {1, 2, 3}, /* Port 6: USB2 rear LAN, top */ + {1, 2, 3}, /* Port 7: USB2 rear LAN, bottom */ + {1, 9, 4}, /* Port 8: USB2 internal header USB910, top */ + {1, 9, 4}, /* Port 9: USB2 internal header USB910, bottom */ + {1, 2, 6}, /* Port 10: USB2 internal header USB1112, top */ + {1, 2, 5}, /* Port 11: USB2 internal header USB1112, bottom */ + {1, 2, 5}, /* Port 12: USB2 internal header USB1314, top */ + {1, 2, 6} /* Port 13: USB2 internal header USB1314, bottom */ + }" device ref pcie_rp1 on end # PCIe x4 slot device ref pcie_rp2 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/82756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ce13493c3ecac8154460c1fedf05e2d70a8e394 Gerrit-Change-Number: 82756 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/asus/p8z77-v: Apply updated USB current map to sb devicetree
by Keith Hui (Code Review) 02 Jun '24

02 Jun '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82755?usp=email ) Change subject: mb/asus/p8z77-v: Apply updated USB current map to sb devicetree ...................................................................... mb/asus/p8z77-v: Apply updated USB current map to sb devicetree This map is found stored in plain text in vendor firmware image. They will take effect when USB config is transitioned to southbridge devicetree. Change-Id: Iab0a225560856771407bb815ff4d8bc95d0f884f Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/82755/1 diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb index 043be06..adbb10a 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v/overridetree.cb @@ -5,6 +5,22 @@ subsystemid 0x1043 0x84ca inherit device ref peg11 on end # PCIEX_16_2 chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 2, 0 }, + { 1, 2, 0 }, + { 1, 2, 1 }, + { 1, 9, 1 }, + { 1, 9, 2 }, + { 1, 2, 2 }, + { 1, 2, 3 }, + { 1, 2, 3 }, + { 1, 2, 4 }, + { 1, 9, 4 }, + { 1, 2, 6 }, + { 1, 2, 5 }, + { 1, 2, 5 }, + { 1, 2, 6 } + }" register "gen1_dec" = "0x000c0291" device ref gbe on end -- To view, visit https://review.coreboot.org/c/coreboot/+/82755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab0a225560856771407bb815ff4d8bc95d0f884f Gerrit-Change-Number: 82755 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: sb/intel/bd82x6x/early_usb.c: Align native current map with MRC
by Keith Hui (Code Review) 02 Jun '24

02 Jun '24

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82754?usp=email ) Change subject: sb/intel/bd82x6x/early_usb.c: Align native current map with MRC ...................................................................... sb/intel/bd82x6x/early_usb.c: Align native current map with MRC Replace 3 unused values in the map with those found during a Ghidra examination of MRC binary, and on hardwares running vendor firmware (asus/p8z77-m and HP Z210 CMT Workstation). The outgoing values were introduced in commit 216ad2170ca8 ("sb/intel/bd82x6x: Add new USB currents") in anticipation for Gigabyte GA-Z77-DS3H mainboard, but effort to land it was eventually abandoned. Since commit xxxxxxxxxxxx, such values can be placed directly in the port config, so there should be no hurdle should that effort be resurrected. Add a few #defines in pch.h to place some inline documentation on MRC values, but more will be documented in the future when this mapping is introduced MRC-side. Finally, update autoport to match. Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/pch.h M util/autoport/bd82x6x.go 3 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/82754/1 diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 6667d47..6c21cf7 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -20,8 +20,9 @@ * See below. */ const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, - USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353, - 0x20000253, 0x20000053, 0x2000055f, 0x20000f5f}; + USBIR_TXRX_GAIN_DESKTOP6_LOW, USBIR_TXRX_GAIN_DESKTOP6_HIGH, + USBIR_TXRX_GAIN_DESKTOP7_LOW, USBIR_TXRX_GAIN_DESKTOP7_MED, + 0x20000053, 0x2000055f, 0x20000f5f}; int i; /* Unlock registers. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 040b477..f2f02b3 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -390,10 +390,23 @@ /* Up to 14" onboard trace length, up to 8" on wires */ #define USBIR_TXRX_GAIN_DEFAULT 0x20000f57 +#define USBIR_TXRX_GAIN_MOBILE_HIGH USBIR_TXRX_GAIN_DEFAULT /* Up to 10" onboard trace length, up to 15" on wires */ #define USBIR_TXRX_GAIN_HIGH 0x2000055B +/* Desktop 6-series PCHs */ +/* In order: up to and not including 8"/13"/15" on wires */ +#define USBIR_TXRX_GAIN_DESKTOP6_LOW USBIR_TXRX_GAIN_DESKTOP_LOW +#define USBIR_TXRX_GAIN_DESKTOP6_MED USBIR_TXRX_GAIN_DEFAULT +#define USBIR_TXRX_GAIN_DESKTOP6_HIGH 0x20000f5b + +/* Desktop 7-series PCHs */ +/* In order: up to and not including 8"/10"/15" on wires */ +#define USBIR_TXRX_GAIN_DESKTOP7_LOW USBIR_TXRX_GAIN_DEFAULT +#define USBIR_TXRX_GAIN_DESKTOP7_MED 0x20000553 +#define USBIR_TXRX_GAIN_DESKTOP7_HIGH USBIR_TXRX_GAIN_HIGH + /* Miscellaneous Control Register */ #define MISCCTL 0x3590 /* 32bit */ /* USB Port Disable Override */ diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 76411e7..e2dc827 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -311,8 +311,8 @@ 0x2000094a: 4, 0x2000035f: 5, 0x20000f53: 6, - 0x20000357: 7, - 0x20000353: 8, + 0x20000f5b: 7, + 0x20000553: 9, } for port := uint(0); port < 14; port++ { -- To view, visit https://review.coreboot.org/c/coreboot/+/82754?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I195c7f627994e48f7a6e6698589504dc96248cff Gerrit-Change-Number: 82754 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com>

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[XS] Change in coreboot[main]: sb/intel/bd82x6x: Make space for USB port config in devicetree
by Keith Hui (Code Review) 02 Jun '24

02 Jun '24

Attention is currently required from: Angel Pons, Patrick Rudolph. Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81878?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: sb/intel/bd82x6x: Make space for USB port config in devicetree ...................................................................... sb/intel/bd82x6x: Make space for USB port config in devicetree This is the first step to: - Move USB port configs, which are static, from C code to devicetree; - Unify USB port configs between MRC and native code path. For USB current strength/trace length settings, define one set of enums that accounts for all combinations currently seen in tree for boards using MRC raminit, and set up mapping in native code path for these enums. MRC code path counterparts will follow separately. This structure will otherwise match the one in C code used by native code path. Change-Id: I59af466d41790e2163342cac8676457ac19371ea Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/bd82x6x/chip.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81878/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I59af466d41790e2163342cac8676457ac19371ea Gerrit-Change-Number: 81878 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit June 2024