coreboot-gerrit May 2024

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[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Alper Nebi Yasak (Code Review) 31 May '24

31 May '24

Attention is currently required from: Jakub Czapiga, Julius Werner, Maximilian Brune, Nico Huber. Alper Nebi Yasak has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80322?usp=email ) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... Patch Set 6: (1 comment) File src/lib/device_tree.c: https://review.coreboot.org/c/coreboot/+/80322/comment/ffc03d12_6fcce70d?us… : PS4, Line 541: > addrcp/sizecp should be reset to 2/1 here. […] Done, used `fdt_find_node_by_path("/")`. -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 6 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Fri, 31 May 2024 13:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domains
by Lean Sheng Tan (Code Review) 31 May '24

31 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82034?usp=email ) Change subject: soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domains ...................................................................... soc/intel/xeon_sp: Add _OSC ASL generation utils for IIO domains For multi-SKU/SoC supports, IIO domain layouts are returned from FSP HOBs. Add _OSC ASL generation utils so that static IIO domain layout definition file per SKU/SoC are not needed any more. The _OSC generation codes is a thin AML generation layer which further invokes \_SB.POSC which is defined in ASL. The ASL handler is able to handle boot-time generated info as parameters while keeps good readability for the ease of maintenance. In this case, firmware granted capabilities are calculated in boot time and passed to ASL handler as parameters. TEST=Build and boot on intel/archercity CRB Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82034 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> --- M src/soc/intel/xeon_sp/acpi.c A src/soc/intel/xeon_sp/acpi/iiostack.asl M src/soc/intel/xeon_sp/include/soc/acpi.h 3 files changed, 171 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Christian Walter: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 1c493af..f66f5e9 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpigen.h> #include <assert.h> #include <intelblocks/acpi.h> #include <soc/chip_common.h> @@ -119,3 +120,22 @@ return NULL; } + +void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain, + const uint32_t granted_pcie_features, + const bool is_cxl_domain, + const uint32_t granted_cxl_features) +{ + acpigen_write_method("_OSC", 4); + + acpigen_write_return_namestr("\\_SB.POSC"); + acpigen_emit_byte(ARG0_OP); + acpigen_emit_byte(ARG1_OP); + acpigen_emit_byte(ARG2_OP); + acpigen_emit_byte(ARG3_OP); + acpigen_write_integer(granted_pcie_features); + acpigen_write_integer(is_cxl_domain); + acpigen_write_integer(granted_cxl_features); + + acpigen_pop_len(); +} diff --git a/src/soc/intel/xeon_sp/acpi/iiostack.asl b/src/soc/intel/xeon_sp/acpi/iiostack.asl new file mode 100644 index 0000000..c943dd5 --- /dev/null +++ b/src/soc/intel/xeon_sp/acpi/iiostack.asl @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" +#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" + +#define OSC_RET_FAILURE 0x02 +#define OSC_RET_UNRECOGNIZED_UUID 0x04 +#define OSC_RET_UNRECOGNIZED_REV 0x08 +#define OSC_RET_CAPABILITIES_MASKED 0x10 + +#define OSC_QUERY_SUPPORT_SET 0x01 + +#define ASL_UUID_UNHANDLED 0x00 +#define ASL_UUID_HANDLED 0x01 + +Scope (\_SB) +{ + /* + * \_SB.POSC - OSC handler for PCIe _OSC calls + * + * Reference: + * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Devic… + * + * Note: + * This call negotiate with OS on fixed firmware capabilities. It doesn't support to runtime + * change firmware settings. + * + * Arguments: (7) + * Arg0 - Map to _OSC Arg0. A Buffer containing a UUID + * Arg1 - Map to _OSC Arg1. An Integer containing a Revision ID of the buffer format + * Arg2 - Map to _OSC Arg2. An Integer containing a count of entries in Arg3 + * Arg3 - Map to _OSC Arg3. A Buffer containing a list of DWORD capabilities + * Arg4 - GrantedPCIeFeatures + * Arg5 - IsCxlDomain + * Arg6 - GrantedCxlFeatures + * + * _OSC ASL Return Value: + * A Buffer containing a list of capabilities + * + * Local Variables Assignment: + * Local0 - Not used + * Local1 - Not used + * Local2 - Not used + * Local3 - Not used + * Local4 - Not used + * Local5 - Not used + * Local6 - Record whether the UUID is handled + * Local7 - Backs up the input value of Arg3 + * + * Field Definitions: + * Name - Width Source Offset Description + * -------------------------------- + * RETE - DWord Arg3 0x00 Returned errors + * SUPP - Dword Arg3 0x04 PCIe Features that OS supported + * CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS + * OTRL - Dword Local7 0x08 PCIe Features that OS requests for control + * SUPC - Dword Arg3 0x0C CXL Features that OS supported + * CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS + * OTRC - Dword Local7 0x10 CXL Features that OS requests for control + */ + + Method (POSC, 7, NotSerialized) + { + +#define OscArg0 Arg0 +#define OscArg1 Arg1 +#define OscArg2 Arg2 +#define OscArg3 Arg3 +#define GrantedPCIeFeatures Arg4 +#define IsCxlDomain Arg5 +#define GrantedCxlFeatures Arg6 + + Local7 = OscArg3 + CreateDWordField (OscArg3, Zero, RETE) + RETE = 0x0 + Local6 = ASL_UUID_UNHANDLED + + If ((OscArg1 != 0x01)) + { + RETE = OSC_RET_UNRECOGNIZED_REV + Return (OscArg3) + } + + If ((OscArg2 < 0x03)) + { + RETE = OSC_RET_FAILURE + Return (OscArg3) + } + + If ((OscArg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) || + ((IsCxlDomain != 0x00) && + (OscArg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID)))) + { + CreateDWordField (OscArg3, 0x04, SUPP) + CreateDWordField (OscArg3, 0x08, CTRL) + CreateDWordField (Local7, 0x08, OTRL) + + CTRL &= GrantedPCIeFeatures + + /* TODO: further suppress CTRL bits per SUPP caps */ + + If ((CTRL != OTRL)) + { + RETE = OSC_RET_CAPABILITIES_MASKED + } + + Local6 = ASL_UUID_HANDLED + } + + If ((IsCxlDomain != 0x00) && + (OscArg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID))) + { + CreateDWordField (OscArg3, 0x0C, SUPC) + CreateDWordField (OscArg3, 0x10, CTRC) + CreateDWordField (Local7, 0x10, OTRC) + + CTRC &= GrantedCxlFeatures + + /* TODO: further suppress CTRC bits per SUPC caps */ + + If ((CTRC != OTRC)) + { + RETE = OSC_RET_CAPABILITIES_MASKED + } + + Local6 = ASL_UUID_HANDLED + } + + If ((Local6 == ASL_UUID_UNHANDLED)) + { + RETE = OSC_RET_UNRECOGNIZED_UUID + } + + Return (OscArg3) + } +} diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index e11b19e..7c7aee0 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -24,4 +24,19 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix); +#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 +#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 +#define PCIE_PME_CONTROL 0x04 +#define PCIE_AER_CONTROL 0x08 +#define PCIE_CAP_STRUCTURE_CONTROL 0x10 +#define PCIE_LTR_CONTROL 0x20 +#define PCIE_DPC_COTROL 0x80 + +#define CXL_ERROR_REPORTING_CONTROL 0x01 + +void acpigen_write_OSC_pci_domain_fixed_caps(const struct device *domain, + const uint32_t granted_pcie_features, + const bool is_cxl_domain, + const uint32_t granted_cxl_features); + #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibd3bfa2428725fe593754436d5ed75a3a11b4cdc Gerrit-Change-Number: 82034 Gerrit-PatchSet: 10 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Alper Nebi Yasak (Code Review) 31 May '24

31 May '24

Attention is currently required from: Alper Nebi Yasak, Jakub Czapiga, Maximilian Brune, Nico Huber. Hello Jakub Czapiga, Julius Werner, Maximilian Brune, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80322?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... device_tree: Add function to get top of memory from a FDT blob coreboot needs to figure out top of memory to place CBMEM data. On some non-x86 QEMU virtual machines, this is achieved by probing the RAM space to find where the VM starts discarding data since it's not backed by actual RAM. This behaviour seems to have changed on the QEMU side since then, VMs using the "virt" model have started raising exceptions/errors instead of silently discarding data (likely [1] for example) which has previously broken coreboot on these emulation boards. The qemu-aarch64 and qemu-riscv mainboards are intended for the "virt" models and had this issue, which were mostly fixed by using exception handlers in the RAM detection process [2][3]. But on 32-bit RISC-V we fail to initialize CBMEM if we have 2048 MiB or more of RAM, and on 64-bit RISC-V we had to limit probing to 16383 MiB because it can run into MMIO regions otherwise. The qemu-armv7 mainboard code is intended for the "vexpress-a9" model VM which doesn't appear to suffer from this issue. Still, the issue can be observed on the ARMv7 "virt" model via a port based on qemu-aarch64. QEMU docs for ARM and RISC-V "virt" models [4][5] recommend reading the device tree blob it provides for device information (incl. RAM size). Implement functions that parse the device tree blob to find described memory regions and calculate the top of memory in order to use it in mainboard code as an alternative to probing RAM space. ARM64 code initializes CBMEM in romstage where malloc isn't available, so take care to do parsing without unflattening the blob and make the code available in romstage as well. [1] https://lore.kernel.org/qemu-devel/1504626814-23124-1-git-send-email-peter.… [2] https://review.coreboot.org/c/coreboot/+/34774 [3] https://review.coreboot.org/c/coreboot/+/36486 [4] https://qemu-project.gitlab.io/qemu/system/arm/virt.html [5] https://qemu-project.gitlab.io/qemu/system/riscv/virt.html Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/include/device_tree.h M src/lib/Makefile.mk M src/lib/device_tree.c 3 files changed, 102 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/80322/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 6 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>

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[S] Change in coreboot[main]: mainboard/qemu-riscv: Get top of memory from device-tree blob
by Alper Nebi Yasak (Code Review) 31 May '24

31 May '24

Attention is currently required from: Maximilian Brune, Nico Huber, Philipp Hug, Ron Minnich. Hello Philipp Hug, Ron Minnich, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80363?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/qemu-riscv: Get top of memory from device-tree blob ...................................................................... mainboard/qemu-riscv: Get top of memory from device-tree blob Trying to probe RAM space to figure out top of memory causes an exception on RISC-V virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in RISC-V QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/mainboard/emulation/qemu-riscv/Kconfig M src/mainboard/emulation/qemu-riscv/cbmem.c 2 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/80363/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab Gerrit-Change-Number: 80363 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com>

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[XS] Change in coreboot[main]: mainboard/qemu-aarch64: Get top of memory from device-tree blob
by Alper Nebi Yasak (Code Review) 31 May '24

31 May '24

Attention is currently required from: Alper Nebi Yasak, Nico Huber. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80364?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mainboard/qemu-aarch64: Get top of memory from device-tree blob ...................................................................... mainboard/qemu-aarch64: Get top of memory from device-tree blob Trying to probe RAM space to figure out top of memory causes an exception on AArch64 virtual machines with recent versions of QEMU, but we temporarily enable exception handlers for that and use it to help detect if a RAM address is usable or not. However, QEMU docs recommend reading device information from the device-tree blob it provides us at the start of RAM. A previous commit adds a library function to parse device-tree blob that QEMU provides us. Use it to determine top of memory in AArch64 QEMU virtual machines, but still fall back to the RAM probing approach as a last-ditch effort. Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> --- M src/mainboard/emulation/qemu-aarch64/Kconfig M src/mainboard/emulation/qemu-aarch64/cbmem.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/80364/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Gerrit-Change-Number: 80364 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>

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[M] Change in coreboot[main]: intelvbtupgrader: New tool to upgrade VBT files to newer versions
by Vladimir Serbinenko (Code Review) 31 May '24

31 May '24

Vladimir Serbinenko has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: New tool to upgrade VBT files to newer versions ...................................................................... intelvbtupgrader: New tool to upgrade VBT files to newer versions Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 --- A util/intelvbtupgrader/.gitignore A util/intelvbtupgrader/Makefile A util/intelvbtupgrader/intelvbtupgrader.c 3 files changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/82722/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 2 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: payloads/iPXE: Add an option for reproducible building
by Filip Lewiński (Code Review) 31 May '24

31 May '24

Attention is currently required from: Felix Singer, Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Filip Lewiński has posted comments on this change by Filip Lewiński. ( https://review.coreboot.org/c/coreboot/+/82039?usp=email ) Change subject: payloads/iPXE: Add an option for reproducible building ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82039/comment/dd6ec671_9ab15fa4?us… : PS5, Line 6: > > `Subject line should not end with a period.` […] [Done](https://review.coreboot.org/c/coreboot/+/82039/8//COMMIT_MSG#7) -- To view, visit https://review.coreboot.org/c/coreboot/+/82039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Gerrit-Change-Number: 82039 Gerrit-PatchSet: 8 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Fri, 31 May 2024 12:42:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: payloads/iPXE: Add an option for reproducible building
by Filip Lewiński (Code Review) 31 May '24

31 May '24

Attention is currently required from: Filip Lewiński, Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82039?usp=email to look at the new patch set (#8). Change subject: payloads/iPXE: Add an option for reproducible building ...................................................................... payloads/iPXE: Add an option for reproducible building Allows to set a custom 32 bit hex build_id option for an iPXE build. Useful for reproducibility. Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 3 files changed, 21 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/82039/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/82039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Gerrit-Change-Number: 82039 Gerrit-PatchSet: 8 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[S] Change in coreboot[main]: payloads/iPXE: Add an option for reproducible building
by Filip Lewiński (Code Review) 31 May '24

31 May '24

Attention is currently required from: Filip Lewiński, Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82039?usp=email to look at the new patch set (#7). Change subject: payloads/iPXE: Add an option for reproducible building ...................................................................... payloads/iPXE: Add an option for reproducible building Allows to set a custom 32 bit hex build_id option for an iPXE build. Useful for reproducibility. Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M 3rdparty/arm-trusted-firmware M 3rdparty/libgfxinit M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 5 files changed, 23 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/82039/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/82039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Gerrit-Change-Number: 82039 Gerrit-PatchSet: 7 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com>

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[M] Change in coreboot[main]: payloads/iPXE: Add an option for reproducible building
by Filip Lewiński (Code Review) 31 May '24

31 May '24

Attention is currently required from: Filip Lewiński, Martin L Roth, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Krystian Hebel, Martin L Roth, Michał Kopeć, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82039?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: payloads/iPXE: Add an option for reproducible building ...................................................................... payloads/iPXE: Add an option for reproducible building Allows to set a custom 32 bit hex build_id option for an iPXE build. Useful for reproducibility. Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M 3rdparty/arm-trusted-firmware M 3rdparty/libgfxinit A build.sh M payloads/external/Makefile.mk M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 6 files changed, 93 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/82039/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/82039?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I926b096e77a9d45ba2beecd1fc2b7d0a9b9a7b9c Gerrit-Change-Number: 82039 Gerrit-PatchSet: 6 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com>

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