coreboot-gerrit May 2024

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up public microcode
by Michał Kopeć (Code Review) 31 May '24

31 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Michał Żygowski, Subrata Banik, Tarun. Michał Kopeć has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82686?usp=email ) Change subject: soc/intel/meteorlake: Hook up public microcode ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/Kconfig: https://review.coreboot.org/c/coreboot/+/82686/comment/c5850258_9fd8bffc?us… : PS1, Line 39: select MICROCODE_BLOB_UNDISCLOSED > > I assume you are using CPU_MICROCODE_CBFS_EXTERNAL_BINS then? So this change shouldn't have an eff […] Added `select MICROCODE_BLOB_UNDISCLOSED if MAINBOARD_HAS_CHROMEOS` as per your suggestion, Subrata -- To view, visit https://review.coreboot.org/c/coreboot/+/82686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f20956a1490da02acc24156360aef235111494 Gerrit-Change-Number: 82686 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 08:36:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up public microcode
by Michał Kopeć (Code Review) 31 May '24

31 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Michał Kopeć, Michał Żygowski, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Felix Singer, Jakub Czapiga, Kapil Porwal, Michał Żygowski, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82686?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Felix Singer, Verified+1 by build bot (Jenkins) Change subject: soc/intel/meteorlake: Hook up public microcode ...................................................................... soc/intel/meteorlake: Hook up public microcode Hook up public microcode for stepping C0 / QS. Keep MICROCODE_BLOB_UNDISCLOSED selected for: - ChromeOS devices, since they use a different version that was released to the public - Boards using pre-production MTL silicon, as ucodes for those steppings have not been released. Change-Id: I16f20956a1490da02acc24156360aef235111494 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.mk 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/82686/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f20956a1490da02acc24156360aef235111494 Gerrit-Change-Number: 82686 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XL] Change in coreboot[main]: ec/dasharo/ec: Add initial copy of ec/system76/ec
by Michał Kopeć (Code Review) 31 May '24

31 May '24

Attention is currently required from: Maciej Pijanowski, Michał Żygowski, Paul Menzel. Michał Kopeć has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82671?usp=email ) Change subject: ec/dasharo/ec: Add initial copy of ec/system76/ec ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82671/comment/f1c7c6b5_cf7457d2?us… : PS3, Line 7: ec/dasharo/ec: add support for Dasharo EC > Since this is just a copy and the actual Dasharo features / flavor is added later, please rephrase. […] Thanks Felix, updated the commit message as per your suggestion -- To view, visit https://review.coreboot.org/c/coreboot/+/82671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Gerrit-Change-Number: 82671 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 31 May 2024 08:33:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XL] Change in coreboot[main]: ec/dasharo/ec: Add initial copy of ec/system76/ec
by Michał Kopeć (Code Review) 31 May '24

31 May '24

Attention is currently required from: Maciej Pijanowski, Michał Kopeć, Michał Żygowski, Paul Menzel. Hello Felix Singer, Maciej Pijanowski, Michał Żygowski, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82671?usp=email to look at the new patch set (#4). Change subject: ec/dasharo/ec: Add initial copy of ec/system76/ec ...................................................................... ec/dasharo/ec: Add initial copy of ec/system76/ec Initial commit is a copy of ec/system76/ec from tag v24.02.1 (commit 0a280ff7) with string changes. Dasharo-specific features will be added in subsequent commits, similar to how Librem EC support was added in changes 52390 and 52391. Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/ec/dasharo/ec/Kconfig A src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi/ac.asl A src/ec/dasharo/ec/acpi/battery.asl A src/ec/dasharo/ec/acpi/battery_thresholds.asl A src/ec/dasharo/ec/acpi/buttons.asl A src/ec/dasharo/ec/acpi/ec.asl A src/ec/dasharo/ec/acpi/ec_ram.asl A src/ec/dasharo/ec/acpi/hid.asl A src/ec/dasharo/ec/acpi/lid.asl A src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/dasharo_ec.c A src/ec/dasharo/ec/dasharo_ec.h A src/ec/dasharo/ec/smbios.c 14 files changed, 1,045 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/82671/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Gerrit-Change-Number: 82671 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Subrata Banik (Code Review) 31 May '24

31 May '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Paul Menzel, Subrata Banik, Tarun. Hello Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82625?usp=email to look at the new patch set (#7). Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... mainboard/google/rex: Enable Rex64 build configuration - Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82625/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds
by Subrata Banik (Code Review) 31 May '24

31 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82699?usp=email ) Change subject: soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds ...................................................................... soc/intel/meteorlake: Exclude deprecated upd from FSP2.4 builds EnableMultiPhaseSiliconInit upd is deprecated and has been removed starting with v2.4 of FSP specification. Multi-phase silicon initialization is mandatory for all FSP implementations compliant to v2.4. The following modifications are made: - In fsp_params.c and silicon_init.c EnableMultiPhaseSiliconInit update is guarded so that it will get included only if FSP2.4 is not selected. BUG=b:329034258 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/meteorlake/fsp_params.c 2 files changed, 4 insertions(+), 1 deletion(-) Approvals: Subrata Banik: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 89b8a1b..cea894c 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -77,7 +77,7 @@ static void fsp_fill_common_arch_params(FSPS_UPD *supd) { -#if CONFIG(FSPS_HAS_ARCH_UPD) +#if (CONFIG(FSPS_HAS_ARCH_UPD) && !CONFIG(PLATFORM_USES_FSP2_4)) FSPS_ARCHx_UPD *s_arch_cfg = &supd->FspsArchUpd; s_arch_cfg->EnableMultiPhaseSiliconInit = fsp_is_multi_phase_init_enabled(); #endif diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 0ac3b48..36412b7 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -705,10 +705,13 @@ static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg) { + +#if !CONFIG(PLATFORM_USES_FSP2_4) /* * EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ s_arch_cfg->EnableMultiPhaseSiliconInit = 1; +#endif /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && -- To view, visit https://review.coreboot.org/c/coreboot/+/82699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdbf3bacc0a05975fc941b264fd400d74f506fce Gerrit-Change-Number: 82699 Gerrit-PatchSet: 5 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: [TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISA...
by Tyler Wang (Code Review) 31 May '24

31 May '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82720?usp=email ) Change subject: [TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN is set ...................................................................... [TEST_ONLY] soc/alderlake: fix eDP not display when VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN is set This patch add function `mainboard_check_lid_state()` to check GBB flag VB2_GBB_FLAG_DISABLE_LID_SHUTDOWN before transfer setting to LidStatus. If the flag is set, LidStatus will be "1" even lid closed, otherwise LidStatus will be set by real lid status. BUG=b:333982806 TEST=none Change-Id: Ieef5a4268baf17fb6b1bb4941d2d71befa7febb1 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/mainboard.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/ramstage.h 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/82720/1 diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c index 07aa4b5..ca81062 100644 --- a/src/mainboard/google/brya/mainboard.c +++ b/src/mainboard/google/brya/mainboard.c @@ -3,12 +3,14 @@ #include <acpi/acpigen.h> #include <baseboard/gpio.h> #include <baseboard/variants.h> +#include <bootmode.h> #include <device/device.h> #include <drivers/tpm/cr50.h> #include <drivers/wwan/fm/chip.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> +#include <security/vboot/vboot_common.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <stdio.h> @@ -132,6 +134,14 @@ acpigen_emit_namestring(acpi_device_path_join(parent, "PGPR._OFF")); } +UINT8 mainboard_check_lid_state(void) +{ + if (vboot_is_disable_lid_close_shutdown()) + return CONFIG(RUN_FSP_GOP); + else + return CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); +} + static void mainboard_generate_mpts(void) { const struct device *wwan = DEV_PTR(rp6_wwan); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index ff5c83c..562191f 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -634,6 +634,11 @@ s_cfg->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); } +__weak UINT8 mainboard_check_lid_state(void) +{ + return CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); +} + static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { @@ -642,7 +647,7 @@ /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); - s_cfg->LidStatus = CONFIG(VBOOT_LID_SWITCH) ? get_lid_switch() : CONFIG(RUN_FSP_GOP); + s_cfg->LidStatus = mainboard_check_lid_state(); s_cfg->PavpEnable = CONFIG(PAVP); } diff --git a/src/soc/intel/alderlake/include/soc/ramstage.h b/src/soc/intel/alderlake/include/soc/ramstage.h index e655198..9d30b0e 100644 --- a/src/soc/intel/alderlake/include/soc/ramstage.h +++ b/src/soc/intel/alderlake/include/soc/ramstage.h @@ -10,5 +10,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params); void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config); void soc_init_pre_device(void *chip_info); +UINT8 mainboard_check_lid_state(void); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82720?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieef5a4268baf17fb6b1bb4941d2d71befa7febb1 Gerrit-Change-Number: 82720 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/trulo/var/orisa: Enable HDA Codec ALC256
by Amanda Hwang (Code Review) 31 May '24

31 May '24

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82719?usp=email ) Change subject: mb/google/trulo/var/orisa: Enable HDA Codec ALC256 ...................................................................... mb/google/trulo/var/orisa: Enable HDA Codec ALC256 We use ALC256 as HDA codec on orisa. Add verb table and the related device tree changes for HDA related registers. BUG=b:338523452 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/orisa/Makefile.mk A src/mainboard/google/brya/variants/orisa/hda_verb.c M src/mainboard/google/brya/variants/orisa/overridetree.cb 4 files changed, 150 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/82719/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 9f6a026..5697052 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -374,6 +374,7 @@ config BOARD_GOOGLE_ORISA select BOARD_GOOGLE_BASEBOARD_TRULO + select SOC_INTEL_COMMON_BLOCK_HDA_VERB config BOARD_GOOGLE_OSIRIS select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/orisa/Makefile.mk b/src/mainboard/google/brya/variants/orisa/Makefile.mk index 91f031e..0bc6c14 100644 --- a/src/mainboard/google/brya/variants/orisa/Makefile.mk +++ b/src/mainboard/google/brya/variants/orisa/Makefile.mk @@ -1,5 +1,9 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += gpio.c + romstage-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/orisa/hda_verb.c b/src/mainboard/google/brya/variants/orisa/hda_verb.c new file mode 100644 index 0000000..bf998e1 --- /dev/null +++ b/src/mainboard/google/brya/variants/orisa/hda_verb.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, // Codec Vendor / Device ID: Realtek ALC256 + 0x10ec12ac, // Subsystem ID + 0x00000013, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting - 1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default (used for headset) + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 0d20a3a..42e31f4 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -91,6 +91,15 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_sdi_enable[1]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -520,5 +529,13 @@ end end end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82719?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92051886341bd317cce6061ece83439d156b0f90 Gerrit-Change-Number: 82719 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel: Fix pointer size mismatch errors in crashlog
by Dinesh Gehlot (Code Review) 31 May '24

31 May '24

Attention is currently required from: Appukuttan V K, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Wonkyu Kim. Dinesh Gehlot has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82481?usp=email ) Change subject: soc/intel: Fix pointer size mismatch errors in crashlog ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Gerrit-Change-Number: 82481 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 07:36:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Dinesh Gehlot (Code Review) 31 May '24

31 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar, Subrata Banik. Dinesh Gehlot has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 27 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 31 May 2024 07:35:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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