May 2024 - coreboot-gerrit - mail.coreboot.org

[XS] Change in coreboot[main]: mb/system76/rpl: Fix addw4 Kconfig name
by Tim Crawford (Code Review) May 31, 2024

May 31, 2024

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82725?usp=email ) Change subject: mb/system76/rpl: Fix addw4 Kconfig name ...................................................................... mb/system76/rpl: Fix addw4 Kconfig name Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant") Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/rpl/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82725/1 diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index 57c3de7..4184265 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -4,7 +4,7 @@ bool "addw3" config BOARD_SYSTEM76_ADDW4 - bool "addw3" + bool "addw4" config BOARD_SYSTEM76_BONW15 bool "bonw15" -- To view, visit https://review.coreboot.org/c/coreboot/+/82725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Gerrit-Change-Number: 82725 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Subrata Banik (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Eran Mitrani, Felix Singer, Jakub Czapiga, Martin L Roth, Paul Menzel, Tarun. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > Build is successful https://qa.coreboot.org/job/coreboot-gerrit/258212/console but stil no V+1 can someone help me to understand why V+1 does not appear even with successful build. -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 17:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: tests/drivers/efivars: Remove duplicated <limits.h>
by Elyes Haouas (Code Review) May 31, 2024

May 31, 2024

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82724?usp=email ) Change subject: tests/drivers/efivars: Remove duplicated <limits.h> ...................................................................... tests/drivers/efivars: Remove duplicated <limits.h> Already included <types.h> is supposed to provide <limits.h>. Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M tests/drivers/efivars.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/82724/1 diff --git a/tests/drivers/efivars.c b/tests/drivers/efivars.c index 6899ce5b..326e1fb 100644 --- a/tests/drivers/efivars.c +++ b/tests/drivers/efivars.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <drivers/efi/efivars.h> -#include <limits.h> #include <vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiFirmwareVolume.h> #include <vendorcode/intel/edk2/UDK2017/MdeModulePkg/Include/Guid/VariableFormat.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11 Gerrit-Change-Number: 82724 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: intel/block/pcie/rtd3: Also implement _PR3
by Tim Crawford (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Jeremy Soller, Tim Crawford. Hello Jeremy Soller, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/50598?usp=email to look at the new patch set (#5). Change subject: intel/block/pcie/rtd3: Also implement _PR3 ...................................................................... intel/block/pcie/rtd3: Also implement _PR3 Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> --- M src/soc/intel/common/block/pcie/rtd3/rtd3.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/50598/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/50598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15 Gerrit-Change-Number: 50598 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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[XS] Change in coreboot[main]: mb/google/brya/var/nova: Update USB ports setting
by Felix Held (Code Review) May 31, 2024

May 31, 2024

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82703?usp=email ) Change subject: mb/google/brya/var/nova: Update USB ports setting ...................................................................... mb/google/brya/var/nova: Update USB ports setting Update used USB port[2][3](type-a) setting for nova. BUG=b:328711879 TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Signed-off-by: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82703 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/nova/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/nova/overridetree.cb b/src/mainboard/google/brya/variants/nova/overridetree.cb index bd0bc86..950bb9b 100644 --- a/src/mainboard/google/brya/variants/nova/overridetree.cb +++ b/src/mainboard/google/brya/variants/nova/overridetree.cb @@ -6,6 +6,8 @@ register "sagv" = "SaGv_Enabled" register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2 Port 1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/82703?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63cf97b23627feac05743f2a6e514a33fcaf7dff Gerrit-Change-Number: 82703 Gerrit-PatchSet: 3 Gerrit-Owner: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: intelvbtupgrader: New tool to upgrade VBT files to newer versions
by Nicholas Chin (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Vladimir Serbinenko. Nicholas Chin has posted comments on this change by Vladimir Serbinenko. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: New tool to upgrade VBT files to newer versions ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Could you also add a `description.md` file to `util/intelvbtupgrader` with a short (~1 line) description of this utility? Refer to the other tools in util. After that, could you then run `./util/util_readme/util_readme.sh` from coreboot's root to regenerate `util/README.md` and `Documentation/util.md`? -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 4 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 15:43:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers
by Nico Huber (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Fabian Meyer, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Srinidhi N Kaushik, Tim Chu. Nico Huber has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > FSP-S is loaded by the bootloader, thus FSP-S must never access the SPI flash, modify it, protect it or whatsoever. There's no TOCTOU Vulnerability, thus nothing to protect. It's a bit more complicated. The concern is about pointers left by FSP-M or the code around it (e.g. in HOBs). Though, enabling paging in FSP-S is rather late anyway. I guess they use it as a development tool, e.g. like an assertion that tells you where you have troublesome code. Not sure why they would ever put that into a production binary, though. And of course it's not reasonable to break FSP ssumptions for it. It explains why the code exists, it just doesn't fit into the FSP world, I guess. -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 31 May 2024 14:55:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: arch/io.h: Add port I/O functions to other architectures
by Nico Huber (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Alper Nebi Yasak, Arthur Heymans, Jianjun Wang, Julius Werner, Ron Minnich, Shelley Chen, Yu-Ping Wu. Nico Huber has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add port I/O functions to other architectures ...................................................................... Patch Set 5: (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/80372/comment/fa3e2e7d_0b91f337?us… : PS5, Line 532: CPU communicate with peripheral devices over PCI I/O space. > Okay, sorry, I guess I meant `struct resource`. I was thinking of stuff like what `src/drivers/emulation/qemu/bochs.c` seems to do, where it gets a `struct resource` from the platform to represent its base address and whenever it wants to write to some register it uses a little helper that checks whether `res->flags & IORESOURCE_IO`, and uses that to decide whether to use I/O or MMIO accessors. Oh, I should have looked closer. That's not a good role model. This is uncommon. When you have a PCI device, usually it's either IO or MMIO. And you know that beforehand, because it's always the same for this device model. This bochs driver seems to abstract because it supports different device models and different (emulated) hardware revisions. ``` /* MMIO bar supported since qemu 3.0+ */ ``` So coreboot is either confronted with this 3.0+ hardware or not. If the driver was written for a single device model/revision, we wouldn't see such abstraction. With that said, I'm not sure if we have a strong use case here for PIO. Unless somebody uses a sadly old QEMU, they could emulate something where the driver would use MMIO, and stubbing out PIO would work. For QEMU's firmware-config interface, we could just pretend it's MMIO (assuming the translation offset is always the same and we can do the calculation by hand). > > I was kinda assuming that that's how that whole coreboot device framework (which I don't really have any experience with because the non-PCI Arm drivers I usually worked on don't use it) works... that you have your `devicetree.cb` thing which says the platform has an instance of device X which is mapped at MMIO address Y (or I/O address Y), and then that somehow gets translated into a `struct resource` and passed to the X driver which can then use the address and flags in that struct to figure out how to talk to it. And if you're on an x86 device you can write your `devicetree.cb` such that it represents an I/O address, and if you're on an Arm device you write it such that it represents an MMIO address (and I guess you need to do the math to see where in your SoC's PCI MMIO window that thing falls by hand then when writing `devicetree.cb`, or maybe build some magic into sconfig that allows you to define the different PCI roots and have it do that math for you). > > Is that not how it works? No. It could be done that way, but isn't. Two major points: 1. PCI was designed for systems where everything was pluggable. Consequently, our static devicetree might not even mention the devices. This requires dynamic resource allocation. And because we have that implemented anyway, we also use it for devices soldered on-board. At least some address calculations would have to be done at runtime. 2. At least for PCI, `struct resource` describes the physical address that the device decodes. Because of all the identity mapping on x86, that's conveniently the same address that the CPU sees. So we don't have any mechanism for address translation. Having to translate PIO-MMIO isn't new. However, this used to be a singleton (where this `arch/io.h` implementation with a single Kconfig offset would work). If we encounter or want to prepare for hardware where we can't use a single offset, we need to design something new. For instance, our IORESOURCE_BRIDGE is just a flag, w/o any concept of offsets or different address spaces on both sides of the bridge. If we'd add the missing information there, implementing a generic `read_res(struct resource *, offset)` / `write_res(...)` would be straight forward. I still doubt, though, if we'll ever need it. -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 14:28:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers
by Angel Pons (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Fabian Meyer, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Srinidhi N Kaushik, Tim Chu. Angel Pons has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > It's not a feature, it's an invalid configuration for FSP in API mode. […] Well, can one simply disable it for now in coreboot? Or is this not exposed as a FSP UPD? -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 31 May 2024 14:26:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Fabian Meyer <fabian(a)meyfa.net>

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[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers
by Patrick Rudolph (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Fabian Meyer, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Shuo Liu, Srinidhi N Kaushik, Tim Chu. Patrick Rudolph has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers ...................................................................... Patch Set 4: (1 comment) Patchset: PS3: > PcdMigrateTemporaryRamFirmwareVolumes is a feature for UEFI boot guard and not ready to be used with […] It's not a feature, it's an invalid configuration for FSP in API mode. FSP-S is loaded by the bootloader, thus FSP-S must never access the SPI flash, modify it, protect it or whatsoever. There's no TOCTOU Vulnerability, thus nothing to protect. -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 31 May 2024 14:25:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Fabian Meyer <fabian(a)meyfa.net>

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