May 2024 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: soc/intel/mtl: Hook up GMA ACPI brightness controls
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82729?usp=email ) Change subject: soc/intel/mtl: Hook up GMA ACPI brightness controls ...................................................................... soc/intel/mtl: Hook up GMA ACPI brightness controls Add function needed to generate ACPI backlight control SSDT, along with Kconfig values for accessing the registers. Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Signed-off-by: Jeremy Soller <jeremy(a)sysetm76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/Makefile.mk M src/soc/intel/meteorlake/chip.h A src/soc/intel/meteorlake/graphics.c 4 files changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/82729/1 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 622d35f..31aee89 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -402,6 +402,18 @@ help Set this option if debug build of FSP is used. +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + config DROP_CPU_FEATURE_PROGRAM_IN_FSP bool default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index 893523c..113bba4 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -37,6 +37,7 @@ ramstage-y += espi.c ramstage-y += finalize.c ramstage-y += fsp_params.c +ramstage-y += graphics.c ramstage-y += lockdown.c ramstage-y += p2sb.c ramstage-y += pcie_rp.c diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 0c76b7c..0cee962 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <device/pci_ids.h> #include <gpio.h> #include <intelblocks/cfg.h> @@ -527,6 +528,9 @@ * as per `enum slew_rate` data type. */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + + /* i915 struct for GMA backlight control */ + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/graphics.c b/src/soc/intel/meteorlake/graphics.c new file mode 100644 index 0000000..0ce4442 --- /dev/null +++ b/src/soc/intel/meteorlake/graphics.c @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <intelblocks/graphics.h> +#include <soc/ramstage.h> + +const struct i915_gpu_controller_info * +intel_igd_get_controller_info(const struct device *const dev) +{ + const struct soc_intel_meteorlake_config *const chip = dev->chip_info; + return &chip->gfx; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied08e5e9fe4913bd60474ed7dcf88b945172558d Gerrit-Change-Number: 82729 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[S] Change in coreboot[main]: soc/intel/common/block/cse: Prevent HECI commands when flash descript...
by Tim Crawford (Code Review) June 1, 2024

June 1, 2024

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82728?usp=email ) Change subject: soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set ...................................................................... soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set Sending the disable and EOP commands will not work if flash descriptor override is set on Meteor Lake. Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee Signed-off-by: Jeremy Soller <Jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/include/intelblocks/fast_spi.h 4 files changed, 27 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/82728/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d78b8a0..20efd91 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -11,6 +11,7 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/me.h> #include <intelblocks/pmclib.h> #include <intelblocks/post_codes.h> @@ -1310,10 +1311,17 @@ size_t enable_reply_size; - /* Function Start */ - int send; int result; + + /* Function Start */ + + if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "HECI: not setting ME state because " + "flash descriptor override is enabled\n"); + return; + } + /* * Check if the CMOS value "me_state" exists, if it doesn't, then * don't do anything. diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 265fe04..f2701d5 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -4,6 +4,7 @@ #include <bootstate.h> #include <console/console.h> #include <intelblocks/cse.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pmc_ipc.h> #include <security/vboot/vboot_common.h> #include <soc/intel/common/reset.h> @@ -243,6 +244,11 @@ return; } + if (fast_spi_flash_descriptor_override()) { + printk(BIOS_WARNING, "CSE: not sending EOP because flash descriptor override is enabled\n"); + return; + } + if (!eop_sent) { set_cse_device_state(PCH_DEVFN_CSE, DEV_ACTIVE); timestamp_add_now(TS_ME_END_OF_POST_START); diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5382644..91eb1aa 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -483,6 +483,15 @@ write32(spibar + SPIBAR_HSFSTS_CTL, SPIBAR_HSFSTS_W1C_BITS); } +/* Check if flash descriptor override is asserted */ +bool fast_spi_flash_descriptor_override(void) +{ + void *spibar = fast_spi_get_bar(); + uint32_t hsfsts = read32(spibar + SPIBAR_HSFSTS_CTL); + printk(BIOS_DEBUG, "HSFSTS: 0x%X\n", hsfsts); + return !(hsfsts & SPIBAR_HSFSTS_FDOPSS); +} + /* As there is no official ACPI ID for this controller use the generic PNP ID for now. */ static const char *fast_spi_acpi_hid(const struct device *dev) diff --git a/src/soc/intel/common/block/include/intelblocks/fast_spi.h b/src/soc/intel/common/block/include/intelblocks/fast_spi.h index 46b4f48..62195a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/fast_spi.h +++ b/src/soc/intel/common/block/include/intelblocks/fast_spi.h @@ -111,5 +111,7 @@ * Set FAST_SPIBAR Vendor Component Lock bit. */ void fast_spi_set_vcl(void); +/* Check if flash descriptor override is asserted */ +bool fast_spi_flash_descriptor_override(void); #endif /* SOC_INTEL_COMMON_BLOCK_FAST_SPI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82728?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b5a56229434c9cc326141d48359faa7759541ee Gerrit-Change-Number: 82728 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[M] Change in coreboot[main]: intelvbtupgrader: New tool to upgrade VBT files to newer versions
by Vladimir Serbinenko (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Vladimir Serbinenko. Vladimir Serbinenko has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: New tool to upgrade VBT files to newer versions ...................................................................... intelvbtupgrader: New tool to upgrade VBT files to newer versions Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M Documentation/util.md M util/README.md A util/intelvbtupgrader/.gitignore A util/intelvbtupgrader/Makefile A util/intelvbtupgrader/description.md A util/intelvbtupgrader/intelvbtupgrader.c 6 files changed, 222 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/82722/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com>

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[M] Change in coreboot[main]: device_tree: Add function to get top of memory from a FDT blob
by Julius Werner (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Alper Nebi Yasak, Jakub Czapiga, Maximilian Brune, Nico Huber. Julius Werner has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80322?usp=email ) Change subject: device_tree: Add function to get top of memory from a FDT blob ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8bef09bc1bc4e324ebeaa37f78d67d3aa315f52c Gerrit-Change-Number: 80322 Gerrit-PatchSet: 7 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 22:51:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mainboard/qemu-aarch64: Get top of memory from device-tree blob
by Julius Werner (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Alper Nebi Yasak, Nico Huber. Julius Werner has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80364?usp=email ) Change subject: mainboard/qemu-aarch64: Get top of memory from device-tree blob ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/mainboard/emulation/qemu-aarch64/cbmem.c: https://review.coreboot.org/c/coreboot/+/80364/comment/6326c0dc_107a40ef?us… : PS5, Line 12: top = fdt_get_memory_top((void *)_dram); Does this mean that the FDT QEMU injects is always placed at the start of DRAM? If so, I'd recommend defining an explicit region for that in this board's `memlayout.ld` (and then referencing that region by name here, instead of `_dram`), so that future changes to this board won't accidentally place something else there and overwrite the FDT. -- To view, visit https://review.coreboot.org/c/coreboot/+/80364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc888b57cf98e0797ce7f9ddfa2eb34d14cd9c1 Gerrit-Change-Number: 80364 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 22:31:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/system76/rpl: Fix addw4 Kconfig name
by Felix Singer (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Tim Crawford. Felix Singer has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82725?usp=email ) Change subject: mb/system76/rpl: Fix addw4 Kconfig name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Gerrit-Change-Number: 82725 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Fri, 31 May 2024 22:24:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: arch/io.h: Add port I/O functions to other architectures
by Julius Werner (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Alper Nebi Yasak, Arthur Heymans, Jianjun Wang, Nico Huber, Ron Minnich, Shelley Chen, Yu-Ping Wu. Julius Werner has posted comments on this change by Alper Nebi Yasak. ( https://review.coreboot.org/c/coreboot/+/80372?usp=email ) Change subject: arch/io.h: Add port I/O functions to other architectures ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/device/Kconfig: https://review.coreboot.org/c/coreboot/+/80372/comment/120ae443_57cc71a9?us… : PS5, Line 532: CPU communicate with peripheral devices over PCI I/O space. > > Okay, sorry, I guess I meant `struct resource`. […] Okay, sounds like I just had the wrong impression of how these things work in practice. Let's go with this single Kconfig solution then and hope that it will be all we'll ever need. -- To view, visit https://review.coreboot.org/c/coreboot/+/80372?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9 Gerrit-Change-Number: 80372 Gerrit-PatchSet: 5 Gerrit-Owner: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 22:23:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Alper Nebi Yasak <alpernebiyasak(a)gmail.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Lean Sheng Tan (Code Review) June 1, 2024

June 1, 2024

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... mainboard/google/rex: Enable Rex64 build configuration - Add Rex64 board to Kconfig menu - Enable building for Rex64 with x86_64 support Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82625 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index 5e019ee..9ee0bc0 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -122,6 +122,11 @@ config BOARD_GOOGLE_REX0 select BOARD_GOOGLE_MODEL_REX +config BOARD_GOOGLE_REX64 + select BOARD_GOOGLE_MODEL_REX + select HAVE_X86_64_SUPPORT + select USE_X86_64_SUPPORT + config BOARD_GOOGLE_REX_EC_ISH select BOARD_GOOGLE_MODEL_REX_EC_ISH @@ -182,6 +187,7 @@ config MAINBOARD_PART_NUMBER default "Rex" if BOARD_GOOGLE_REX0 + default "Rex64" if BOARD_GOOGLE_REX64 default "Rex_Ec_Ish" if BOARD_GOOGLE_REX_EC_ISH default "Rex4ES" if BOARD_GOOGLE_REX4ES default "Rex4ES_Ec_Ish" if BOARD_GOOGLE_REX4ES_EC_ISH diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index 6aca8fa..f4fed2a 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -32,6 +32,9 @@ config BOARD_GOOGLE_REX4ES_EC_ISH bool "-> Rex4ES EC ISH" +config BOARD_GOOGLE_REX64 + bool "-> Rex 64" + config BOARD_GOOGLE_SCREEBO bool "-> Screebo" -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 10 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Lean Sheng Tan (Code Review) June 1, 2024

June 1, 2024

Attention is currently required from: Eran Mitrani, Felix Held, Felix Singer, Jakub Czapiga, Martin L Roth, Paul Menzel, Subrata Banik, Tarun. Lean Sheng Tan has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 9: (1 comment) Patchset: PS7: > > Build is successful https://qa.coreboot.org/job/coreboot-gerrit/258212/console but stil no V+1 […] Jenkins was acting up, and that's where those V+1 are coming from. Felix S. restarted Jenkins. -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 31 May 2024 22:11:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: drivers/intel/dtbt: Add discrete Thunderbolt driver
by Tim Crawford (Code Review) May 31, 2024

May 31, 2024

Attention is currently required from: Kyösti Mälkki, Martin L Roth, Michał Żygowski, Paul Menzel, Tim Wawrzynczak, Utkarsh H Patel. Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75286?usp=email ) Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver ...................................................................... Patch Set 10: (1 comment) File src/drivers/intel/dtbt/dtbt.c: https://review.coreboot.org/c/coreboot/+/75286/comment/bdbfac3a_bd60ed3b?us… : PS5, Line 187: printk(BIOS_DEBUG, "DTBT get security level\n"); > maybe add a comment here about why you need to get the security level before and after writing the s […] This appears to have been just not implementing the required steps when changing the level. I think the intent is: - `GET_SECURITY_LEVEL` to check if it needs to change in the first place - `SET_SECURITY_LEVEL` to apply the desired security level (SL0 in this case) - `GET_SECURITY_LEVEL` to verify controllers made the change, and rollback any changes if it failed Without any of the checking, only the `SET_SECURITY_LEVEL` makes sense to keep here. -- To view, visit https://review.coreboot.org/c/coreboot/+/75286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Gerrit-Change-Number: 75286 Gerrit-PatchSet: 10 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 20:49:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com>

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