coreboot-gerrit May 2024

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[S] Change in coreboot[main]: soc/intel: Fix pointer size mismatch errors in crashlog
by Lean Sheng Tan (Code Review) 31 May '24

31 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82481?usp=email ) ( 8 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel: Fix pointer size mismatch errors in crashlog ...................................................................... soc/intel: Fix pointer size mismatch errors in crashlog The crashlog code in intel/common/block and meteorlake soc was casting integer addresses directly to pointer types, which caused compilation errors in x86_64 bit builds. This commit fixes the issue by using uintptr_t for casting integer addresses to pointer types before dereferencing. BUG=b:329034258 TEST=Successfully build Meteor Lake (rex) in both x86_32 and x86_64 modes. Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82481 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/common/block/crashlog/crashlog.c M src/soc/intel/meteorlake/crashlog.c 2 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Kapil Porwal: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve Dinesh Gehlot: Looks good to me, approved diff --git a/src/soc/intel/common/block/crashlog/crashlog.c b/src/soc/intel/common/block/crashlog/crashlog.c index a9ac8a53..d92d7bc 100644 --- a/src/soc/intel/common/block/crashlog/crashlog.c +++ b/src/soc/intel/common/block/crashlog/crashlog.c @@ -112,7 +112,7 @@ u16 stall_cnt = 0; do { - cl_mailbox_interface.data = read32((u32 *)cl_mailbox_addr); + cl_mailbox_interface.data = read32((u32 *)(uintptr_t)cl_mailbox_addr); udelay(CPU_CRASHLOG_WAIT_STALL); stall_cnt++; } while ((cl_mailbox_interface.fields.busy == 1) @@ -140,7 +140,7 @@ cl_mailbox_intf.fields.param = param; cl_mailbox_intf.fields.busy = 1; - write32((u32 *)(cl_base_addr + cl_get_cpu_mb_int_addr()), + write32((u32 *)(uintptr_t)(cl_base_addr + cl_get_cpu_mb_int_addr()), cl_mailbox_intf.data); cpu_cl_poll_mailbox_ready(cl_base_addr + cl_get_cpu_mb_int_addr()); @@ -167,7 +167,7 @@ pmc_crashlog_desc_table_t *descriptor_table) { int total_data_size = 0; - descriptor_table->numb_regions = read32((u32 *)desc_table_addr); + descriptor_table->numb_regions = read32((u32 *)(uintptr_t)desc_table_addr); printk(BIOS_DEBUG, "CL PMC desc table: numb of regions is 0x%x at addr 0x%x\n", descriptor_table->numb_regions, desc_table_addr); for (int i = 0; i < descriptor_table->numb_regions; i++) { @@ -178,7 +178,7 @@ break; } desc_table_addr += 4; - descriptor_table->regions[i].data = read32((u32 *)(desc_table_addr)); + descriptor_table->regions[i].data = read32((u32 *)(uintptr_t)(desc_table_addr)); total_data_size += descriptor_table->regions[i].bits.size * sizeof(u32); printk(BIOS_DEBUG, "CL PMC desc table: region 0x%x has size 0x%x at offset 0x%x\n", i, descriptor_table->regions[i].bits.size, @@ -295,7 +295,7 @@ u32 src_addr = src_bar + offset; - u32 data = read32((u32 *)src_addr); + u32 data = read32((u32 *)(uintptr_t)src_addr); /* First 32bits of the record must not be 0xdeadbeef */ if (data == INVALID_CRASHLOG_RECORD) { @@ -320,7 +320,7 @@ u32 copied = 0; while (copied < size) { /* DW by DW copy: byte access to PMC SRAM not allowed */ - *dest_addr = read32((u32 *)src_addr); + *dest_addr = read32((u32 *)(uintptr_t)src_addr); dest_addr++; src_addr += 4; copied++; diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 6d654d7..0321e00 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -34,7 +34,7 @@ static u64 get_disc_tab_header(void) { - return read64((void *)disc_tab_addr); + return read64((void *)(uintptr_t)disc_tab_addr); } /* Get the SRAM BAR. */ @@ -338,7 +338,7 @@ disc_tab_addr = bar_addr + get_disc_table_offset(); - u32 dw0 = read32((u32 *)disc_tab_addr); + u32 dw0 = read32((u32 *)(uintptr_t)disc_tab_addr); if (!is_crashlog_data_valid(dw0)) return false; @@ -351,7 +351,7 @@ for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { cur_offset = 8 + 24 * i; - dw0 = read32((u32 *)disc_tab_addr + cur_offset); + dw0 = read32((u32 *)(uintptr_t)disc_tab_addr + cur_offset); if (!is_crashlog_data_valid(dw0)) continue; @@ -361,7 +361,7 @@ break; } - cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset)); + cpu_cl_disc_tab.buffers[i].data = read64((void *)(uintptr_t)(disc_tab_addr + cur_offset)); printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, cpu_cl_disc_tab.buffers[i].fields.offset); @@ -450,7 +450,7 @@ cl_punit_control_interface_t punit_ctrl_intfc; memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t)); punit_ctrl_intfc.fields.set_re_arm = 1; - write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); + write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); if (!wait_and_check(CRASHLOG_RE_ARM_STATUS_MASK)) printk(BIOS_ERR, "CPU crashlog re_arm not asserted\n"); @@ -480,7 +480,7 @@ cl_punit_control_interface_t punit_ctrl_intfc; memset(&punit_ctrl_intfc, 0, sizeof(cl_punit_control_interface_t)); punit_ctrl_intfc.fields.set_storage_off = 1; - write32((u32 *)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); + write32((u32 *)(uintptr_t)(ctrl_sts_intfc_addr), punit_ctrl_intfc.data); if (!wait_and_check(CRASHLOG_PUNIT_STORAGE_OFF_MASK)) printk(BIOS_ERR, "CPU crashlog storage_off not asserted\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/82481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Gerrit-Change-Number: 82481 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/system76/rpl: Hook up TAS5825M init
by Jeremy Soller (Code Review) 31 May '24

31 May '24

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82726?usp=email ) Change subject: mb/system76/rpl: Hook up TAS5825M init ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Gerrit-Change-Number: 82726 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Fri, 31 May 2024 18:21:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/system76/rpl: Fix addw4 Kconfig name
by Jeremy Soller (Code Review) 31 May '24

31 May '24

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82725?usp=email ) Change subject: mb/system76/rpl: Fix addw4 Kconfig name ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Gerrit-Change-Number: 82725 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Fri, 31 May 2024 18:21:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/system76: Add SPDX ID to devicetree files
by Jeremy Soller (Code Review) 31 May '24

31 May '24

Attention is currently required from: Tim Crawford. Jeremy Soller has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/82700?usp=email ) Change subject: mb/system76: Add SPDX ID to devicetree files ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82700?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I55f2730f7277a3c699b86ded5864e9690d92d518 Gerrit-Change-Number: 82700 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Comment-Date: Fri, 31 May 2024 18:21:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: security/tpm/tspi: Do TPM Restart if TPM Resume fails
by Tim Crawford (Code Review) 31 May '24

31 May '24

Attention is currently required from: Christian Walter, Paul Menzel, Tim Crawford. Hello Christian Walter, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75878?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: security/tpm/tspi: Do TPM Restart if TPM Resume fails ...................................................................... security/tpm/tspi: Do TPM Restart if TPM Resume fails The Infineon SLB 9672 on newer Clevo machines regularly fails TPM Resume on S3 with the error `TPM_RC_VALUE`. Per TPM2 spec, handle the failure by performing a TPM Restart. > The startup behavior defined by this specification is different than > TPM 1.2 with respect to Startup(STATE). A TPM 1.2 device will enter > Failure Mode if no state is available when the TPM receives > Startup(STATE). This is not the case in this specification. It is up > to the CRTM to take corrective action if it the TPM returns > TPM_RC_VALUE in response to Startup(STATE). Fixes the following error from being repeatedly logged in Linux: > kernel: tpm tpm0: A TPM error (256) occurred attempting get random Ref: Trusted Platform Module Library, Part 1: Architecture, rev 1.59 Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/security/tpm/tspi/tspi.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75878/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3388007d4448c93bd0dda591c8ca7d1a8dc5306b Gerrit-Change-Number: 75878 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com>

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[XS] Change in coreboot[main]: mb/system76/rpl: Hook up TAS5825M init
by Tim Crawford (Code Review) 31 May '24

31 May '24

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82726?usp=email ) Change subject: mb/system76/rpl: Hook up TAS5825M init ...................................................................... mb/system76/rpl: Hook up TAS5825M init Ensure per-board smart amp init is configured. Fixes speaker output on oryp12. Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Fixes: 8b9716e2269d ("mb/system76/rpl: Add Oryx Pro 12 as a variant") Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/rpl/Makefile.mk 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/82726/1 diff --git a/src/mainboard/system76/rpl/Makefile.mk b/src/mainboard/system76/rpl/Makefile.mk index cf92eb2..2c8dfba 100644 --- a/src/mainboard/system76/rpl/Makefile.mk +++ b/src/mainboard/system76/rpl/Makefile.mk @@ -10,5 +10,6 @@ ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD -- To view, visit https://review.coreboot.org/c/coreboot/+/82726?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40ff1889dd144bf83ef85979a55535493aa7abdd Gerrit-Change-Number: 82726 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree
by Tim Crawford (Code Review) 31 May '24

31 May '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Michał Kopeć, Michał Żygowski, Subrata Banik, Tarun. Tim Crawford has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82685?usp=email ) Change subject: soc/intel/meteorlake: Hook up PchHdaAudioLinkHdaEnable to devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecbe106ae18b5a8b53c04a5335a4e4c4ae27c7a0 Gerrit-Change-Number: 82685 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 17:46:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/system76/rpl: Fix addw4 Kconfig name
by Tim Crawford (Code Review) 31 May '24

31 May '24

Tim Crawford has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82725?usp=email ) Change subject: mb/system76/rpl: Fix addw4 Kconfig name ...................................................................... mb/system76/rpl: Fix addw4 Kconfig name Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Fixes: 29f1b791270b ("mb/system76/rpl: Add Adder WS 4 as a variant") Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/rpl/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/82725/1 diff --git a/src/mainboard/system76/rpl/Kconfig.name b/src/mainboard/system76/rpl/Kconfig.name index 57c3de7..4184265 100644 --- a/src/mainboard/system76/rpl/Kconfig.name +++ b/src/mainboard/system76/rpl/Kconfig.name @@ -4,7 +4,7 @@ bool "addw3" config BOARD_SYSTEM76_ADDW4 - bool "addw3" + bool "addw4" config BOARD_SYSTEM76_BONW15 bool "bonw15" -- To view, visit https://review.coreboot.org/c/coreboot/+/82725?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ed280c1e62e0f094fd40d2165892240f76de390 Gerrit-Change-Number: 82725 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Subrata Banik (Code Review) 31 May '24

31 May '24

Attention is currently required from: Eran Mitrani, Felix Singer, Jakub Czapiga, Martin L Roth, Paul Menzel, Tarun. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 8: (1 comment) Patchset: PS7: > Build is successful https://qa.coreboot.org/job/coreboot-gerrit/258212/console but stil no V+1 can someone help me to understand why V+1 does not appear even with successful build. -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 17:00:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: tests/drivers/efivars: Remove duplicated <limits.h>
by Elyes Haouas (Code Review) 31 May '24

31 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82724?usp=email ) Change subject: tests/drivers/efivars: Remove duplicated <limits.h> ...................................................................... tests/drivers/efivars: Remove duplicated <limits.h> Already included <types.h> is supposed to provide <limits.h>. Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M tests/drivers/efivars.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/82724/1 diff --git a/tests/drivers/efivars.c b/tests/drivers/efivars.c index 6899ce5b..326e1fb 100644 --- a/tests/drivers/efivars.c +++ b/tests/drivers/efivars.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <drivers/efi/efivars.h> -#include <limits.h> #include <vendorcode/intel/edk2/UDK2017/MdePkg/Include/Pi/PiFirmwareVolume.h> #include <vendorcode/intel/edk2/UDK2017/MdeModulePkg/Include/Guid/VariableFormat.h> #include <string.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82724?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I945eeeeccb16851f64d85cf5c67ea6e256082e11 Gerrit-Change-Number: 82724 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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coreboot-gerrit May 2024