coreboot-gerrit May 2024

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[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Felix Singer (Code Review) 31 May '24

31 May '24

Attention is currently required from: Alexander Couzens, Angel Pons, Maciej Pijanowski, Paul Menzel. Felix Singer has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ...................................................................... Patch Set 7: (2 comments) Patchset: PS7: Rebase on main File src/mainboard/lenovo/m920q/Makefile.inc: PS7: Rename to Makefile.mk -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Fri, 31 May 2024 11:17:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel: Fix pointer size mismatch errors in crashlog
by Kapil Porwal (Code Review) 31 May '24

31 May '24

Attention is currently required from: Appukuttan V K, Eran Mitrani, Jakub Czapiga, Subrata Banik, Tarun, Wonkyu Kim. Kapil Porwal has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82481?usp=email ) Change subject: soc/intel: Fix pointer size mismatch errors in crashlog ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Gerrit-Change-Number: 82481 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 10:50:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Subrata Banik (Code Review) 31 May '24

31 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard This commit removes config guard around FSPM_ARCH_UPD from the FspApi.h header file. This change is done to ensure that this header file can be used with both x86_32 and x86_64 architectures and also with different FSP specification versions. The following modifications are made: - Removes PLATFORM_USES_FSP2_X86_32 config guard around FSPM_ARCH_UPD, this was added to isolate the structure from x64 build. This is not really required since the x64 build uses FSP2.4 structures. BUG=b:343428206 TEST=Verified x86_32 and x86_64 builds on Meteor Lake board (Rex) Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82425 Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h 1 file changed, 0 insertions(+), 4 deletions(-) Approvals: Dinesh Gehlot: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h index 388fced..9efcfa9 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -155,8 +155,6 @@ UINT8 Reserved1[16]; } FSPT_ARCH2_UPD; -#if CONFIG(PLATFORM_USES_FSP2_X86_32) - /// /// FSPM_ARCH_UPD Configuration. /// @@ -204,8 +202,6 @@ UINT8 Reserved1[4]; } FSPM_ARCH_UPD; -#endif - /// /// FSPM_ARCH2_UPD Configuration for FSP 2.4 and above. /// -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 28 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: intelvbtupgrader: New tool to upgrade VBT files to newer versions
by Vladimir Serbinenko (Code Review) 31 May '24

31 May '24

Vladimir Serbinenko has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82722?usp=email ) Change subject: intelvbtupgrader: New tool to upgrade VBT files to newer versions ...................................................................... intelvbtupgrader: New tool to upgrade VBT files to newer versions Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 --- A util/intelvbtupgrader/.gitignore A util/intelvbtupgrader/Makefile A util/intelvbtupgrader/intelvbtupgrader.c 3 files changed, 219 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/82722/1 diff --git a/util/intelvbtupgrader/.gitignore b/util/intelvbtupgrader/.gitignore new file mode 100644 index 0000000..e39d748 --- /dev/null +++ b/util/intelvbtupgrader/.gitignore @@ -0,0 +1 @@ +intelvbtupgrader diff --git a/util/intelvbtupgrader/Makefile b/util/intelvbtupgrader/Makefile new file mode 100644 index 0000000..ee4259e --- /dev/null +++ b/util/intelvbtupgrader/Makefile @@ -0,0 +1,20 @@ +## +## SPDX-License-Identifier: GPL-2.0-only + +PROGRAM = intelvbtupgrader +CC ?= gcc +CFLAGS ?= -O2 -g +CFLAGS += -Wall -Werror +CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include + +all: $(PROGRAM) + +$(PROGRAM): $(PROGRAM).c + $(CC) $(CFLAGS) $(CPPFLAGS) $(PROGRAM).c -o $(PROGRAM) + +clean: + rm -f $(PROGRAM) + +distclean: clean + +.PHONY: all clean distclean diff --git a/util/intelvbtupgrader/intelvbtupgrader.c b/util/intelvbtupgrader/intelvbtupgrader.c new file mode 100644 index 0000000..d47addb --- /dev/null +++ b/util/intelvbtupgrader/intelvbtupgrader.c @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <commonlib/helpers.h> + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +}; + +static u8 csum = 0; +static FILE *fout = 0; +static FILE *fin; +static u8 buf[1 << 15]; + +static void write_block(void *data, size_t sz) +{ + u8 *b = data; + for (size_t i = 0; i < sz; i++) + csum += b[i]; + fwrite(b, 1, sz, fout); +} + +static void copy_chunk(size_t sz) +{ + if (sz > sizeof(buf)) { + printf("Copy too large"); + exit(1); + return; + } + fread(buf, 1, sz, fin); + write_block(buf, sz); +} + +static void zero_fill(size_t sz) +{ + if (sz > sizeof(buf)) { + printf("Zero fill too large"); + exit(1); + return; + } + memset(buf, 0, sz); + write_block(buf, sz); +} + +static u16 sec_sizes_240[256] = { + [254] = 0xea, [1] = 0x5, [253] = 0x42, [2] = 0x164, [252] = 0x7a, + [9] = 0x64, [10] = 0xcb, [12] = 0x13, [20] = 0xaa, [27] = 0x30c, + [40] = 0x22, [42] = 0x554, [43] = 0x131, [44] = 0x3a, [46] = 0x130, + [51] = 0x9, [52] = 0x336, [56] = 0xd2, [57] = 0xa52, [58] = 0x2a2, +}; + +static u16 sec_sizes_250[256] = { + [254] = 0xea, [1] = 0xa, [253] = 0x42, [2] = 0x164, [252] = 0x7a, + [9] = 0x64, [10] = 0xcb, [12] = 0x13, [20] = 0xaa, [27] = 0x32c, + [40] = 0x22, [42] = 0x556, [43] = 0x131, [44] = 0x4e, [46] = 0x130, + [51] = 0x9, [52] = 0x336, [56] = 0xd2, [57] = 0xa52, [58] = 0x2a2, +}; + +static struct { + const char *name; + int version; + const u16 *size_table; +} targets[] = { + {"2.40", 240, sec_sizes_240}, + {"2.50", 250, sec_sizes_250}, +}; + +int main(int argc, char **argv) +{ + if (argc < 4) { + printf("Usage: %s INPUT OUTPUT VERSION\n", argv[0]); + return 0; + } + + int targetid = -1; + + for (int i = 0; i < ARRAY_SIZE(targets); i++) + if (strcmp(targets[i].name, argv[3]) == 0) { + targetid = i; + break; + } + if (targetid == -1) { + printf("Unknown version %s\n", argv[3]); + return 0; + } + int target = targets[targetid].version; + fin = fopen(argv[1], "rb"); + struct vbt_header head; + fread(&head, sizeof(head), 1, fin); + printf("version: %d.%02d\n", head.version / 100, head.version % 100); + if (head.version != 100) { + printf("Head version not 1.00\n"); + return 0; + } + + u16 vbt_size = head.vbt_size; + head.vbt_size = 0; + head.vbt_checksum = 0; + + ssize_t extra_size = head.bdb_offset - sizeof(head); + if (extra_size < 0 || extra_size >= sizeof(buf)) { + printf("invalid BDB offset\n"); + return 0; + } + + fout = fopen(argv[2], "wb"); + + write_block(&head, sizeof(head)); + fread(buf, 1, extra_size, fin); + write_block(buf, extra_size); + struct bdb_header bdb_head; + size_t bdb_offset = ftell(fin); + + fread(&bdb_head, 1, sizeof(bdb_head), fin); + + if (bdb_head.version >= target) { + printf("Already at target or higher. Nothing to do\n"); + return 0; + } + + bdb_head.version = target; + + u16 bdb_size = bdb_head.bdb_size + 1; + + bdb_head.bdb_size = 0; + ssize_t extra_size2 = bdb_head.header_size - sizeof(bdb_head); + if (extra_size2 < 0 || extra_size2 >= sizeof(buf)) { + printf("invalid BDB header size\n"); + return 0; + } + write_block(&bdb_head, sizeof(bdb_head)); + copy_chunk(extra_size2); + + size_t bdb_contents_size = 0; + + for (int off = bdb_head.header_size; off < bdb_size;) { + fread(buf, 1, 3, fin); + u8 sectype = buf[0]; + u16 secsz = (buf[1] | (buf[2] << 8)); + int intended = targets[targetid].size_table[sectype]; + off += 3; + bdb_contents_size += 3; + if (intended <= secsz) { + write_block(buf, 3); + copy_chunk(secsz); + bdb_contents_size += secsz; + off += secsz; + } else { + buf[1] = intended; + buf[2] = intended >> 8; + write_block(buf, 3); + copy_chunk(secsz); + zero_fill(intended - secsz); + bdb_contents_size += intended; + off += intended; + } + } + ssize_t extra_size3 = vbt_size - bdb_size - head.bdb_offset; + copy_chunk(extra_size3); + + fseek(fout, bdb_offset + 20, SEEK_SET); + size_t bdbout_size = bdb_contents_size + extra_size2 + sizeof(bdb_head); + u16 b = bdbout_size - 1; + buf[0] = b; + buf[1] = b >> 8; + write_block(buf, 2); + fseek(fout, 24, SEEK_SET); + size_t vbtout_size = bdbout_size + extra_size + sizeof(head) + extra_size3; + buf[0] = vbtout_size; + buf[1] = vbtout_size >> 8; + write_block(buf, 2); + buf[0] = -csum; + write_block(buf, 1); + fclose(fin); + fclose(fout); + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie677403898b7b8ab9f57ad77668155bb55188769 Gerrit-Change-Number: 82722 Gerrit-PatchSet: 1 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel: Fix pointer size mismatch errors in crashlog
by Eric Lai (Code Review) 31 May '24

31 May '24

Attention is currently required from: Appukuttan V K, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Wonkyu Kim. Eric Lai has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82481?usp=email ) Change subject: soc/intel: Fix pointer size mismatch errors in crashlog ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d0814a8b767270ec140341bfb51d0782469545d Gerrit-Change-Number: 82481 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 10:00:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard
by Eric Lai (Code Review) 31 May '24

31 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar, Subrata Banik. Eric Lai has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Remove FSPM_ARCH_UPD config guard ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 27 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 31 May 2024 09:58:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: payloads/external/Makefile.mk: build iPXE for EDK2 with custom boot o...
by Filip Lewiński (Code Review) 31 May '24

31 May '24

Attention is currently required from: Michał Kopeć. Hello Michał Kopeć, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/82721?usp=email to review the following change. Change subject: payloads/external/Makefile.mk: build iPXE for EDK2 with custom boot option name ...................................................................... payloads/external/Makefile.mk: build iPXE for EDK2 with custom boot option name Change-Id: Ied61c7b8aa7a34261d6c6f7fd089b1affdc7d3f6 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M payloads/external/Makefile.mk 1 file changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/82721/1 diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index d497cf8..045c93a 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -156,7 +156,11 @@ # edk2 -$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) +ifeq ($(CONFIG_EDK2_ENABLE_IPXE),y) +IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom +endif + +$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) $(MAKE) -C payloads/external/edk2 UefiPayloadPkg \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ @@ -206,7 +210,8 @@ OBJCOPY_x86_64=$(OBJCOPY_x86_64) \ OBJCOPY_arm=$(OBJCOPY_arm) \ OBJCOPY_arm64=$(OBJCOPY_arm64) \ - MFLAGS= MAKEFLAGS= + MFLAGS= MAKEFLAGS= \ + CONFIG_EDK2_IPXE_OPTION_NAME=$(CONFIG_EDK2_IPXE_OPTION_NAME) $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/edk2 UniversalPayload \ @@ -364,13 +369,18 @@ IPXE_SERIAL_CONSOLE = n endif +ifneq ($(CONFIG_EDK2_ENABLE_IPXE),y) cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw +IPXE_CROSS_COMPILE:="$(CROSS_COMPILE_$(ARCH-ramstage-y))" +else +IPXE_CROSS_COMPILE:=$(CROSS_COMPILE_x86_64) +endif payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ - CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ + CROSS_COMPILE=$(IPXE_CROSS_COMPILE) \ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \ CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \ @@ -382,7 +392,9 @@ CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \ CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \ CONFIG_PXE_TRUST_CMD=$(CONFIG_PXE_TRUST_CMD) \ - MFLAGS= MAKEFLAGS= + MFLAGS= MAKEFLAGS= \ + CFLAGS_x86_64="$(CFLAGS_x86_64)" \ + CONFIG_IPXE_BUILD_EFI=$(CONFIG_EDK2_ENABLE_IPXE) \ # LinuxBoot LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86) = x86_32 -- To view, visit https://review.coreboot.org/c/coreboot/+/82721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied61c7b8aa7a34261d6c6f7fd089b1affdc7d3f6 Gerrit-Change-Number: 82721 Gerrit-PatchSet: 1 Gerrit-Owner: Filip Lewiński <filip.lewinski(a)3mdeb.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XS] Change in coreboot[main]: doc/distributions: Update NovaCustom domain
by Angel Pons (Code Review) 31 May '24

31 May '24

Attention is currently required from: Felix Singer, Wessel klein Snakenborg. Angel Pons has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/82159?usp=email ) Change subject: doc/distributions: Update NovaCustom domain ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > I confirm the URL change. […] I believe updating the text should be a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/82159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fe9c3a2e3335d0ea5a5352cc1948b1a82c327ec Gerrit-Change-Number: 82159 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Wessel klein Snakenborg Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Wessel klein Snakenborg Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Fri, 31 May 2024 09:20:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Wessel klein Snakenborg

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[S] Change in coreboot[main]: mb/google/trulo: Support OCP fault on A0/1 ports
by Subrata Banik (Code Review) 31 May '24

31 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82637?usp=email ) Change subject: mb/google/trulo: Support OCP fault on A0/1 ports ...................................................................... mb/google/trulo: Support OCP fault on A0/1 ports The devicetree entry and gpio.c updated as per the schematics of Trulo to map the OC fault signals from A0/A1 USB ports. BUG=b:335858378 TEST= Able to build google/trulo Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Signed-off-by: Pranava Y N <pranavayn(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82637 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/mainboard/google/brya/variants/trulo/gpio.c M src/mainboard/google/brya/variants/trulo/overridetree.cb 2 files changed, 10 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c index beee6fc..1a6d1b1 100644 --- a/src/mainboard/google/brya/variants/trulo/gpio.c +++ b/src/mainboard/google/brya/variants/trulo/gpio.c @@ -8,7 +8,10 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* TODO */ + /* A14 : USB_OC1# ==> USB_A0_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A14, NONE, NF1, LOCK_CONFIG), + /* A15 : USB_OC2# ==> USB_A1_FAULT_ODL */ + PAD_CFG_NF_LOCK(GPP_A15, NONE, NF1, LOCK_CONFIG), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index ee86142..9285c33 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/alderlake - device domain 0 on - end + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + + device domain 0 on + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic17debc5eecebca8c000c43a660e1b52d2932f2a Gerrit-Change-Number: 82637 Gerrit-PatchSet: 6 Gerrit-Owner: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mainboard/google/rex: Enable Rex64 build configuration
by Subrata Banik (Code Review) 31 May '24

31 May '24

Attention is currently required from: Eran Mitrani, Felix Singer, Jakub Czapiga, Martin L Roth, Paul Menzel, Tarun. Subrata Banik has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/82625?usp=email ) Change subject: mainboard/google/rex: Enable Rex64 build configuration ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Build is successful https://qa.coreboot.org/job/coreboot-gerrit/258212/console but stil no V+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02e2c49b4aeb2cb98d9d0cb66717db18c3f96d45 Gerrit-Change-Number: 82625 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Fri, 31 May 2024 08:45:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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