April 2024 - coreboot-gerrit - mail.coreboot.org

[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part
by Leo Chou (Code Review) April 1, 2024

April 1, 2024

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81612?usp=email ) Change subject: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part ...................................................................... mb/google/nissa/var/sundance: Generate SPD ID for supported memory part Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/memory/Makefile.mk M src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt 3 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81612/1 diff --git a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk index eace2e4..26dc4b0 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt index fa24790..fee3476 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56AK6BX069 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 3 (0011) diff --git a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt index 2499005..83001c1 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56AK6BX069 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/81612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Gerrit-Change-Number: 81612 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency
by Subrata Banik (Code Review) April 1, 2024

April 1, 2024

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81571?usp=email ) Change subject: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency ...................................................................... drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency This patch replaces UINT8 with uint8_t to align with coreboot's standard data type conventions. This promotes consistency within the codebase. BUG=b:242829490 TEST=Verified firmware splash screen functionality on google/rex0. Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/81571/1 diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index a43364a..8b64502 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -151,7 +151,7 @@ die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n", __func__); - bmp_image = ((UINT8 *)logo_ptr) + header->ImageOffset; + bmp_image = ((uint8_t *)logo_ptr) + header->ImageOffset; bmp_image_header = bmp_image; gop_blt_buffer = gop_blt_ptr; bmp_color_map = (efi_bmp_color_map *)(logo_ptr + sizeof(efi_bmp_image_header)); -- To view, visit https://review.coreboot.org/c/coreboot/+/81571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Gerrit-Change-Number: 81571 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81318?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... Patch Set 30: (1 comment) Patchset: PS30: > Hi, I'd like to say up front that this isn't a super big deal, and this message is just to bring thi […] Oh, thanks for heads-up :) -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 30 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:18:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD101NE3_40TI panel
by Yidi Lin (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81583?usp=email ) Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Gerrit-Change-Number: 81583 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:01:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Martin L Roth (Code Review) April 1, 2024

April 1, 2024

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... mb/google/{brya,hades}: use soc index for variant_update_power_limits() The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c 2 files changed, 68 insertions(+), 11 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 9c2d4aa..a7e5e8a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -11,11 +11,43 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + if (sa_pci_id == 0xffff) + return NULL; + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,20 +61,18 @@ for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", - limits[i].pl1_min_power, - limits[i].pl1_max_power, - limits[i].pl2_min_power, - limits[i].pl2_max_power, - limits[i].pl4_power); + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); } } } diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c index 4858eb7..7862dfe 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c @@ -11,11 +11,40 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,14 +58,12 @@ for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 12 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Martin L Roth (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar, Varshit Pandya. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 11 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:52:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Eric Lai (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Jérémy Compostella, Nico Huber. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81379?usp=email ) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:51:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Eric Lai (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Ashish Kumar Mishra, Deepti Deshatty, Shelley Chen, Varshit Pandya, Vijay P Hiremath. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:50:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by SH Kim (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Martin L Roth, Nick Vaccaro, Paul Menzel, Subrata Banik, Sumeet R Pawnikar, Varshit Pandya. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81436/comment/1f0758d3_52fb34a7 : PS10, Line 22: - Before this CL: msr_pl4 was not changed, it's always 114 : - After this CL: msr_pl4 was changed to 80 > When I click the hyperlink it opens "https://chromium-review.googlesource. […] Thanks. Just changed the comment CL -> patch to remove unintended hyperlink. -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 11 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:48:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
by Martin L Roth (Code Review) April 1, 2024

April 1, 2024

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81444?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC ...................................................................... mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC Update GPIO configuration according to the schematic changes. The locations of speaker and DMIC are swapped. - Speaker: I2S2 -> I2S1 - DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5 BUG=b:318584606 TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81444 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/xol/gpio.c 1 file changed, 14 insertions(+), 4 deletions(-) Approvals: Eric Lai: Looks good to me, approved SH Kim: Looks good to me, but someone else must approve Varshit Pandya: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 13fd10d..168d982 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -151,13 +151,23 @@ /* H23 : SRCCLKREQ5# ==> PU 100K 3.3V */ PAD_CFG_GPI(GPP_H23, NONE, DEEP), + /* R4 : HDA_RST# ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SNDW0_DATA ==> NC */ - PAD_NC(GPP_S1, NONE), + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Gerrit-Change-Number: 81444 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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