April 2024 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate SSDT device objects for off-SoC devices
by Patrick Rudolph (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Shuo Liu, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81568?usp=email ) Change subject: soc/intel/xeon_sp: Generate SSDT device objects for off-SoC devices ...................................................................... Patch Set 1: (2 comments) File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81568/comment/e9a2404e_0aaa6609 : PS1, Line 385: dev_bus_each_child not needed with RP PCI driver https://review.coreboot.org/c/coreboot/+/81568/comment/bb5c1f4a_8970b3df : PS1, Line 394: acpigen_write_SUN acpigen_write_name_integer("_SUN", psn); -- To view, visit https://review.coreboot.org/c/coreboot/+/81568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea8dab122ed2f0f3fb34d758400488a96b6a50ce Gerrit-Change-Number: 81568 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/device_util: Add is_pci_bridge
by Patrick Rudolph (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81566?usp=email ) Change subject: device/device_util: Add is_pci_bridge ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Gerrit-Change-Number: 81566 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:50:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate root port SSDT device objects
by Patrick Rudolph (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Shuo Liu, Tim Chu, Tim Wawrzynczak. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81567?usp=email ) Change subject: soc/intel/xeon_sp: Generate root port SSDT device objects ...................................................................... Patch Set 1: (2 comments) File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81567/comment/3ba48f8e_d3508f31 : PS1, Line 368: is_pci_bridge When it's a PCI bridge there should be a PCI driver for it, thus no need to have this separate method. File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/81567/comment/1a5d481b_618b6dbd : PS1, Line 176: ops Use a pci driver to set ops and name -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:50:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part
by Eric Lai (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Derek Huang, Dinesh Gehlot, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81612?usp=email ) Change subject: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Gerrit-Change-Number: 81612 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:48:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part
by Leo Chou (Code Review) April 1, 2024

April 1, 2024

Leo Chou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81612?usp=email ) Change subject: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part ...................................................................... mb/google/nissa/var/sundance: Generate SPD ID for supported memory part Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- M src/mainboard/google/brya/variants/sundance/memory/Makefile.mk M src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt 3 files changed, 20 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81612/1 diff --git a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk index eace2e4..26dc4b0 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt index fa24790..fee3476 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56AK6BX069 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 3 (0011) diff --git a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt index 2499005..83001c1 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56AK6BX069 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/81612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Gerrit-Change-Number: 81612 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency
by Subrata Banik (Code Review) April 1, 2024

April 1, 2024

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81571?usp=email ) Change subject: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency ...................................................................... drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency This patch replaces UINT8 with uint8_t to align with coreboot's standard data type conventions. This promotes consistency within the codebase. BUG=b:242829490 TEST=Verified firmware splash screen functionality on google/rex0. Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/81571/1 diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index a43364a..8b64502 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -151,7 +151,7 @@ die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n", __func__); - bmp_image = ((UINT8 *)logo_ptr) + header->ImageOffset; + bmp_image = ((uint8_t *)logo_ptr) + header->ImageOffset; bmp_image_header = bmp_image; gop_blt_buffer = gop_blt_ptr; bmp_color_map = (efi_bmp_color_map *)(logo_ptr + sizeof(efi_bmp_image_header)); -- To view, visit https://review.coreboot.org/c/coreboot/+/81571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Gerrit-Change-Number: 81571 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81318?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... Patch Set 30: (1 comment) Patchset: PS30: > Hi, I'd like to say up front that this isn't a super big deal, and this message is just to bring thi […] Oh, thanks for heads-up :) -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 30 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:18:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for KD_KD101NE3_40TI panel
by Yidi Lin (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81583?usp=email ) Change subject: drivers/mipi: Add support for KD_KD101NE3_40TI panel ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibed67d2f3321fef332ab1e80f06225e27d205f71 Gerrit-Change-Number: 81583 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 05:01:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Martin L Roth (Code Review) April 1, 2024

April 1, 2024

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... mb/google/{brya,hades}: use soc index for variant_update_power_limits() The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81436 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c 2 files changed, 68 insertions(+), 11 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index 9c2d4aa..a7e5e8a 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -11,11 +11,43 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + if (sa_pci_id == 0xffff) + return NULL; + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,20 +61,18 @@ for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", - limits[i].pl1_min_power, - limits[i].pl1_max_power, - limits[i].pl2_min_power, - limits[i].pl2_max_power, - limits[i].pl4_power); + limits[i].pl1_min_power, + limits[i].pl1_max_power, + limits[i].pl2_min_power, + limits[i].pl2_max_power, + limits[i].pl4_power); } } } diff --git a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c index 4858eb7..7862dfe 100644 --- a/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/hades/ramstage.c @@ -11,11 +11,40 @@ WEAK_DEV_PTR(dptf_policy); +static struct soc_power_limits_config *get_soc_power_limit_config(void) +{ + config_t *config = config_of_soc(); + size_t i; + struct device *sa = pcidev_path_on_root(SA_DEVFN_ROOT); + uint16_t sa_pci_id; + u8 tdp; + + if (!sa) + return NULL; + + sa_pci_id = pci_read_config16(sa, PCI_DEVICE_ID); + + tdp = get_cpu_tdp(); + + for (i = 0; i < ARRAY_SIZE(cpuid_to_adl); i++) { + if (sa_pci_id == cpuid_to_adl[i].cpu_id && + tdp == cpuid_to_adl[i].cpu_tdp) { + return &config->power_limits_config[cpuid_to_adl[i].limits]; + } + } + + return NULL; +} + void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) { if (!num_entries) return; + struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + if (!soc_config) + return; + const struct device *policy_dev = DEV_PTR(dptf_policy); if (!policy_dev) return; @@ -29,14 +58,12 @@ for (size_t i = 0; i < num_entries; i++) { if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { struct dptf_power_limits *settings = &config->controls.power_limits; - config_t *conf = config_of_soc(); - struct soc_power_limits_config *soc_config = conf->power_limits_config; settings->pl1.min_power = limits[i].pl1_min_power; settings->pl1.max_power = limits[i].pl1_max_power; settings->pl2.min_power = limits[i].pl2_min_power; settings->pl2.max_power = limits[i].pl2_max_power; soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, - MILLIWATTS_TO_WATTS); + MILLIWATTS_TO_WATTS); printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n", limits[i].pl1_min_power, limits[i].pl1_max_power, -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 12 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Martin L Roth (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar, Varshit Pandya. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 11 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:52:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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