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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81436/comment/44798180_07d2d68c :
PS10, Line 22: - Before this CL: msr_pl4 was not changed, it's always 114
: - After this CL: msr_pl4 was changed to 80
When I click the hyperlink it opens "https://chromium-review.googlesource.com/q/status:open+-is:wip" and not any particular CL. Not sure if that is what you intended to do.
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Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30:
Hi, I'd like to say up front that this isn't a super big deal, and this message is just to bring this to your attention.
It looks like you're rebasing a long patch train, so I wanted to ask that you not do this all at once. If you want to rebase a long patch train, please submit 10 patches to be rebased, wait for everything to finish, then rebase another 10 or so patches. This gives other people a chance to get their patches through the CI system as well, instead of having to wait for an hour or more until all of your patches get through. This is actually covered in the gerrit guidelines document.
Here are the gerrit guidelines in case you wanted to read through them:
https://doc.coreboot.org/contributing/gerrit_guidelines.html
Alternatively, if Intel wanted to donate some money to coreboot to spin up some additional build servers on demand, I'd be happy to make an exception. :)
Thanks.
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81436/comment/0eac681a_183cc102 :
PS9, Line 22: chaged
> Nit: changed
Done
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81436?usp=email
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
mb/google/{brya,hades}: use soc index for variant_update_power_limits()
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.
I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
{PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```
And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this CL: msr_pl4 was not changed, it's always 114
- After this CL: msr_pl4 was changed to 80
BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.
Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
2 files changed, 68 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81436/10
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Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81444/comment/ed23206a_a9cfcf8e :
PS3, Line 9: The locations of speaker and DMIC are swapped.
> Please wrap this line.
Done
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Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
......................................................................
mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
Update GPIO configuration according to the schematic changes. The
locations of speaker and DMIC are swapped.
- Speaker: I2S2 -> I2S1
- DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5
BUG=b:318584606
TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage
Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/xol/gpio.c
1 file changed, 14 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/81444/4
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81418?usp=email )
Change subject: mb/google/brox: Configure ISH device based on FW_CONFIG
......................................................................
mb/google/brox: Configure ISH device based on FW_CONFIG
ISH Firmware name needs to be configured only when full sensing
capabilities are enabled through ISH_ENABLE FW_CONFIG. Similarly DMA
property needs to be added only when UFS is enabled through STORAGE_UFS
FW_CONFIG. Hence configure the ISH device at run-time based on
FW_CONFIG.
BUG=b:319164720
TEST=Build Brox BIOS image and boot to OS.
Change-Id: I678416acd48e03ab77ae299beae6e295a688b8df
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81418
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
---
M src/mainboard/google/brox/variants/brox/fw_config.c
M src/mainboard/google/brox/variants/brox/overridetree.cb
2 files changed, 14 insertions(+), 4 deletions(-)
Approvals:
Varshit Pandya: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c
index 162f4a1..d8fd44d 100644
--- a/src/mainboard/google/brox/variants/brox/fw_config.c
+++ b/src/mainboard/google/brox/variants/brox/fw_config.c
@@ -1,10 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootstate.h>
+#include <drivers/intel/ish/chip.h>
#include <fw_config.h>
#include <gpio.h>
#define GPIO_PADBASED_OVERRIDE(b, a) gpio_padbased_override(b, a, ARRAY_SIZE(a))
+#define ISH_FIRMWARE_NAME "brox_ish.bin"
static const struct pad_config ish_enable_pads[] = {
/* GPP_B5 : ISH I2C0_SDA */
@@ -27,9 +29,19 @@
static void fw_config_handle(void *unused)
{
+ struct device *ish_config_device = DEV_PTR(ish_conf);
+ struct drivers_intel_ish_config *config = config_of(ish_config_device);
+
if (fw_config_probe(FW_CONFIG(ISH, ISH_ENABLE))) {
- printk(BIOS_INFO, "Configure GPIOs for ISH.\n");
+ printk(BIOS_INFO, "Configure GPIOs, device config for ISH.\n");
gpio_configure_pads(ish_enable_pads, ARRAY_SIZE(ish_enable_pads));
+
+ config->firmware_name = ISH_FIRMWARE_NAME;
+ }
+
+ if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) {
+ printk(BIOS_INFO, "Configure GPIOs, device config for UFS.\n");
+ config->add_acpi_dma_property = true;
}
}
BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index 2c4335b..7b00098 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -300,9 +300,7 @@
end
device ref ish on
chip drivers/intel/ish
- register "firmware_name" = ""brox_ish.bin""
- register "add_acpi_dma_property" = "true"
- device generic 0 on end
+ device generic 0 alias ish_conf on end
end
probe ISH ISH_ENABLE
probe STORAGE STORAGE_UFS
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81436/comment/51680085_ff73eace :
PS9, Line 22: chaged
Nit: changed
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81444/comment/ca91acf2_978c47a3 :
PS3, Line 9: The locations of speaker and DMIC are swapped.
Please wrap this line.
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Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81552?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/nissa/var/glassway: Add 2nd Synaptics touchpad
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mb/google/nissa/var/glassway: Add 2nd Synaptics touchpad
Add Synaptics touchpad via HID-I2C interface in I2C5 bus for glassway.
BUG=b:331677400
BRANCH=firmware-nissa-15217.B
TEST=emerge-brya coreboot and check touchpad function work.
[INFO ] input: PNP0C50:00 06CB:CE9B Touchpad as /devices/pci0000:00/0000:00:19.1/i2c_designware.5/i2c-17/i2c-PNP0C50:00/0018:06CB:CE9B.0001/input/input4
[INFO ] hid-multitouch 0018:06CB:CE9B.0001: input,hidraw0: I2C HID v1.00 Device [PNP0C50:00 06CB:CE9B] on i2c-PNP0C50:00
Change-Id: Ifbb2cb750a80bc6e8f96609257dcd1e695ad1fa4
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81552
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <ericllai(a)google.com>
Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com>
---
M src/mainboard/google/brya/variants/glassway/overridetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
Approvals:
Varshit Pandya: Looks good to me, but someone else must approve
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Frank Chu: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb
index 29629d4..64c8ee0 100644
--- a/src/mainboard/google/brya/variants/glassway/overridetree.cb
+++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb
@@ -384,6 +384,15 @@
register "detect" = "1"
device i2c 15 on end
end
+ chip drivers/i2c/hid
+ register "generic.hid" = ""PNP0C50""
+ register "generic.desc" = ""PIXART Touchpad""
+ register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
+ register "generic.wake" = "GPE0_DW2_14"
+ register "generic.detect" = "1"
+ register "hid_desc_reg_offset" = "0x20"
+ device i2c 2c on end
+ end
end #I2C5
device ref pcie_rp4 on
# Enable wlan PCIe 4 using clk 2
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