April 2024 - coreboot-gerrit - mail.coreboot.org

[M] Change in coreboot[main]: mb/google/brya/var/xol: Configure power limits by battery status
by SH Kim (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, SH Kim, Sumeet R Pawnikar. Hello Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81614?usp=email to look at the new patch set (#3). Change subject: mb/google/brya/var/xol: Configure power limits by battery status ...................................................................... mb/google/brya/var/xol: Configure power limits by battery status When battery level is below critical level or battery is not present, cpus need to run with a power optimized configuration to avoid platform instabilities such as system power down. This will check the current battery status and configure cpu power limits using current PD power value. BUG=b:328729536 TEST=built and veified MSR PL2/PL4 values using PTAT. Original power limit configuration for Xol: MSR PL2: 55W, MSR PL4: 114W. [When connected 60W adaptor without battery] Before: MSR PL2: 55W, MSR PL4: 114W After: MSR PL2: 55W, MSR PL4: 60W [When connected 45W adaptor without battery] Before: MSR PL2: 55W, MSR PL4: 114W After: MSR PL2: 45W, MSR PL4: 45W Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brya/variants/xol/Makefile.mk A src/mainboard/google/brya/variants/xol/ramstage.c 4 files changed, 65 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/81614/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Gerrit-Change-Number: 81614 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
by Subrata Banik (Code Review) April 1, 2024

April 1, 2024

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81615?usp=email ) Change subject: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t ...................................................................... drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t Replaces fixed-width integers for pointers and sizes with uintptr_t and size_t, promoting portability across 32-bit and 64-bit architectures. For FSP-API specific UPD assignments, relying on `efi_uintn_t` rather fixed size datatype uint32_t/uint64_t. BUG=b:242829490 TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and 64-bit compilation. Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h M src/include/bootsplash.h M src/lib/bmp_logo.c 4 files changed, 10 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81615/1 diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index 8b64502..52e4595 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -133,7 +133,7 @@ /* Fill BMP image into BLT buffer format */ static void *fill_blt_buffer(efi_bmp_image_header *header, - uint32_t logo_ptr, uint32_t blt_buffer_size) + uintptr_t logo_ptr, size_t blt_buffer_size) { efi_graphics_output_blt_pixel *gop_blt_buffer; efi_graphics_output_blt_pixel *gop_blt_ptr; @@ -233,11 +233,12 @@ } /* Convert a *.BMP graphics image to a GOP blt buffer */ -void fsp_convert_bmp_to_gop_blt(uint32_t *logo, uint32_t *logo_size, - uint32_t *blt_ptr, uint32_t *blt_size, +void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size, + efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width) { - uint32_t logo_ptr, logo_ptr_size, blt_buffer_size; + uintptr_t logo_ptr; + size_t logo_ptr_size, blt_buffer_size; efi_bmp_image_header *bmp_header; if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width) @@ -265,5 +266,5 @@ *blt_size = blt_buffer_size; *pixel_height = bmp_header->PixelHeight; *pixel_width = bmp_header->PixelWidth; - *blt_ptr = (uint32_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size); + *blt_ptr = (uintptr_t)fill_blt_buffer(bmp_header, logo_ptr, blt_buffer_size); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h index 7ffb54c..ff15483 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h +++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h @@ -7,8 +7,8 @@ #include <types.h> /* Convert a *.BMP graphics image to a GOP blt buffer */ -void fsp_convert_bmp_to_gop_blt(uint32_t *logo, uint32_t *logo_size, - uint32_t *blt_ptr, uint32_t *blt_size, +void fsp_convert_bmp_to_gop_blt(efi_uintn_t *logo, uint32_t *logo_size, + efi_uintn_t *blt_ptr, efi_uintn_t *blt_size, uint32_t *pixel_height, uint32_t *pixel_width); #endif /* FSP_GOP_BLT_H */ diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 86048a4..0c9b032 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -20,7 +20,7 @@ * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS */ const char *bmp_logo_filename(void); -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size); +void bmp_load_logo(uintptr_t *logo_ptr, size_t *logo_size); void bmp_release_logo(void); #endif diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 2888777..ee0626a 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -16,7 +16,7 @@ } #endif -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size) +void bmp_load_logo(uintptr_t *logo_ptr, size_t *logo_size) { void *logo_buffer; -- To view, visit https://review.coreboot.org/c/coreboot/+/81615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Gerrit-Change-Number: 81615 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: device/device_util: Add is_pci_bridge
by Felix Singer (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81566?usp=email ) Change subject: device/device_util: Add is_pci_bridge ...................................................................... Patch Set 1: (1 comment) File src/device/device_util.c: https://review.coreboot.org/c/coreboot/+/81566/comment/a649a92c_34a4b6d3 : PS1, Line 939: ( The outer parentheses are not needed, please remove -- To view, visit https://review.coreboot.org/c/coreboot/+/81566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Gerrit-Change-Number: 81566 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 07:00:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency
by Paul Menzel (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Andrey Petrov, Ronak Kanabar, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81571?usp=email ) Change subject: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Gerrit-Change-Number: 81571 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:53:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part
by Paul Menzel (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Derek Huang, Dinesh Gehlot, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81612?usp=email ) Change subject: mb/google/nissa/var/sundance: Generate SPD ID for supported memory part ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81612/comment/83920221_0a2bd56e : PS1, Line 7: for supported memory part … for 4 supported memory parts -- To view, visit https://review.coreboot.org/c/coreboot/+/81612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Gerrit-Change-Number: 81612 Gerrit-PatchSet: 1 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_stack_mmios
by Shuo Liu (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81570?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_stack_mmios ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81570/comment/3776a576_a24154a5 : PS1, Line 10: unused IOAT MMIOs (CPM1 and HQM1). These resources are within stack > How do you read the stack MMIO range? is there a HOB for that? xSTACK_RES *sr->PciResourceMem64Base/Limit is the portion for PCI device xSTACK_RES *sr->Mmio64Base/Limit is the total MMIO range e.g. in CXL domain setting up, non PCI resources are used if (sr->Mmio64Base < sr->PciResourceMem64Base) { res = new_resource(dev, index++); res->base = sr->Mmio64Base; res->limit = sr->PciResourceMem64Base - 1; res->size = res->limit - res->base + 1; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED; } https://review.coreboot.org/c/coreboot/+/81570/comment/b089a85f_89d3067e : PS1, Line 10: unused > what does unused mean? When it decodes MMIO, it's not unused, is it? in void create_ioat_domains(const union xeon_domain_path path ...), HQM1 and CPM1 MMIO64 will be always reserved, but for SKUs that is not with HQM1 and CPM1, these resources are not assigned to domains, thus forming MTRR segmentation. Will update the commit message. File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/81570/comment/980b072d_f3c40678 : PS1, Line 135: while (from && (from->path.type != DEVICE_PATH_DOMAIN) && This check is not correct, will update. -- To view, visit https://review.coreboot.org/c/coreboot/+/81570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a8063d8bee8fb4b5578e84ba8f9951815ffbf3 Gerrit-Change-Number: 81570 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/xol: Configure power limits by battery status
by Paul Menzel (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, SH Kim, Sumeet R Pawnikar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81614?usp=email ) Change subject: mb/google/brya/var/xol: Configure power limits by battery status ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81614/comment/4c3bc9bf_d12657e9 : PS2, Line 10: platform : instabilities What instabilities occur? Please elaborate? Doesn’t the battery just drain faster? https://review.coreboot.org/c/coreboot/+/81614/comment/7b847a46_41c7dc32 : PS2, Line 18: MSR PL2: 55W, MSR PL4: 114W Please document the command you used to get these. File src/mainboard/google/brya/variants/xol/ramstage.c: https://review.coreboot.org/c/coreboot/+/81614/comment/a6447c05_7635d367 : PS2, Line 24: Log the non-zero return value? https://review.coreboot.org/c/coreboot/+/81614/comment/32fe9c32_772b8d24 : PS2, Line 64: performance The commit message says *power*? -- To view, visit https://review.coreboot.org/c/coreboot/+/81614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Gerrit-Change-Number: 81614 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:51:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate root port SSDT device objects
by Shuo Liu (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81567?usp=email ) Change subject: soc/intel/xeon_sp: Generate root port SSDT device objects ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpigen_pci.c: https://review.coreboot.org/c/coreboot/+/81567/comment/34a20914_eafd741f : PS1, Line 368: is_pci_bridge > When it's a PCI bridge there should be a PCI driver for it, thus no need to have this separate metho […] Sure, good suggestion, will update. -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:46:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: device/device_util: Add is_pci_bridge
by Paul Menzel (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81566?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: device/device_util: Add is_pci_bridge ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81566/comment/8d46dace_75fe5f6b : PS1, Line 7: Add Add and use is_pci_bridge() -- To view, visit https://review.coreboot.org/c/coreboot/+/81566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Gerrit-Change-Number: 81566 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/xol: Configure power limits by battery status
by Subrata Banik (Code Review) April 1, 2024

April 1, 2024

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, SH Kim, Sumeet R Pawnikar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81614?usp=email ) Change subject: mb/google/brya/var/xol: Configure power limits by battery status ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/xol/ramstage.c: https://review.coreboot.org/c/coreboot/+/81614/comment/e83edd29_4362b702 : PS2, Line 28: get_soc_power_limit_config this is already present inside baseboard/brya. why not leveraging the same ? src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:14:static struct soc_power_limits_config *get_soc_power_limit_config(void) I don't see any need for redundant implementation across baseboard and variant -- To view, visit https://review.coreboot.org/c/coreboot/+/81614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Gerrit-Change-Number: 81614 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 06:36:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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