coreboot-gerrit April 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Arthur Heymans (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Shuo Liu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/81349/comment/ca561531_393b1387 : PS15, Line 164: /* Only call this code from socket0! */ : static void unlock_pam_regions(void) : { : uint32_t pam0123_unlock_dram = 0x33333330; : uint32_t pam456_unlock_dram = 0x00333333; : /* Get UBOX(1) for socket0 */ : uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); : : /* Assume socket0 owns PCI segment 0 */ : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM456_CSR, pam456_unlock_dram); : : uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); : uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); : printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", : __FILE__, __func__, reg1, reg2); : } Why is this code duplicated in cpx and skx. It was also valid for SPR-SP but not used. Why not have the function definiton in common code but call it in SOC specific code? -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 15 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 08:32:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Arthur Heymans (Code Review) 01 Apr '24

01 Apr '24

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: It's moved from romstage to ramstage on platforms that we think need it. The commit message does not say why or whether this was tested. Care to explain? -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 15 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 08:31:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Swap LAN device indices
by Tony Huang (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, Zhuohao Lee. Hello Derek Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81564?usp=email to look at the new patch set (#4). Change subject: mb/google/rex/var/deku: Swap LAN device indices ...................................................................... mb/google/rex/var/deku: Swap LAN device indices Deku has 2 ethernet ports, due to the LAN devices indices were swapped. So set vpd ethernet_mac0 will affect the eth1 and set vpd ethernet_mac1 will affect the eth0 from ifconfig. This CL is to correct the device indices for LAN devices so ethernet_mac[0-1] in vpd can apply to the correct ethernet ports. BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=vpd -s ethernet_mac0=<mac address0> vpd -s ethernet_mac1=<mac address1> reboot the system and check ifconfig eth0 and eth1 MAC addresses are fetched correctly Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81564/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Gerrit-Change-Number: 81564 Gerrit-PatchSet: 4 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Swap LAN device indices
by Tony Huang (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, Zhuohao Lee. Hello Derek Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81564?usp=email to look at the new patch set (#3). Change subject: mb/google/rex/var/deku: Swap LAN device indices ...................................................................... mb/google/rex/var/deku: Swap LAN device indices Deku has 2 ethernet ports, due to the LAN devices indices were swaped. So set vpd ethernet_mac0 will affect the eth1 and set vpd ethernet_mac1 will affect the eth0 from ifconfig. This CL is to correct the device indices for LAN devices so ethernet_mac[0-1] in vpd can apply to the correct ethernet ports. BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=vpd -s ethernet_mac0=<mac address0> vpd -s ethernet_mac1=<mac address1> reboot the system and check ifconfig eth0 and eth1 MAC addresses are fetched correctly Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81564/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Gerrit-Change-Number: 81564 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Swap LAN device indices
by Tony Huang (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, Zhuohao Lee. Tony Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81564?usp=email ) Change subject: mb/google/rex/var/deku: Swap LAN device indices ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81564/comment/afe163cf_a61be81e : PS1, Line 7: Correct LAN device index > Swap LAN device indices Done https://review.coreboot.org/c/coreboot/+/81564/comment/7a3313c9_79cbc7a6 : PS1, Line 9: Correct LAN device index to match MAC from VPD setting. > Please start by describing the problem. […] Done https://review.coreboot.org/c/coreboot/+/81564/comment/e7a6af7a_37315895 : PS1, Line 16: address was > addresses are Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Gerrit-Change-Number: 81564 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 08:13:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex/var/deku: Swap LAN device indices
by Tony Huang (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tony Huang, Zhuohao Lee. Hello Derek Huang, Dinesh Gehlot, Eran Mitrani, Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Zhuohao Lee, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81564?usp=email to look at the new patch set (#2). Change subject: mb/google/rex/var/deku: Swap LAN device indices ...................................................................... mb/google/rex/var/deku: Swap LAN device indices Deku has 2 ethernet ports, due to the LAN device indices was swaped. So set vpd ethernet_mac0 will affect the eth1 and set vpd ethernet_mac1 will affect the eth0 from ifconfig. This CL is to correct the device indices for LAN devices so ethernet_mac[0-1] in vpd can apply to the correct ethernet ports. BUG=b:320203629 BRANCH=firmware-rex-15709.B TEST=vpd -s ethernet_mac0=<mac address0> vpd -s ethernet_mac1=<mac address1> reboot the system and check ifconfig eth0 and eth1 MAC addresses are fetched correctly Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/81564/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id1508104cbb5cf0a234f34f9db19cc535fdb634b Gerrit-Change-Number: 81564 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Lean Sheng Tan (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 08:11:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Lean Sheng Tan (Code Review) 01 Apr '24

01 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... soc/intel/xeon_sp: Remove PAM unlock operations unlock_pam_regions routes Programmable Attribute Map (PAM) access to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the step to SoC specific codes. TEST=intel/archercity CRB Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/util.c 5 files changed, 51 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 1fc9c75..b0e61b6 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -161,8 +161,32 @@ set_bios_init_completion(); } +/* Only call this code from socket0! */ +static void unlock_pam_regions(void) +{ + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + /* Get UBOX(1) for socket0 */ + uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); + + /* Assume socket0 owns PCI segment 0 */ + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + static void chip_init(void *data) { + unlock_pam_regions(); + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 5904b16..177d6d5 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -9,7 +9,6 @@ #define MEM_ADDR_64MB_SHIFT_BITS 26 void lock_pam0123(void); -void unlock_pam_regions(void); msr_t read_msr_ppin(void); int get_platform_thread_count(void); diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 9084f2a..8af5dd8 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -24,8 +24,6 @@ } } - unlock_pam_regions(); - save_dimm_info(); } diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index d8b3161..fe16e05 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -3,6 +3,9 @@ #include <cbfs.h> #include <console/console.h> #include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> @@ -35,8 +38,32 @@ } } +/* Only call this code from socket0! */ +static void unlock_pam_regions(void) +{ + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + /* Get UBOX(1) for socket0 */ + uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); + + /* Assume socket0 owns PCI segment 0 */ + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} + static void soc_init(void *data) { + unlock_pam_regions(); + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index b3ee02b..81dc77d 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -17,28 +17,6 @@ #include <soc/util.h> #include <timer.h> -/* Only call this code from socket0! */ -void unlock_pam_regions(void) -{ - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - /* Get UBOX(1) for socket0 */ - uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); - - /* Assume socket0 owns PCI segment 0 */ - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - msr_t read_msr_ppin(void) { msr_t ppin = {0}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 15 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya: Make get_soc_power_limit_config() a public function
by Eric Lai (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, SH Kim. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81616?usp=email ) Change subject: mb/google/brya: Make get_soc_power_limit_config() a public function ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Gerrit-Change-Number: 81616 Gerrit-PatchSet: 2 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 08:06:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Lean Sheng Tan (Code Review) 01 Apr '24

01 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... acpi: Add acpigen_write_OSC_pci_domain Add dynamic PCI domain _OSC ASL generation codes, supporting both PCIe and CXL domains. Dynamic SSDT generation is used to generate a list of ASL device objects based on FSP outputs (e.g. the SoC/SKU configurations) and _OSC is a method inside these objects (hence it would be straightforward to be generated altogether, plus some C codes managed boot configs could be referenced as well). This usage is optional. It is helpful for cases where the same code set supports multiple SKUs/SoCs (difficult to be handled by one set of static SSDT), and the CPU performance is good enough to run SSDT generation logics with minimal costs. TEST=intel/archercity CRB Tested with https://review.coreboot.org/c/coreboot/+/81377. Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81375 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h 2 files changed, 316 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index 3edf0d0..a23b84c 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -55,3 +55,308 @@ acpigen_pop_len(); /* Package */ } + +#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" +#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" + +#define OSC_RET_FAILURE 0x02 +#define OSC_RET_UNRECOGNIZED_UUID 0x04 +#define OSC_RET_UNRECOGNIZED_REV 0x08 +#define OSC_RET_CAPABILITIES_MASKED 0x10 + +#define OSC_QUERY_SUPPORT_SET 0x01 + +#define ASL_UUID_UNHANDLED 0x00 +#define ASL_UUID_HANDLED 0x01 + +static void acpigen_OSC_handle_pcie_request(const struct device *domain); +static void acpigen_OSC_handle_cxl_request(const struct device *domain); + +/* + * acpigen_write_OSC_pci_domain + * + * Reference: + * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Devic… + * + * _OSC ASL Arguments: (4) + * Arg0 - A Buffer containing a UUID + * Arg1 - An Integer containing a Revision ID of the buffer format + * Arg2 - An Integer containing a count of entries in Arg3 + * Arg3 - A Buffer containing a list of DWORD capabilities + * + * _OSC ASL Return Value: + * A Buffer containing a list of capabilities + * + * Local Variables Assignment: + * Local0 - Temp assigned + * Local1 - Temp assigned + * Local2 - Not used + * Local3 - Not used + * Local4 - Not used + * Local5 - Not used + * Local6 - Record whether the UUID is handled + * Local7 - Backs up the input value of Arg3 + * + * Field Definitions: + * Name - Width Source Offset Description + * -------------------------------- + * QSUP - DWord Local7 0x00 Query support + * RETE - DWord Arg3 0x00 Returned errors + * SUPP - Dword Arg3 0x04 PCIe Features that OS supported + * CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS + * OTRL - Dword Local7 0x08 PCIe Features that OS requests for control + * SUPC - Dword Arg3 0x0C CXL Features that OS supported + * CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS + * OTRC - Dword Local7 0x10 CXL Features that OS requests for control + */ +void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain) +{ + /* + * Method (_OSC, 4, NotSerialized) + * { + */ + acpigen_write_method("_OSC", 4); + + /* + * // + * // Check revision ID + * // + * If (Arg1 != 1) + * { + * RETE = OSC_RET_UNRECOGNIZED_REV + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG1_OP); + acpigen_write_integer(0x1); + + acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_REV, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * // + * // Setup up local variables + * // + * Local7 = Arg3 + * CreateDwordField (Local7, 0x00, QSUP) + * CreateDWordField (Arg3, 0x00, RETE) + * RETE = 0x0 + * Local6 = ASL_UUID_UNHANDLED + */ + acpigen_write_store_ops(ARG3_OP, LOCAL7_OP); + acpigen_write_create_dword_field(LOCAL7_OP, 0x00, "QSUP"); + acpigen_write_create_dword_field(ARG3_OP, 0x00, "RETE"); + acpigen_write_store_int_to_namestr(0x0, "RETE"); + acpigen_write_store_int_to_op(ASL_UUID_UNHANDLED, LOCAL6_OP); + + /* + * // + * // Refer to CXL-3.1-Specification, 9.18.2 + * // A CXL Host Bridge also originates a PCIe hierarchy and will have a + * // _CID of EISAID("PNP0A08"). As such, a CXL Host Bridge device may expose + * // both CXL _OSC and PCIe _OSC. + * // + * + * If (Arg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) + * { + * // + * // Handle PCIe _OSC request + * // Mark UUID handled + * // + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); + + acpigen_OSC_handle_pcie_request(domain); + acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); + + acpigen_write_if_end(); + + if (is_cxl_domain) { + /* + * If (Arg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID)) + * { + * // + * // Handle CXL _OSC request + * // Mark UUID handled + * // + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID); + + acpigen_OSC_handle_cxl_request(domain); + acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); + + acpigen_write_if_end(); + } + + /* + * // + * // Handle unrecognized UUID + * // + * If (Local6 == ASL_UUID_UNHANDLED) + * { + * RETE = OSC_RET_UNRECOGNIZED_UUID + * } + */ + acpigen_write_if_lequal_op_int(LOCAL6_OP, ASL_UUID_UNHANDLED); + acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_UUID, "RETE"); + acpigen_write_if_end(); + + /* + * // + * // All done, return + * // + * Return (Arg3) + */ + acpigen_write_return_op(ARG3_OP); + + /* + * } // Method (_OSC, 4, NotSerialized) + */ + acpigen_pop_len(); + +} + +void acpigen_OSC_handle_pcie_request(const struct device *domain) +{ + uint32_t osc_features = soc_get_granted_pci_features(domain); + + /* + * If (Arg2 < 2)) + * { + * RETE = OSC_RET_FAILURE + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LLESS_OP); + acpigen_emit_byte(ARG2_OP); + acpigen_write_integer(0x2); + + acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * CreateDWordField (Arg3, 0x04, SUPP) + * CreateDWordField (Arg3, 0x08, CTRL) + * CreateDWordField (Local7, 0x08, OTRL) + */ + acpigen_write_create_dword_field(ARG3_OP, 0x04, "SUPP"); + acpigen_write_create_dword_field(ARG3_OP, 0x08, "CTRL"); + acpigen_write_create_dword_field(LOCAL7_OP, 0x08, "OTRL"); + + /* + * // Grant PCIe feature controls to OS + * CTRL &= osc_features + */ + acpigen_write_to_integer_from_namestring("CTRL", LOCAL0_OP); + acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); + acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); + acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRL"); + + /* + * If (CTRL != OTRL) + * { + * RETE = OSC_RET_CAPABILITIES_MASKED + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("CTRL"); + acpigen_emit_namestring("OTRL"); + acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); + acpigen_write_if_end(); +}; + +void acpigen_OSC_handle_cxl_request(const struct device *domain) +{ + uint32_t osc_features = soc_get_granted_cxl_features(domain); + + /* + * If (Arg2 < 4)) + * { + * RETE = OSC_RET_FAILURE + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LLESS_OP); + acpigen_emit_byte(ARG2_OP); + acpigen_write_integer(0x4); + + acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * CreateDWordField (Arg3, 0x0C, SUPC) + * CreateDWordField (Arg3, 0x10, CTRC) + * CreateDWordField (Local7, 0x10, OTRC) + */ + acpigen_write_create_dword_field(ARG3_OP, 0x0C, "SUPC"); + acpigen_write_create_dword_field(ARG3_OP, 0x10, "CTRC"); + acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC"); + + /* + * // Grant CXL feature controls to OS + * CTRC &= osc_features + */ + acpigen_write_to_integer_from_namestring("CTRC", LOCAL0_OP); + acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); + acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); + acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRC"); + + /* + * If (CTRC != OTRC) + * { + * RETE = OSC_RET_CAPABILITIES_MASKED + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("CTRC"); + acpigen_emit_namestring("OTRC"); + acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); + acpigen_write_if_end(); +}; + +__weak uint32_t soc_get_granted_pci_features(const struct device *domain) +{ + /* + * By default grant no features to OS, which equals to the case where _OSC + * is absent. + * + * Refer to PCI firmware specification, revision 3.1. + * If the _OSC control method is absent from the scope of a host bridge device, then + * the operating system must not enable or attempt to use any features defined in this + * section for the hierarchy originated by the host bridge. Doing so could contend with + * platform firmware operations or produce undesired results. + */ + return 0; +} + +__weak uint32_t soc_get_granted_cxl_features(const struct device *domain) +{ + /* + * By default grant no features to OS, which equals to the case where _OSC + * is absent. + */ + return 0; +} diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 69216ec..7a07423 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -7,6 +7,13 @@ #include <device/pci_def.h> #include <device/pci_type.h> +#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 +#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 +#define PCIE_PME_CONTROL 0x04 +#define PCIE_AER_CONTROL 0x08 +#define PCIE_CAP_STRUCTURE_CONTROL 0x10 +#define PCIE_LTR_CONTROL 0x20 + void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); @@ -16,4 +23,8 @@ void pci_domain_fill_ssdt(const struct device *domain); +void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain); +uint32_t soc_get_granted_pci_features(const struct device *domain); +uint32_t soc_get_granted_cxl_features(const struct device *domain); + #endif /* ACPIGEN_PCI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 19 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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