coreboot-gerrit April 2024

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[S] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Enable the MIPI panel KD_KD101NE3_40TI
by Yang Wu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Ruihai Zhou, Xuxin Xiong, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81585?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/corsola/var/wugtrio: Enable the MIPI panel KD_KD101NE3_40TI ...................................................................... mb/google/corsola/var/wugtrio: Enable the MIPI panel KD_KD101NE3_40TI Enable the K&D Technology MIPI panel KD_KD101NE3_40TI for Wugtrio. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage and display normally BRANCH=Corsola Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Makefile.mk A src/mainboard/google/corsola/panel_wugtrio.c 3 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/81585/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Gerrit-Change-Number: 81585 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/corsola: Add new board variant Wugtrio
by Yang Wu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Eric Lai, Hung-Te Lin, Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu, Yu-Ping Wu. Hello Eric Lai, Hung-Te Lin, Ruihai Zhou, Xuxin Xiong, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81584?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai Change subject: mb/google/corsola: Add new board variant Wugtrio ...................................................................... mb/google/corsola: Add new board variant Wugtrio Add a new Staryu follower device 'Wugtrio'. BUG=b:331870701 TEST=emerge-staryu coreboot chromeos-bootimage BRANCH=corsola Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81584/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Gerrit-Change-Number: 81584 Gerrit-PatchSet: 4 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 32: (1 comment) Patchset: PS32: > Wait sorry, there are a few parts that are not directly related to GNR. […] Sure, for the parts to split from this one, any suggestions? -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 13:02:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Lean Sheng Tan (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) The change is no longer submittable: All-Comments-Resolved and Code-Review are unsatisfied now. Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 32: Code-Review+1 (1 comment) Patchset: PS32: Wait sorry, there are a few parts that are not directly related to GNR. would you mind to split them up into separate patch? -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 11:49:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... Patch Set 15: (1 comment) File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/81349/comment/ccc936fa_74a5b318 : PS15, Line 164: /* Only call this code from socket0! */ : static void unlock_pam_regions(void) : { : uint32_t pam0123_unlock_dram = 0x33333330; : uint32_t pam456_unlock_dram = 0x00333333; : /* Get UBOX(1) for socket0 */ : uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); : : /* Assume socket0 owns PCI segment 0 */ : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM456_CSR, pam456_unlock_dram); : : uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); : uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); : printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", : __FILE__, __func__, reg1, reg2); : } > This is because this code cannot pass compilation with the GNR target. […] New patch made - https://review.coreboot.org/c/coreboot/+/81619 -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 15 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 11:09:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Share unlock_pam_regions()
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81619?usp=email ) Change subject: soc/intel/xeon_sp: Share unlock_pam_regions() ...................................................................... soc/intel/xeon_sp: Share unlock_pam_regions() unlock_pam_regions() is needed for SKX and CPX. Put the codes into chip_gen1.c so that it could be shared among SoC generations. After shared, unlock_pam_regions() is still called from SKX and CPX SoC specific codes. SPR will also use chip_gen1.c, but it will not call unlock_pam_regions(). TEST=intel/archercity CRB Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/skx/chip.c 4 files changed, 30 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81619/1 diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index 80ffdda..99f5bd9 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -4,6 +4,9 @@ #include <assert.h> #include <console/console.h> #include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> #include <intelblocks/acpi.h> #include <post.h> #include <soc/acpi.h> @@ -199,3 +202,28 @@ else if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(sr)) create_ioat_domains(dp, bus, sr, pci_segment_group); } + +/* + * Route PAM segment access to DRAM + * Only call this code from socket0! + */ +void unlock_pam_regions(void) +{ + uint32_t pam0123_unlock_dram = 0x33333330; + uint32_t pam456_unlock_dram = 0x00333333; + /* Get UBOX(1) for socket0 */ + uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); + + /* Assume socket0 owns PCI segment 0 */ + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); + pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + SAD_ALL_PAM456_CSR, pam456_unlock_dram); + + uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); + uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); + printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", + __FILE__, __func__, reg1, reg2); +} diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index b0e61b6..9c86aee 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -161,28 +161,6 @@ set_bios_init_completion(); } -/* Only call this code from socket0! */ -static void unlock_pam_regions(void) -{ - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - /* Get UBOX(1) for socket0 */ - uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); - - /* Assume socket0 owns PCI segment 0 */ - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - static void chip_init(void *data) { unlock_pam_regions(); diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 3740426..c499f62 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -89,4 +89,6 @@ #define is_dev_on_domain0(dev) (is_domain0(dev_get_pci_domain(dev))) #define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) +void unlock_pam_regions(void); + #endif /* _CHIP_COMMON_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index fe16e05..903d0cc 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -3,9 +3,6 @@ #include <cbfs.h> #include <console/console.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <soc/pci_devs.h> #include <gpio.h> #include <intelblocks/acpi.h> #include <soc/acpi.h> @@ -38,28 +35,6 @@ } } -/* Only call this code from socket0! */ -static void unlock_pam_regions(void) -{ - uint32_t pam0123_unlock_dram = 0x33333330; - uint32_t pam456_unlock_dram = 0x00333333; - /* Get UBOX(1) for socket0 */ - uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); - - /* Assume socket0 owns PCI segment 0 */ - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM456_CSR, pam456_unlock_dram); - - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, - SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); - printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", - __FILE__, __func__, reg1, reg2); -} - static void soc_init(void *data) { unlock_pam_regions(); -- To view, visit https://review.coreboot.org/c/coreboot/+/81619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37 Gerrit-Change-Number: 81619 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/brya/var/sundance: Add GPIO table
by Paul Menzel (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81613?usp=email ) Change subject: mb/google/brya/var/sundance: Add GPIO table ...................................................................... Patch Set 4: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81613/comment/33082dfe_f48e0f9d : PS4, Line 9: Follow the NEC_SHIKIBU_ADL_N_MB_EVT_20240329 and fill GPIO table for Sundance. Please wrap the line after 72 characters. -- To view, visit https://review.coreboot.org/c/coreboot/+/81613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Gerrit-Change-Number: 81613 Gerrit-PatchSet: 4 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 10:38:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib: Use platform-independent types in bmp_load_logo()
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Ronak Kanabar, Sean Rhodes. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81618?usp=email ) Change subject: lib: Use platform-independent types in bmp_load_logo() ...................................................................... lib: Use platform-independent types in bmp_load_logo() This patch replaces fixed-width integers with uintptr_t/size_t in bmp_load_logo() parameters. This is an initial step towards wider portability improvements. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/include/bootsplash.h M src/lib/bmp_logo.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c 8 files changed, 13 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81618/1 diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 5c40966..5a3f073 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -77,8 +77,8 @@ mainboard_silicon_init_params(&silicon_init_params); if (CONFIG(BMP_LOGO)) - bmp_load_logo(&silicon_init_params.PcdLogoPtr, - &silicon_init_params.PcdLogoSize); + bmp_load_logo((uintptr_t *)&silicon_init_params.PcdLogoPtr, + (size_t *)&silicon_init_params.PcdLogoSize); /* Display the UPD data */ if (CONFIG(DISPLAY_UPD_DATA)) diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index a43364a..34cb1b1 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -243,7 +243,7 @@ if (!logo || !logo_size || !blt_ptr || !blt_size || !pixel_height || !pixel_width) return; - bmp_load_logo(&logo_ptr, &logo_ptr_size); + bmp_load_logo((uintptr_t *)&logo_ptr, (size_t *)&logo_ptr_size); if (!logo_ptr || logo_ptr_size < sizeof(efi_bmp_image_header)) { printk(BIOS_ERR, "%s: BMP Image size is too small.\n", __func__); return; diff --git a/src/include/bootsplash.h b/src/include/bootsplash.h index 86048a4..0c9b032 100644 --- a/src/include/bootsplash.h +++ b/src/include/bootsplash.h @@ -20,7 +20,7 @@ * For example: Introduce configurable BMP logo for customization on platforms like ChromeOS */ const char *bmp_logo_filename(void); -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size); +void bmp_load_logo(uintptr_t *logo_ptr, size_t *logo_size); void bmp_release_logo(void); #endif diff --git a/src/lib/bmp_logo.c b/src/lib/bmp_logo.c index 2888777..ee0626a 100644 --- a/src/lib/bmp_logo.c +++ b/src/lib/bmp_logo.c @@ -16,7 +16,7 @@ } #endif -void bmp_load_logo(uint32_t *logo_ptr, uint32_t *logo_size) +void bmp_load_logo(uintptr_t *logo_ptr, size_t *logo_size) { void *logo_buffer; diff --git a/src/soc/amd/mendocino/fsp_s_params.c b/src/soc/amd/mendocino/fsp_s_params.c index 8374fb3..3cfbef9 100644 --- a/src/soc/amd/mendocino/fsp_s_params.c +++ b/src/soc/amd/mendocino/fsp_s_params.c @@ -55,6 +55,6 @@ void soc_load_logo(FSPS_UPD *supd) { - uint32_t logo_size; - bmp_load_logo(&supd->FspsConfig.logo_bmp_buffer, &logo_size); + size_t logo_size; + bmp_load_logo((uintptr_t *)&supd->FspsConfig.logo_bmp_buffer, &logo_size); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 91e39c9..6cb0c5a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -915,7 +915,8 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + bmp_load_logo((uintptr_t *)&supd->FspsConfig.LogoPtr, + (size_t *)&supd->FspsConfig.LogoSize); } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c9ef548..44fa83f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -754,5 +754,6 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + bmp_load_logo((uintptr_t *)&supd->FspsConfig.LogoPtr, + (size_t *)&supd->FspsConfig.LogoSize); } diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ea091ce..fd8b278 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -529,5 +529,6 @@ /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + bmp_load_logo((uintptr_t *)&supd->FspsConfig.LogoPtr, + (size_t *)&supd->FspsConfig.LogoSize); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Gerrit-Change-Number: 81618 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Ronak Kanabar. Hello Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81615?usp=email to look at the new patch set (#5). Change subject: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t ...................................................................... drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t Replace fixed-width integers for pointers and sizes with uintptr_t and size_t, promoting portability across 32-bit and 64-bit architectures. For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather fixed size datatype uint32_t/uint64_t. BUG=b:242829490 TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and 64-bit compilation. Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h 2 files changed, 9 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81615/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Gerrit-Change-Number: 81615 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... Patch Set 15: (2 comments) Patchset: PS15: > It's moved from romstage to ramstage on platforms that we think need it. […] Sure, unlock_pam_region() will route the access to PAM-F segment to DRAM, coreboot places ACPI RSDP lower pointer here, without RSDP pointer, LinuxBoot cannot boot. In SPR, FSP covered such unlock operations (confirmed from source code), and after removed from coreboot, the coreboot ACPI table can still be accessed by LinuxBoot, hence it proves the removal is okay for SPR. (for GNR, the same). For the calling site of the unlock in CPX and SKX, it is moved from late romstage and early ramstage, which is close to each other. From the ACPI table write point of view, they are similar. However, only compilation test are executed for SKX and CPX. File src/soc/intel/xeon_sp/cpx/chip.c: https://review.coreboot.org/c/coreboot/+/81349/comment/95563f6e_6ac2b76e : PS15, Line 164: /* Only call this code from socket0! */ : static void unlock_pam_regions(void) : { : uint32_t pam0123_unlock_dram = 0x33333330; : uint32_t pam456_unlock_dram = 0x00333333; : /* Get UBOX(1) for socket0 */ : uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); : : /* Assume socket0 owns PCI segment 0 */ : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); : pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), : SAD_ALL_PAM456_CSR, pam456_unlock_dram); : : uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); : uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, : SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); : printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", : __FILE__, __func__, reg1, reg2); : } > Why is this code duplicated in cpx and skx. It was also valid for SPR-SP but not used. […] This is because this code cannot pass compilation with the GNR target. If we would like to further share the codes, I can make another patch to put this into chip_gen1.c. Your opinion? -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 15 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 10:19:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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