coreboot-gerrit April 2024

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[M] Change in coreboot[main]: mb/google/brya/var/sundance: Add GPIO table
by Leo Chou (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Leo Chou, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik. Hello Derek Huang, Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81613?usp=email to look at the new patch set (#5). Change subject: mb/google/brya/var/sundance: Add GPIO table ...................................................................... mb/google/brya/var/sundance: Add GPIO table Follow the NEC_SHIKIBU_ADL_N_MB_EVT_20240329 and fill GPIO table for Sundance. BUG=b:327520553 TEST=emerge-nissa coreboot Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> --- A src/mainboard/google/brya/variants/sundance/Makefile.inc A src/mainboard/google/brya/variants/sundance/gpio.c 2 files changed, 115 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/81613/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53ed5874347006985ca5231d1531fa519088f796 Gerrit-Change-Number: 81613 Gerrit-PatchSet: 5 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: security/tpm: replace CONFIG(TPMx) checks with runtime check
by Julius Werner (Code Review) 02 Apr '24

02 Apr '24

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69161?usp=email ) Change subject: security/tpm: replace CONFIG(TPMx) checks with runtime check ...................................................................... Patch Set 36: (1 comment) File src/drivers/tpm/ppi.c: https://review.coreboot.org/c/coreboot/+/69161/comment/4d10c372_3d7581de : PS36, Line 574: BIOS_WARN > Thanks for fixing this. […] No, a missing identifier should still be found long before it gets to any optimization passes. I think this whole file isn't checked by Jenkins. You should add or change a config in `configs/` to set `CONFIG_TPM_PPI` to close that testing gap. -- To view, visit https://review.coreboot.org/c/coreboot/+/69161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id9cc25aad8d1d7bfad12b7a92059b1b3641bbfa9 Gerrit-Change-Number: 69161 Gerrit-PatchSet: 36 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jan Samek <samekh(a)email.cz> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 00:10:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/corsola: Add new board variant Wugtrio
by Yidi Lin (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Eric Lai, Hung-Te Lin, Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81584?usp=email ) Change subject: mb/google/corsola: Add new board variant Wugtrio ...................................................................... Patch Set 6: (1 comment) Patchset: PS6: please rebase to ToT -- To view, visit https://review.coreboot.org/c/coreboot/+/81584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84cb86bf4eb2762b3072cb030b3c34a08c6b869d Gerrit-Change-Number: 81584 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 00:09:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/brya/var/xol: Reduce power limits according to battery status
by SH Kim (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jamie Chen, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Sumeet R Pawnikar. SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81614?usp=email ) Change subject: mb/google/brya/var/xol: Reduce power limits according to battery status ...................................................................... Patch Set 5: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81614/comment/1134c008_0837ea79 : PS2, Line 18: MSR PL2: 55W, MSR PL4: 114W > Sorry, I do not know what PTAT is. Done Commit Message: https://review.coreboot.org/c/coreboot/+/81614/comment/2e8aa06d_19e605c2 : PS4, Line 7: Configure power limits by battery status > Maybe: […] Thanks for the suggestion. Modified from it due to the length. https://review.coreboot.org/c/coreboot/+/81614/comment/c1b9e320_24a1e6cd : PS4, Line 18: veified > verified Done https://review.coreboot.org/c/coreboot/+/81614/comment/52805753_f4dd5e9c : PS4, Line 23: adaptor > adapt*e*r Done https://review.coreboot.org/c/coreboot/+/81614/comment/ee63ca65_0cb05c5b : PS4, Line 29: adaptor > Ditto. Done File src/mainboard/google/brya/variants/xol/ramstage.c: https://review.coreboot.org/c/coreboot/+/81614/comment/c509ffc5_e90c085e : PS4, Line 27: printk(BIOS_INFO, "Cannot get PD power info\n"); > Please also print the return value. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77d Gerrit-Change-Number: 81614 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 01 Apr 2024 23:32:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Subrata Banik has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81623?usp=email ) Change subject: vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility ...................................................................... vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility This change refactors EDK2 essential header management within the FSP directory to ensure compatibility. Header selection is now dynamically based on: * FSP specification version: Distinguishes between 1.1 and 2.x * EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header FSP Header | |-> FSP 1.1 specification FSP_INFO_HEADER |-> FSP 2.0 specification EDK2 release |-> EDK2_2017 FSP_INFO_HEADER |-> EDK2_2020 FSP_INFO_HEADER |-> EDK2_2021 FSP_INFO_HEADER |-> EDK2_2023 FSP_INFO_HEADER Any .C/.H file requires to include FSP_INFO_HEADER can now just add the FSP header alone. BUG=b:242829490 TEST=Able to build google/rex0 with 64-bit FSP. Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- A src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h A src/vendorcode/intel/fsp/fsp_header.h 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/81623/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff Gerrit-Change-Number: 81623 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: commonlib: Simplify FSP header inclusion
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81624?usp=email ) Change subject: commonlib: Simplify FSP header inclusion ...................................................................... commonlib: Simplify FSP header inclusion Include `fsp_header.h` from vendorcode for dynamic FSP_INFO_HEADER selection. BUG=b:242829490 TEST=google/rex0 builds successfully with 64-bit FSP. Change-Id: If165e0517752f320d898cf82f298aa9f5699ae86 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/commonlib/fsp_relocate.c 1 file changed, 1 insertion(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81624/1 diff --git a/src/commonlib/fsp_relocate.c b/src/commonlib/fsp_relocate.c index 96d31b3..f57e278 100644 --- a/src/commonlib/fsp_relocate.c +++ b/src/commonlib/fsp_relocate.c @@ -4,24 +4,11 @@ #include <commonlib/endian.h> #include <commonlib/fsp.h> #include <inttypes.h> -/* - * Intel's code does not have a handle on changing global packing state. - * Therefore, one needs to protect against packing policies that are set - * globally for a compilation unit just by including a header file. - */ -#pragma pack(push) - -/* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ -#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> -#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> - -/* Restore original packing policy. */ -#pragma pack(pop) - #include <commonlib/helpers.h> #include <stddef.h> #include <stdint.h> #include <string.h> +#include <vendorcode/intel/fsp/fsp_header.h> #define FSP_DBG_LVL BIOS_NEVER #define MASK_24BITS 0x00FFFFFF -- To view, visit https://review.coreboot.org/c/coreboot/+/81624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If165e0517752f320d898cf82f298aa9f5699ae86 Gerrit-Change-Number: 81624 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81623?usp=email ) Change subject: vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility ...................................................................... vc/intel/fsp: Refactor FSP header inclusion for EDK2 compatibility This change refactors EDK2 essential header management within the FSP directory to ensure compatibility. Header selection is now dynamically based on: * FSP specification version: Distinguishes between 1.1 and 2.x * EDK2 revision (for FSP 2.x): Chooses the appropriate FSP info header FSP Header | |-> FSP 1.1 specification FSP_INFO_HEADER |-> FSP 2.0 specification EDK2 release |-> EDK2_2017 FSP_INFO_HEADER |-> EDK2_2020 FSP_INFO_HEADER |-> EDK2_2021 FSP_INFO_HEADER |-> EDK2_2023 FSP_INFO_HEADER Any .C/.H file requires to include FSP_INFO_HEADER can now just add the FSP header alone. BUG=b:242829490 TEST=Able to build google/rex0 with 64-bit FSP. Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- A src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h A src/vendorcode/intel/fsp/fsp_header.h 2 files changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/81623/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h b/src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h new file mode 100644 index 0000000..93495c4 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _FSP_INFO_HEADER_H_ +#define _FSP_INFO_HEADER_H_ + +#if CONFIG_UDK_VERSION == CONFIG_UDK_2017_VERSION +#include <vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h> +#elif CONFIG_UDK_VERSION == CONFIG_UDK_202005_VERSION +#include <vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h> +#elif CONFIG_UDK_VERSION == CONFIG_UDK_202111_VERSION +#include <vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h> +#elif CONFIG_UDK_VERSION == CONFIG_UDK_2022_VERSION +#include <vendorcode/intel/edk2/edk2-stable2022/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h> +#elif CONFIG_UDK_VERSION == CONFIG_UDK_202302_VERSION +#include <vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h> +#else +#error "Unknown UDK_VESION!" +#endif + +#endif /* _FSP_INFO_HEADER_H_ */ diff --git a/src/vendorcode/intel/fsp/fsp_header.h b/src/vendorcode/intel/fsp/fsp_header.h new file mode 100644 index 0000000..148e8d5 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp_header.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _FSP_HEADER_H_ +#define _FSP_HEADER_H_ + +/* + * Intel's code does not have a handle on changing global packing state. + * Therefore, one needs to protect against packing policies that are set + * globally for a compilation unit just by including a header file. + */ +#pragma pack(push) +/* Default bind edk2 UEFI 2.4 types. */ +#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> + +#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION +#include <vendorcode/intel/fsp/fsp2_0/IntelFspPkg/Include/FspInfoHeader.h> +#else +#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> +#endif +#pragma pack(pop) + +#endif /* _FSP_HEADER_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29e5002821843c9cffbc8f6317d1062175f014ff Gerrit-Change-Number: 81623 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibility
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81622?usp=email ) Change subject: vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibility ...................................................................... vc/intel/edk2: Define FSP_SIG macro for FSP 2.x compatibility This patch introduces the FSP_SIG macro into EDK2 headers to ensure compilation compatibility when using FSP 2.x specifications. Previously, the macro was only defined for FSP 1.1. BUG=b:242829490 TEST=Successful build of google/rex0 with 64-bit FSP. Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h M src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h M src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h M src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h 4 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81622/1 diff --git a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 472880f..ceeeede 100644 --- a/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/src/vendorcode/intel/edk2/UDK2017/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -30,6 +30,8 @@ #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') +#define FSP_SIG 0x48505346 /* 'FSPH' */ + #pragma pack(1) /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 24e2012..6e22aca 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/src/vendorcode/intel/edk2/edk2-stable202005/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -24,6 +24,8 @@ #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') +#define FSP_SIG 0x48505346 /* 'FSPH' */ + #pragma pack(1) /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 6751af1..3c3c9a5 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/src/vendorcode/intel/edk2/edk2-stable202111/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -24,6 +24,8 @@ #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') +#define FSP_SIG 0x48505346 /* 'FSPH' */ + #pragma pack(1) /// diff --git a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h index 9ea1b2f..daaed24 100644 --- a/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h +++ b/src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -32,6 +32,8 @@ #define FSP_IA32 0 #define FSP_X64 1 +#define FSP_SIG 0x48505346 /* 'FSPH' */ + #pragma pack(1) /// -- To view, visit https://review.coreboot.org/c/coreboot/+/81622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f97fc303ca2881ccd17b4d149d01c3b671dbbde Gerrit-Change-Number: 81622 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Andrey Petrov, Chen, Gang C, Jincheng Li, Jérémy Compostella, Martin L Roth, Ronak Kanabar, Shuo Liu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80323?usp=email ) Change subject: drivers/intel/fsp2_0: Default to 64-bits for FSP 2.4 ...................................................................... Patch Set 27: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/80323/comment/fd546e90_06659246 : PS27, Line 62: Starting with FSP specification 2.4 they can be 64-bits. help to rewrite this statement. -- To view, visit https://review.coreboot.org/c/coreboot/+/80323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec98 Gerrit-Change-Number: 80323 Gerrit-PatchSet: 27 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 17:31:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel: Align FSP debug handler with EFI calling convention
by Subrata Banik (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Andrey Petrov, Ronak Kanabar. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81621?usp=email ) Change subject: drivers/intel: Align FSP debug handler with EFI calling convention ...................................................................... drivers/intel: Align FSP debug handler with EFI calling convention Ensures the FSP debug handler adheres to the EFI calling convention, enabling seamless integration with coreboot infrastructure. This is critical for 64-bit coreboot and FSP communications. BUG=b:242829490 TEST=FSP debug logs successfully captured via coreboot event handler. Change-Id: I9085a6c7d50e58fb56cbbc61da3a0af094d0dc05 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_debug_event.c M src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/81621/1 diff --git a/src/drivers/intel/fsp2_0/fsp_debug_event.c b/src/drivers/intel/fsp2_0/fsp_debug_event.c index 2ebecc0..4b3e151a 100644 --- a/src/drivers/intel/fsp2_0/fsp_debug_event.c +++ b/src/drivers/intel/fsp2_0/fsp_debug_event.c @@ -17,7 +17,7 @@ return FSP_SUCCESS; } -efi_return_status_t fsp_debug_event_handler(efi_status_code_type_t ignored1, +__efiapi efi_return_status_t fsp_debug_event_handler(efi_status_code_type_t ignored1, efi_status_code_value_t ignored2, efi_uint32_t ignored3, efi_guid_t *ignored4, efi_status_code_data_t *data) { diff --git a/src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h b/src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h index 7d50c1e..149629a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h +++ b/src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h @@ -12,7 +12,7 @@ #include <fsp/soc_binding.h> /* fsp debug event handler */ -efi_return_status_t fsp_debug_event_handler(efi_status_code_type_t ignored1, +__efiapi efi_return_status_t fsp_debug_event_handler(efi_status_code_type_t ignored1, efi_status_code_value_t ignored2, efi_uint32_t ignored3, efi_guid_t *ignored4, efi_status_code_data_t *data); -- To view, visit https://review.coreboot.org/c/coreboot/+/81621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9085a6c7d50e58fb56cbbc61da3a0af094d0dc05 Gerrit-Change-Number: 81621 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newchange

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