coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3285 discussions

[XS] Change in coreboot[main]: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL The RPL FSP currently uses HECI commands to retrieve the chipset initialization version because the MBP HOB creation is disabled (SkipMbpHob=1). This has resulted in an approximate 150ms increase in boot time. Investigations are ongoing to determine the cause of the delay when using HECI commands. As an interim solution, this patch sets SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset initialization version, which is expected to reduce the boot time. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With this patch: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) Without this patch: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 01d5f89..5086069 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -517,7 +517,7 @@ config FSP_PUBLISH_MBP_HOB bool - default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) + default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) default y help This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. @@ -526,8 +526,7 @@ Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the - later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based - platforms. + later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. config INCLUDE_HSPHY_IN_FMAP bool "Include PCIe 5.0 HSPHY firmware in flash" -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 8 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81349?usp=email ) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... Patch Set 14: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81349/comment/f63d4e44_0689af35 : PS13, Line 11: some SoCs > which ones? Updated. File src/soc/intel/xeon_sp/util.c: https://review.coreboot.org/c/coreboot/+/81349/comment/e4222311_e13b1df2 : PS5, Line 115: lock_pam0123 > This doesn't answer the question. […] I need some more time to clarify lock_pam0123, hence I remove the related parts from this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:01:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Ashish Kumar Mishra (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Deepti Deshatty, Eric Lai, Shelley Chen, Varshit Pandya, Vijay P Hiremath. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81207/comment/c668d2b2_208d4312 : PS1, Line 9: For PMC-PD communication we need to enable 3 pins. > this information for SoC (about native function) is captured in it's datasheet (EDS in your case), t […] Done File src/mainboard/google/brox/variants/baseboard/brox/gpio.c: https://review.coreboot.org/c/coreboot/+/81207/comment/09d572dc_e249ca07 : PS2, Line 105: NC > should remove NC? Acknowledged https://review.coreboot.org/c/coreboot/+/81207/comment/7690ae66_a36abb31 : PS2, Line 137: NC > same Acknowledged https://review.coreboot.org/c/coreboot/+/81207/comment/141141cf_03b89c70 : PS2, Line 139: NC > same Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:01:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit Pandya <pandyavarshit(a)gmail.com> Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_stack_mmios
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81570?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_stack_mmios ...................................................................... soc/intel/xeon_sp: Add soc_add_stack_mmios IIO stacks will reserve some non-domain owned resources, e.g. unused IOAT MMIOs (CPM1 and HQM1). These resources are within stack MMIO range but outside domain MMIO range. They needs to be reserved explicitly so that covered by MTRR UC policy. Besides MTRR correctness, another benefit is less MTRR entries due to less segmented MTRR regions. Change-Id: Ib2a8063d8bee8fb4b5578e84ba8f9951815ffbf3 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/chip_gen1.c M src/soc/intel/xeon_sp/chip_gen6.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/uncore.c 6 files changed, 87 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/81570/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 8f5c024..4d6e3a8 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -125,6 +125,21 @@ return dev; } +struct device *dev_find_all_domains_on_stack(uint8_t socket, uint8_t stack, struct device *from) +{ + if (!from) + from = all_devices; + else + from = from->next; + + while (from && (from->path.type != DEVICE_PATH_DOMAIN) && + (iio_pci_domain_socket_from_dev(from) != socket) && + (iio_pci_domain_stack_from_dev(from) != stack)) + from = from->next; + + return from; +} + /** * Returns the socket ID where the specified device is connected to. * This is an integer in the range [0, CONFIG_MAX_SOCKET). @@ -263,3 +278,64 @@ return strstr(dev->name, DOMAIN_TYPE_CXL); } + +const xSTACK_RES *domain_to_stack_res(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_DOMAIN); + const union xeon_domain_path dn = { + .domain_path = dev->path.domain.domain + }; + + const IIO_UDS *hob = get_iio_uds(); + assert(hob != NULL); + + return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; +} + +int soc_add_stack_mmios(struct device *dev, int start_index) +{ + const struct device *domain = dev_get_domain(dev); + if (!domain) + return 0; + + const xSTACK_RES *sr = domain_to_stack_res(domain); + if (!is_enabled_stack_res(sr)) + return 0; + + int index = start_index; + + struct memranges mmio32, mmio64; + memranges_init_empty(&mmio32, NULL, 0); + if (sr->Mmio32Base <= sr->Mmio32Limit) + memranges_insert(&mmio32, sr->Mmio32Base, + sr->Mmio32Limit - sr->Mmio32Base + 1, 0); + memranges_init_empty(&mmio64, NULL, 0); + if (sr->Mmio64Base <= sr->Mmio64Limit) + memranges_insert(&mmio64, sr->Mmio64Base, + sr->Mmio64Limit - sr->Mmio64Base + 1, 0); + + union xeon_domain_path dn; + dn.domain_path = domain->path.domain.domain; + struct device *d = NULL; + while ((d = dev_find_all_domains_on_stack(dn.socket, dn.stack, d))) { + struct resource *res; + for (res = d->resource_list; res; res = res->next) { + if ((res->flags & IORESOURCE_MEM) && + (res->base >= sr->Mmio32Base && + res->limit <= sr->Mmio32Limit)) + memranges_create_hole(&mmio32, res->base, res->size); + else if ((res->flags & IORESOURCE_MEM) && + (res->base >= sr->Mmio64Base && + res->limit <= sr->Mmio64Limit)) + memranges_create_hole(&mmio64, res->base, res->size); + } + } + + struct range_entry *cur; + for (cur = mmio32.entries; cur != NULL; cur = cur->next) + mmio_from_to(dev, index++, cur->begin, cur->end + 1); + for (cur = mmio64.entries; cur != NULL; cur = cur->next) + mmio_from_to(dev, index++, cur->begin, cur->end + 1); + + return index - start_index; +} diff --git a/src/soc/intel/xeon_sp/chip_gen1.c b/src/soc/intel/xeon_sp/chip_gen1.c index ce95c13..c574b7f 100644 --- a/src/soc/intel/xeon_sp/chip_gen1.c +++ b/src/soc/intel/xeon_sp/chip_gen1.c @@ -14,19 +14,6 @@ #include <soc/util.h> #include <stdlib.h> -static const STACK_RES *domain_to_stack_res(const struct device *dev) -{ - assert(dev->path.type == DEVICE_PATH_DOMAIN); - const union xeon_domain_path dn = { - .domain_path = dev->path.domain.domain - }; - - const IIO_UDS *hob = get_iio_uds(); - assert(hob != NULL); - - return &hob->PlatformData.IIO_resource[dn.socket].StackRes[dn.stack]; -} - static void iio_pci_domain_read_resources(struct device *dev) { struct resource *res; diff --git a/src/soc/intel/xeon_sp/chip_gen6.c b/src/soc/intel/xeon_sp/chip_gen6.c index 5873913..17a9383 100644 --- a/src/soc/intel/xeon_sp/chip_gen6.c +++ b/src/soc/intel/xeon_sp/chip_gen6.c @@ -6,6 +6,7 @@ #include <drivers/ocp/include/vpd.h> #include <device/pci.h> #include <intelblocks/acpi.h> +#include <memrange.h> #include <post.h> #include <soc/acpi.h> #include <soc/chip_common.h> diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 798398a..44845ce 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -70,6 +70,7 @@ u16 vendor, u16 device, struct device *from); struct device *dev_find_all_devices_on_domain(struct device *domain, u16 vendor, u16 device, struct device *from); +struct device *dev_find_all_domains_on_stack(uint8_t socket, uint8_t stack, struct device *from); int iio_pci_domain_socket_from_dev(const struct device *dev); int iio_pci_domain_stack_from_dev(const struct device *dev); @@ -89,6 +90,8 @@ #define is_dev_on_domain0(dev) (is_domain0(dev_get_domain(dev))) #define is_stack0(socket, stack) (socket == 0 && stack == IioStack0) +const xSTACK_RES *domain_to_stack_res(const struct device *dev); + enum { TOHM_REG, MMIOL_REG, @@ -108,6 +111,7 @@ }; int soc_add_dram_resources(struct device *dev, uint64_t mc_values[], int start_index); +int soc_add_stack_mmios(struct device *dev, int start_index); void soc_pci_domain_fill_ssdt(const struct device *domain); diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index e694af3..53982f1 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -27,6 +27,10 @@ bool is_ubox_stack_res(const xSTACK_RES *res); bool is_ioat_iio_stack_res(const xSTACK_RES *res); bool is_iio_cxl_stack_res(const xSTACK_RES *res); +#define is_enabled_stack_res(res) (is_pcie_iio_stack_res(res) ||\ + is_ubox_stack_res(res) || is_ioat_iio_stack_res(res) ||\ + is_iio_cxl_stack_res(res)) + void bios_done_msr(void *unused); union p2sb_bdf soc_get_hpet_bdf(void); union p2sb_bdf soc_get_ioapic_bdf(void); diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index c700816..5f1ebf7 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -197,6 +197,8 @@ LOG_RESOURCE("vtd_bar", dev, res); } + index += soc_add_stack_mmios(dev, index); + /* Only add dram resources once. */ if (dev->upstream->secondary != 0 || dev->upstream->segment_group != 0) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/81570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a8063d8bee8fb4b5578e84ba8f9951815ffbf3 Gerrit-Change-Number: 81570 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add xeonsp_acpigen_write_PRT_pci_bridge
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81569?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add xeonsp_acpigen_write_PRT_pci_bridge ...................................................................... soc/intel/xeon_sp: Add xeonsp_acpigen_write_PRT_pci_bridge Add support of _PRT SSDT generation for PCI domain and root ports. The routing info is based on PCI interrupt pin/line info configured in pch_pirq_init() ahead of time. Change-Id: I98497523d11fcdd3724bc6b09585a3fe17fec2a7 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/gnr/chip.c M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 4 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/81569/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9881138..1c2ef76 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,10 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <assert.h> +#include <device/pci_ops.h> #include <intelblocks/acpi.h> #include <soc/chip_common.h> #include <soc/pci_devs.h> #include <soc/util.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #include <stdint.h> #include <stdlib.h> @@ -206,3 +210,43 @@ return NULL; } + +void xeonsp_acpigen_write_PRT_pci_bridge(const struct device *br) +{ + int dev_num = 0; + uint32_t routed_dev_bitmap = 0; + char *entry_count; + + if ((!is_pci_bridge(br)) && (br->path.type != DEVICE_PATH_DOMAIN)) + return; + + const char *acpi_scope = acpi_device_path(br); + if (!acpi_scope) + return; + + acpigen_write_scope(acpi_scope); + acpigen_write_name("_PRT"); + entry_count = acpigen_write_package(0); + + struct device *dev = NULL; + while ((dev = dev_bus_each_child(br->downstream, dev))) { + if (!is_pci(dev)) + continue; + dev_num = PCI_SLOT(dev->path.pci.devfn); + if (routed_dev_bitmap & (1 << dev_num)) + continue; + + uint8_t int_line = pci_read_config8(dev, PCI_INTERRUPT_LINE); + uint8_t int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if ((int_pin > PCI_INT_MAX) || (int_pin < PCI_INT_A)) + continue; + + acpigen_write_PRT_GSI_entry(dev_num, int_pin - PCI_INT_A, int_line); + + (*entry_count)++; + routed_dev_bitmap |= (1 << dev_num); + } + + acpigen_pop_len(); + acpigen_pop_len(); +} diff --git a/src/soc/intel/xeon_sp/gnr/chip.c b/src/soc/intel/xeon_sp/gnr/chip.c index c918587..3be2d10 100644 --- a/src/soc/intel/xeon_sp/gnr/chip.c +++ b/src/soc/intel/xeon_sp/gnr/chip.c @@ -3,12 +3,14 @@ #include <arch/hpet.h> #include <arch/ioapic.h> #include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <console/debug.h> #include <cpu/x86/lapic.h> #include <device/pci.h> #include <gpio.h> #include <intelblocks/gpio.h> +#include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> @@ -18,6 +20,7 @@ #include <soc/chip_common.h> #include <soc/cpu.h> #include <soc/pch.h> +#include <soc/pcr_ids.h> #include <soc/ramstage.h> #include <soc/soc_util.h> #include <soc/util.h> @@ -89,3 +92,15 @@ { mainboard_silicon_init_params(silupd); } + +static void pirq_init(void *unused) +{ + /* to program irq pin/line for pci devices */ + pch_pirq_init(); + /* set polarity low for PIRQA to PIRQH */ + for (int i = 0; i < PIRQ_COUNT; i++) { + itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1); + } +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, pirq_init, NULL); diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c index d8160fc..d960b9e 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c @@ -109,6 +109,15 @@ acpigen_pop_len(); acpigen_pop_len(); + + /* _PRT */ + xeonsp_acpigen_write_PRT_pci_bridge(domain); + struct device *dev = NULL; + while ((dev = dev_bus_each_child(domain->downstream, dev))) { + if (!is_pci_bridge(dev)) + continue; + xeonsp_acpigen_write_PRT_pci_bridge(dev); + } } uint32_t soc_get_granted_pci_features(const struct device *domain) diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index 7ab681e..6d611db 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -26,4 +26,6 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix); void iio_domain_set_root_port_acpi_names(const struct device *domain); +void xeonsp_acpigen_write_PRT_pci_bridge(const struct device *br); + #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81569?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I98497523d11fcdd3724bc6b09585a3fe17fec2a7 Gerrit-Change-Number: 81569 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate SSDT device objects for off-SoC devices
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81568?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Generate SSDT device objects for off-SoC devices ...................................................................... soc/intel/xeon_sp: Generate SSDT device objects for off-SoC devices Off-SoC devices are devices directly connected under PCIe root ports. Create SSDT device objects for them and write _ADR and _SUN. Change-Id: Iea8dab122ed2f0f3fb34d758400488a96b6a50ce Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpigen.c M src/acpi/acpigen_pci.c M src/include/acpi/acpigen.h M src/soc/intel/xeon_sp/acpi.c 4 files changed, 70 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81568/1 diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 9c04e84..49d1722 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -2515,3 +2515,11 @@ acpigen_write_name_dword("OSFG", sleep_enable); acpigen_pop_len(); } + +void acpigen_write_SUN(uint8_t phy_slot_num) +{ + acpigen_write_method("_SUN", 0); + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte(phy_slot_num); + acpigen_pop_len(); +} diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index 427fb49..938fceb 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_type.h> +#include <device/pci_ops.h> #include <types.h> void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn) @@ -361,6 +362,40 @@ return 0; } +static bool read_physical_slot_number(const struct device *dev, uint8_t *psn) +{ + if (!is_pci(dev)) + return false; + + const size_t pos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!pos) + return false; + + u32 sltcap = pci_read_config32(dev, pos + PCI_EXP_SLTCAP); + *psn = ((sltcap >> 19) & 0x1FF); + return true; +} + +static void acpigen_write_pci_root_port_devices(const struct device *rp) +{ + uint8_t psn; + bool have_psn = read_physical_slot_number(rp, &psn); + + struct device *dev = NULL; + while ((dev = dev_bus_each_child(rp->downstream, dev))) { + if (!is_pci(dev)) + continue; + const char *name = acpi_device_name(dev); + if (!name) + continue; + acpigen_write_device(name); + acpigen_write_ADR_pci_device(dev); + if (have_psn) + acpigen_write_SUN(psn); + acpigen_pop_len(); + } +} + void acpigen_write_pci_root_ports(const struct device *domain) { struct device *dev = NULL; @@ -373,6 +408,7 @@ acpigen_write_device(name); acpigen_write_BBN(dev->downstream->secondary); acpigen_write_ADR_pci_device(dev); + acpigen_write_pci_root_port_devices(dev); acpigen_pop_len(); } } diff --git a/src/include/acpi/acpigen.h b/src/include/acpi/acpigen.h index d2e669f..e9aac1d 100644 --- a/src/include/acpi/acpigen.h +++ b/src/include/acpi/acpigen.h @@ -530,6 +530,7 @@ void acpigen_write_upc(enum acpi_upc_type type); void acpigen_write_pld(const struct acpi_pld *pld); void acpigen_write_ADR(uint64_t adr); +void acpigen_write_SUN(uint8_t phy_slot_num); struct soundwire_address; void acpigen_write_ADR_soundwire_device(const struct soundwire_address *address); void acpigen_write_create_byte_field(uint8_t op, size_t byte_offset, const char *name); diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index dcba092..9881138 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -148,21 +148,33 @@ dev->name = name; } -static struct device_operations pci_root_port_ops = { +static struct device_operations pci_dev_ops = { .acpi_name = &soc_acpi_name, }; -static void pci_root_port_set_acpi_name(struct device *dev, uint8_t id) +static void pci_dev_set_acpi_name(struct device *dev, const char *prefix, uint8_t id) { - if (!is_pci_bridge(dev)) + if (!is_pci(dev)) return; - assert(id < 8); + assert(id < 32); char *name = xmalloc(ACPI_NAME_BUFFER_SIZE); - snprintf(name, ACPI_NAME_BUFFER_SIZE, "RP%02X", id); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%02X", prefix, id); dev->name = name; - dev->ops = &pci_root_port_ops; + dev->ops = &pci_dev_ops; +} + +static void root_port_set_device_acpi_names(const struct device *rp) +{ + struct device *dev = NULL; + uint8_t id = 0; + while ((dev = dev_bus_each_child(rp->downstream, dev))) { + if (!is_pci(dev)) + continue; + pci_dev_set_acpi_name(dev, "DV", id++); + dev->ops = &pci_dev_ops; + } } void iio_domain_set_root_port_acpi_names(const struct device *domain) @@ -172,8 +184,9 @@ while ((dev = dev_bus_each_child(domain->downstream, dev))) { if (!is_pci_bridge(dev)) continue; - pci_root_port_set_acpi_name(dev, id++); - dev->ops = &pci_root_port_ops; + pci_dev_set_acpi_name(dev, "RP", id++); + dev->ops = &pci_dev_ops; + root_port_set_device_acpi_names(dev); } } @@ -185,6 +198,10 @@ if (is_pci_bridge(dev)) return dev->name; + if (is_pci_bridge(dev->upstream->dev) && is_pci(dev)) + return dev->name; + + /* FIXME: Add SoC specific device names here */ return NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/81568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea8dab122ed2f0f3fb34d758400488a96b6a50ce Gerrit-Change-Number: 81568 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Generate root port SSDT device objects
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Jincheng Li, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Tim Wawrzynczak. Hello Jincheng Li, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81567?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Generate root port SSDT device objects ...................................................................... soc/intel/xeon_sp: Generate root port SSDT device objects PCIe root port devices are Root Complex Integrated End Points (RCiEP) PCIe bridges under IIO stacks. Create SSDT device objects for them and write _ADR and _BBN. Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/gnr/soc_acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 5 files changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81567/1 diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index a23b84c..427fb49 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -360,3 +360,19 @@ */ return 0; } + +void acpigen_write_pci_root_ports(const struct device *domain) +{ + struct device *dev = NULL; + while ((dev = dev_bus_each_child(domain->downstream, dev))) { + if (!is_pci_bridge(dev)) + continue; + const char *name = acpi_device_name(dev); + if (!name) + continue; + acpigen_write_device(name); + acpigen_write_BBN(dev->downstream->secondary); + acpigen_write_ADR_pci_device(dev); + acpigen_pop_len(); + } +} diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 7a07423..5b5d473 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -27,4 +27,6 @@ uint32_t soc_get_granted_pci_features(const struct device *domain); uint32_t soc_get_granted_cxl_features(const struct device *domain); +void acpigen_write_pci_root_ports(const struct device *domain); + #endif /* ACPIGEN_PCI_H */ diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9ee8d6a..dcba092 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -148,11 +148,43 @@ dev->name = name; } +static struct device_operations pci_root_port_ops = { + .acpi_name = &soc_acpi_name, +}; + +static void pci_root_port_set_acpi_name(struct device *dev, uint8_t id) +{ + if (!is_pci_bridge(dev)) + return; + + assert(id < 8); + + char *name = xmalloc(ACPI_NAME_BUFFER_SIZE); + snprintf(name, ACPI_NAME_BUFFER_SIZE, "RP%02X", id); + dev->name = name; + dev->ops = &pci_root_port_ops; +} + +void iio_domain_set_root_port_acpi_names(const struct device *domain) +{ + struct device *dev = NULL; + uint8_t id = 0; + while ((dev = dev_bus_each_child(domain->downstream, dev))) { + if (!is_pci_bridge(dev)) + continue; + pci_root_port_set_acpi_name(dev, id++); + dev->ops = &pci_root_port_ops; + } +} + const char *soc_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) return dev->name; + if (is_pci_bridge(dev)) + return dev->name; + /* FIXME: Add SoC specific device names here */ return NULL; diff --git a/src/soc/intel/xeon_sp/gnr/soc_acpi.c b/src/soc/intel/xeon_sp/gnr/soc_acpi.c index 29bb51a..d8160fc 100644 --- a/src/soc/intel/xeon_sp/gnr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/gnr/soc_acpi.c @@ -103,6 +103,10 @@ /* _OSC */ acpigen_write_OSC_pci_domain(domain, is_cxl_domain(domain)); + /* RP0X */ + iio_domain_set_root_port_acpi_names(domain); + acpigen_write_pci_root_ports(domain); + acpigen_pop_len(); acpigen_pop_len(); } diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index e374544..7ab681e 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -24,5 +24,6 @@ unsigned long cxl_fill_srat(unsigned long current); void iio_domain_set_acpi_name(struct device *dev, const char *prefix); +void iio_domain_set_root_port_acpi_names(const struct device *domain); #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81567?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81bd5d5a2e62301543a332162a5a789e0793e18e Gerrit-Change-Number: 81567 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: device/device_util: Add is_pci_bridge
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81566?usp=email ) Change subject: device/device_util: Add is_pci_bridge ...................................................................... device/device_util: Add is_pci_bridge Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/device/device_util.c M src/include/device/device.h M src/soc/intel/xeon_sp/uncore_acpi.c 3 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/81566/1 diff --git a/src/device/device_util.c b/src/device/device_util.c index 53cd915..c9da805 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -933,3 +933,8 @@ return is_pci(pci) && pci->upstream->segment_group == 0 && pci->upstream->secondary == bus; } + +bool is_pci_bridge(const struct device *pci) +{ + return (is_pci(pci) && ((pci->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)); +} diff --git a/src/include/device/device.h b/src/include/device/device.h index 7e5ebde..c8b51fe 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -193,6 +193,7 @@ bool is_pci(const struct device *pci); bool is_enabled_pci(const struct device *pci); bool is_pci_dev_on_bus(const struct device *pci, unsigned int bus); +bool is_pci_bridge(const struct device *pci); /* Returns whether there is a hotplug port on the path to the given device. */ bool dev_path_hotplug(const struct device *); diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 90cc108..c2c5008 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -318,7 +318,7 @@ const struct device *domain = dev_get_domain(iommu); struct device *dev = NULL; while ((dev = dev_bus_each_child(domain->downstream, dev))) - if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) + if (is_pci_bridge(dev)) current += acpi_create_dmar_ds_pci_br_for_port( current, dev, pcie_seg, false, NULL); @@ -422,7 +422,7 @@ continue; for (child = dev->upstream->children; child; child = child->sibling) { - if ((child->hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) + if (!is_pci_bridge(child)) continue; current += acpi_create_dmar_ds_pci_br_for_port( -- To view, visit https://review.coreboot.org/c/coreboot/+/81566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895 Gerrit-Change-Number: 81566 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#32). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/acpi/platform.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 25 files changed, 1,322 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/32 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 32 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81349?usp=email to look at the new patch set (#14). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Remove PAM unlock operations ...................................................................... soc/intel/xeon_sp: Remove PAM unlock operations unlock_pam_regions routes Programmable Attribute Map (PAM) access to DRAM. In SPR, PAM routing to DRAM is covered by FSP. Move the step to SoC specific codes. TEST=intel/archercity CRB Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/util.c 5 files changed, 51 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/81349/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/81349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3fd1d806807449e6a4d9d4d2c8a47ce61ed53018 Gerrit-Change-Number: 81349 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024