coreboot-gerrit April 2024

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[S] Change in coreboot[main]: mb/google/nissa: Create sundance variant
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81347?usp=email ) ( 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa: Create sundance variant ...................................................................... mb/google/nissa: Create sundance variant Create the sundance variant of nissa reference board by copying the template files to a new directory named for the variant. Due to new_variant.py limitation that repo can no longer be used in inside, created this CL manually following google suggestion. BUG=b:328505938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_SUNDANCE Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81347 Reviewed-by: Derek Huang <derekhuang(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/sundance/include/variant/ec.h A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt A src/mainboard/google/brya/variants/sundance/overridetree.cb 8 files changed, 47 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Shou-Chieh Hsu: Looks good to me, but someone else must approve Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 992be88..160d12a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -382,6 +382,9 @@ select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT +config BOARD_GOOGLE_SUNDANCE + select BOARD_GOOGLE_BASEBOARD_NISSA + config BOARD_GOOGLE_QUANDISO select BOARD_GOOGLE_BASEBOARD_NISSA select CHROMEOS_WIFI_SAR if CHROMEOS @@ -713,6 +716,7 @@ default "Bujia" if BOARD_GOOGLE_BUJIA default "Tivviks" if BOARD_GOOGLE_TIVVIKS default "Yavista" if BOARD_GOOGLE_YAVISTA + default "Sundance" if BOARD_GOOGLE_SUNDANCE config VARIANT_DIR default "brya0" if BOARD_GOOGLE_BRYA0 @@ -772,6 +776,7 @@ default "bujia" if BOARD_GOOGLE_BUJIA default "nivviks" if BOARD_GOOGLE_TIVVIKS default "yavista" if BOARD_GOOGLE_YAVISTA + default "sundance" if BOARD_GOOGLE_SUNDANCE config VBOOT select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 6cedaac..a8d111a 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -172,3 +172,6 @@ config BOARD_GOOGLE_YAVISTA bool "-> Yavista" + +config BOARD_GOOGLE_SUNDANCE + bool "-> Sundance" diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/ec.h b/src/mainboard/google/brya/variants/sundance/include/variant/ec.h new file mode 100644 index 0000000..7a2a6ff --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __VARIANT_EC_H__ +#define __VARIANT_EC_H__ + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h new file mode 100644 index 0000000..c4fe342 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk new file mode 100644 index 0000000..eace2e4 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt new file mode 100644 index 0000000..fa24790 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt new file mode 100644 index 0000000..2499005 --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt @@ -0,0 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Generated IDs are dependent on the order of parts in this file, +# so new parts must always be added at the end of the file! +# +# Generate an updated Makefile.mk and dram_id.generated.txt by running the +# part_id_gen tool from util/spd_tools. +# See util/spd_tools/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb new file mode 100644 index 0000000..4f2c04a --- /dev/null +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -0,0 +1,6 @@ +chip soc/intel/alderlake + + device domain 0 on + end + +end -- To view, visit https://review.coreboot.org/c/coreboot/+/81347?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea Gerrit-Change-Number: 81347 Gerrit-PatchSet: 14 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/ppc64: Add arch as supported by the clang compiler
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78448?usp=email ) Change subject: arch/ppc64: Add arch as supported by the clang compiler ...................................................................... arch/ppc64: Add arch as supported by the clang compiler Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e Reviewed-on: https://review.coreboot.org/c/coreboot/+/78448 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/arch/ppc64/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/ppc64/Kconfig b/src/arch/ppc64/Kconfig index 25a0f50..93e4929 100644 --- a/src/arch/ppc64/Kconfig +++ b/src/arch/ppc64/Kconfig @@ -2,6 +2,7 @@ config ARCH_PPC64 bool + select ARCH_SUPPORTS_CLANG config ARCH_BOOTBLOCK_PPC64 bool -- To view, visit https://review.coreboot.org/c/coreboot/+/78448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1aacff869663e1db74cd485787d7103b9ec5602e Gerrit-Change-Number: 78448 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/ppc64: Fix inline assembly for clang
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78446?usp=email ) Change subject: arch/ppc64: Fix inline assembly for clang ...................................................................... arch/ppc64: Fix inline assembly for clang Use macros from the Linux kernel 6.5 to make the inline assembly also compile on clang. TEST: See that the generated code is identical on GCC and compiles on clang. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78446 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/arch/ppc64/stages.c 1 file changed, 6 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/arch/ppc64/stages.c b/src/arch/ppc64/stages.c index 01b9efa..c6d35ed 100644 --- a/src/arch/ppc64/stages.c +++ b/src/arch/ppc64/stages.c @@ -25,10 +25,15 @@ _cbmem_top_ptr = stage_arg; #if ENV_RAMSTAGE +#define __stringify_in_c(...) #__VA_ARGS__ +#define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " " +#define PPC_RAW_SLBIA(IH) (0x7c0003e4 | (((IH) & 0x7) << 21)) +#define PPC_SLBIA(IH) stringify_in_c(.long PPC_RAW_SLBIA(IH)) + hrmor = read_spr(SPR_HRMOR); asm volatile("sync; isync" ::: "memory"); write_spr(SPR_HRMOR, 0); - asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory"); + asm volatile("or 1,1,%0;" PPC_SLBIA(7)"; sync; isync" :: "r"(hrmor) : "memory"); #endif main(); -- To view, visit https://review.coreboot.org/c/coreboot/+/78446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55 Gerrit-Change-Number: 78446 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: arch/ppc64: Fix inline assembly for clang
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Julius Werner, ron minnich. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78446?usp=email ) Change subject: arch/ppc64: Fix inline assembly for clang ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I516033c69e62dfdb38f83285c156d5527917ad55 Gerrit-Change-Number: 78446 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:16:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Kconfig: Make GBD_STUB and long mode mutually exclusive
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Jérémy Compostella, Nico Huber. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81379?usp=email ) Change subject: Kconfig: Make GBD_STUB and long mode mutually exclusive ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81379?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icaf7d0763829d5badf73d38bb8fc3d36cfe18964 Gerrit-Change-Number: 81379 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:13:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add soc_add_stack_mmios
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81570?usp=email ) Change subject: soc/intel/xeon_sp: Add soc_add_stack_mmios ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: SPR MTRR before: [0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m [0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200000000000 - 0x00002064ffffffff size 0x6500000000 type 0[0m [0m[DEBUG] 0x0000206a00000000 - 0x00002074ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000207a00000000 - 0x00002084ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000208a00000000 - 0x00002094ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000209a00000000 - 0x00002104ffffffff size 0x6b00000000 type 0[0m [0m[DEBUG] 0x0000210a00000000 - 0x00002114ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000211a00000000 - 0x00002124ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000212a00000000 - 0x00002134ffffffff size 0xb00000000 type 0[0m [0m[DEBUG] 0x0000213a00000000 - 0x0000213fffffffff size 0x600000000 type 0[0m [0m[DEBUG] MTRR: default type WB/UC MTRR counts: 37/7.[0m [0m[DEBUG] MTRR: UC selected as default type.[0m [0m[DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x000fffff80000000 type 6[0m [0m[DEBUG] MTRR: 1 base 0x0000000100000000 mask 0x000fffff00000000 type 6[0m [0m[DEBUG] MTRR: 2 base 0x0000000200000000 mask 0x000ffffe00000000 type 6[0m [0m[DEBUG] MTRR: 3 base 0x0000000400000000 mask 0x000ffffc00000000 type 6[0m [0m[DEBUG] MTRR: 4 base 0x0000000800000000 mask 0x000ffff800000000 type 6[0m [0m[DEBUG] MTRR: 5 base 0x0000001000000000 mask 0x000ffff000000000 type 6[0m [0m[DEBUG] MTRR: 6 base 0x0000002000000000 mask 0x000fffff80000000 type 6[0m SPR MTRR after: [0m[DEBUG] MTRR: Physical address space:[0m [0m[DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6[0m [0m[DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0[0m [0m[DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6[0m [0m[DEBUG] 0x0000000080000000 - 0x00000000ffffffff size 0x80000000 type 0[0m [0m[DEBUG] 0x0000000100000000 - 0x000000207fffffff size 0x1f80000000 type 6[0m [0m[DEBUG] 0x0000200000000000 - 0x0000213fffffffff size 0x14000000000 type 0[0m [0m[DEBUG] MTRR: default type WB/UC MTRR counts: 3/7.[0m [0m[DEBUG] MTRR: WB selected as default type.[0m [0m[DEBUG] MTRR: 0 base 0x0000000080000000 mask 0x000fffff80000000 type 0[0m [0m[DEBUG] MTRR: 1 base 0x0000200000000000 mask 0x000fff0000000000 type 0[0m [0m[DEBUG] MTRR: 2 base 0x0000210000000000 mask 0x000fffc000000000 type 0[0m -- To view, visit https://review.coreboot.org/c/coreboot/+/81570?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib2a8063d8bee8fb4b5578e84ba8f9951815ffbf3 Gerrit-Change-Number: 81570 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/corsola: Add new board variant 'Kyogre'
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81218?usp=email ) Change subject: mb/google/corsola: Add new board variant 'Kyogre' ...................................................................... mb/google/corsola: Add new board variant 'Kyogre' Add a new Kingler follower device 'Kyogre' BUG=b:318614302 TEST=emerge-corsola coreboot Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Signed-off-by: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81218 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/corsola/Kconfig M src/mainboard/google/corsola/Kconfig.name 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Varshit Pandya: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/corsola/Kconfig b/src/mainboard/google/corsola/Kconfig index fe6e6d6..96d5f12 100644 --- a/src/mainboard/google/corsola/Kconfig +++ b/src/mainboard/google/corsola/Kconfig @@ -7,6 +7,7 @@ config BOARD_GOOGLE_KINGLER_COMMON def_bool BOARD_GOOGLE_KINGLER || \ + BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB @@ -51,6 +52,7 @@ select HAVE_LINEAR_FRAMEBUFFER select DRIVER_ANALOGIX_ANX7625 if BOARD_GOOGLE_CHINCHOU || \ BOARD_GOOGLE_KINGLER || \ + BOARD_GOOGLE_KYOGRE || \ BOARD_GOOGLE_PONYTA || \ BOARD_GOOGLE_STEELIX || \ BOARD_GOOGLE_VOLTORB @@ -74,6 +76,7 @@ string default "Kingler" if BOARD_GOOGLE_KINGLER default "Krabby" if BOARD_GOOGLE_KRABBY + default "Kyogre" if BOARD_GOOGLE_KYOGRE default "Steelix" if BOARD_GOOGLE_STEELIX default "Tentacruel" if BOARD_GOOGLE_TENTACRUEL default "Magikarp" if BOARD_GOOGLE_MAGIKARP diff --git a/src/mainboard/google/corsola/Kconfig.name b/src/mainboard/google/corsola/Kconfig.name index 4894165..17fc65d 100644 --- a/src/mainboard/google/corsola/Kconfig.name +++ b/src/mainboard/google/corsola/Kconfig.name @@ -5,6 +5,9 @@ config BOARD_GOOGLE_KINGLER bool "-> Kingler" +config BOARD_GOOGLE_KYOGRE + bool "-> Kyogre" + config BOARD_GOOGLE_STEELIX bool "-> Steelix" -- To view, visit https://review.coreboot.org/c/coreboot/+/81218?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae3857a9f8edadcc2eee3500fda2e76c0334221c Gerrit-Change-Number: 81218 Gerrit-PatchSet: 11 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kenny Pan <kennypan(a)google.com> Gerrit-CC: Knox Chiou <knoxchiou(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Martin L Roth (Code Review) 01 Apr '24

01 Apr '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... soc/intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL The RPL FSP currently uses HECI commands to retrieve the chipset initialization version because the MBP HOB creation is disabled (SkipMbpHob=1). This has resulted in an approximate 150ms increase in boot time. Investigations are ongoing to determine the cause of the delay when using HECI commands. As an interim solution, this patch sets SkipMbpHob=0, enabling the use of MBP HOB or acquiring the chipset initialization version, which is expected to reduce the boot time. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With this patch: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) Without this patch: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81446 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Reviewed-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 3 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Varshit Pandya: Looks good to me, but someone else must approve Ronak Kanabar: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 01d5f89..5086069 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -517,7 +517,7 @@ config FSP_PUBLISH_MBP_HOB bool - default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) + default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) default y help This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. @@ -526,8 +526,7 @@ Note: It cannot be disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the - later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based - platforms. + later platforms so creation of MBP HOB can be skipped for ADL-N based platforms. config INCLUDE_HSPHY_IN_FMAP bool "Include PCIe 5.0 HSPHY firmware in flash" -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 8 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Remove PAM unlock operations
by Shuo Liu (Code Review) 01 Apr '24

01 Apr '24

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[S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Ashish Kumar Mishra (Code Review) 01 Apr '24

01 Apr '24

Attention is currently required from: Deepti Deshatty, Eric Lai, Shelley Chen, Varshit Pandya, Vijay P Hiremath. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 4: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81207/comment/c668d2b2_208d4312 : PS1, Line 9: For PMC-PD communication we need to enable 3 pins. > this information for SoC (about native function) is captured in it's datasheet (EDS in your case), t […] Done File src/mainboard/google/brox/variants/baseboard/brox/gpio.c: https://review.coreboot.org/c/coreboot/+/81207/comment/09d572dc_e249ca07 : PS2, Line 105: NC > should remove NC? Acknowledged https://review.coreboot.org/c/coreboot/+/81207/comment/7690ae66_a36abb31 : PS2, Line 137: NC > same Acknowledged https://review.coreboot.org/c/coreboot/+/81207/comment/141141cf_03b89c70 : PS2, Line 139: NC > same Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Mon, 01 Apr 2024 04:01:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit Pandya <pandyavarshit(a)gmail.com> Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-MessageType: comment

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