[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Martin L Roth, Nick Vaccaro, Paul Menzel, SH Kim, Subrata Banik, Sumeet R Pawnikar. Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Sumeet R Pawnikar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81436?usp=email to look at the new patch set (#11). Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... mb/google/{brya,hades}: use soc index for variant_update_power_limits() The power_limits_config variable for ADL/RPL is array data, but we got soc_power_limits_config variable without its index. So correct the code to get the proper pointer of the data for current CPU SKU. I tried to override the PL4 value to 80W from 114W with following table in ramstage.c as a test for bug b/328729536. ``` const struct cpu_power_limits limits[] = { {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, } ``` And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool. - Before this patch: msr_pl4 was not changed, it's always 114 - After this patch: msr_pl4 was changed to 80 BUG=None BRANCH=None TEST=Built and tested the function could adjust PL4 on xol in local. Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c 2 files changed, 68 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81436/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 11 Gerrit-Owner: SH Kim <sh_.kim@samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot@google.com> Gerrit-Reviewer: Eric Lai <ericllai@google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal@google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro@chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik@google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-CC: Martin L Roth <gaumless@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit@gmail.com> Gerrit-Attention: Martin L Roth <gaumless@gmail.com> Gerrit-Attention: Subrata Banik <subratabanik@google.com> Gerrit-Attention: SH Kim <sh_.kim@samsung.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter@mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal@google.com> Gerrit-Attention: Dinesh Gehlot <digehlot@google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro@chromium.org> Gerrit-MessageType: newpatchset
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SH Kim (Code Review)