coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: [DO NOT MERGE] block pmc ipc communication
by Deepti Deshatty (Code Review) 04 Apr '24

04 Apr '24

Deepti Deshatty has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81667?usp=email ) Change subject: [DO NOT MERGE] block pmc ipc communication ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia96926feda611157b32aca56b8c711531f3db231 Gerrit-Change-Number: 81667 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: [DO NOT MERGE] block pmc ipc communication
by Deepti Deshatty (Code Review) 04 Apr '24

04 Apr '24

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81667?usp=email ) Change subject: [DO NOT MERGE] block pmc ipc communication ...................................................................... [DO NOT MERGE] block pmc ipc communication Change-Id: Ia96926feda611157b32aca56b8c711531f3db231 --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81667/1 diff --git a/src/soc/intel/common/block/tcss/tcss.c b/src/soc/intel/common/block/tcss/tcss.c index 1c4b9b3..e4b7a22 100644 --- a/src/soc/intel/common/block/tcss/tcss.c +++ b/src/soc/intel/common/block/tcss/tcss.c @@ -69,6 +69,7 @@ static int send_pmc_req(int cmd_type, const struct pmc_ipc_buffer *req, struct pmc_ipc_buffer *res, uint32_t size) { +#if 0 uint32_t cmd_reg; uint32_t res_reg; int tries = 2; @@ -113,6 +114,9 @@ printk(BIOS_ERR, "pmc_send_ipc_cmd failed after retries\n"); return -1; +#endif + printk(BIOS_ERR, "** bypass sending pmc_send_ipc_cmd \n"); + return 0; } static int send_pmc_disconnect_request(int port, const struct tcss_port_map *port_map) -- To view, visit https://review.coreboot.org/c/coreboot/+/81667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia96926feda611157b32aca56b8c711531f3db231 Gerrit-Change-Number: 81667 Gerrit-PatchSet: 1 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use official microcodes
by Paul Menzel (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81637?usp=email ) Change subject: soc/intel/xeon_sp/spr: Use official microcodes ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Gerrit-Change-Number: 81637 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 10:19:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/genoa_poc: Fix DEBUG_SMI compilation error
by Paul Menzel (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81072?usp=email ) Change subject: soc/amd/genoa_poc: Fix DEBUG_SMI compilation error ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81072/comment/c911eb96_c1796781 : PS1, Line 7: Fix DEBUG_SMI compilation error > Something like this? […] Yes. Thank you. -- To view, visit https://review.coreboot.org/c/coreboot/+/81072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7c6f2346d5f9ffb371d51d1de6f0b695acedf10 Gerrit-Change-Number: 81072 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 04 Apr 2024 10:19:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/anraggar: Delay to deassert RST pin for TCHSCR
by Paul Menzel (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, Varshit Pandya, Weimin Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81636?usp=email ) Change subject: mb/google/nissa/var/anraggar: Delay to deassert RST pin for TCHSCR ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81636/comment/cddd0ad6_e9c1a83e : PS3, Line 7: Delay to deassert RST pin for TCHSCR Please use a verb in imperative mood. Either > Add delay to … or > Delay deassert RST pin for TCHSCR https://review.coreboot.org/c/coreboot/+/81636/comment/2a54c18f_69d124e7 : PS3, Line 9: Change to pull up “Change to” is redundant in the commit message: Pull up GPP_C1 (RST pin of touchscreen) in override GPIO table instead of early GPIO table to make … -- To view, visit https://review.coreboot.org/c/coreboot/+/81636?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4bd17ecf8ffbe6ca8791fa1bc4577f4dfb4ea8e8 Gerrit-Change-Number: 81636 Gerrit-PatchSet: 3 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 10:19:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0:Make coreboot FSP stack 16-bytes aligned
by Paul Menzel (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Ronak Kanabar, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0:Make coreboot FSP stack 16-bytes aligned ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81661/comment/c4fca8ba_23e3110f : PS2, Line 7: drivers/intel/fsp2_0:Make Please add a space after the alignment. https://review.coreboot.org/c/coreboot/+/81661/comment/db2f484d_4b3f6958 : PS2, Line 9: - Stack alignment: Making this an item seems unnecessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 10:06:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0:Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar, Subrata Banik. Hello Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81661?usp=email to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0:Make coreboot FSP stack 16-bytes aligned ...................................................................... drivers/intel/fsp2_0:Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned. This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). 2. The FSP stack buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned. Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 2 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Nico Huber (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Cliff Huang, Felix Held, Johnny Lin, Jonathan Zhang, Lance Zhao, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81652?usp=email ) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: > since the acpi code seems to be part of the acpi spec Which is violated by the current implementation for the PCIe bits when called with the CXL UUID. Haven't found much about it, but Linux seems to always call with this UUID if it's a CXL root. I couldn't figure out if it would still consider the PCIe bits then, but they are there and this implementation seems not even Linux compatible. And that's on top of the odd design, unnecessary repetition in the generated code (per root), and unnecessary repetition at runtime for this. IMO, we should first discuss the generated code, then how it is generated (or if it should be generated at all?). I'm rather picky about it because new code patterns seem to have the habit to spread. Upstream, code should be discussed, reviewed and set a good example, especially in common code areas. I suggested to move it back because people seemed to be too much in a hurry for a proper process atm. -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 09:19:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81419?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: [for test] upgrade crossgcc ...................................................................... [for test] upgrade crossgcc Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/acpica-R06_28_23_iasl.patch R util/crossgcc/patches/gcc-14-20240331_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-14-20240331_gnat.patch R util/crossgcc/patches/gcc-14-20240331_libcpp.patch R util/crossgcc/patches/gcc-14-20240331_libgcc.patch R util/crossgcc/patches/gcc-14-20240331_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-14-20240331_rv32iafc.patch A util/crossgcc/sum/G20240322.tar.gz.cksum D util/crossgcc/sum/R06_28_23.tar.gz.cksum D util/crossgcc/sum/clang-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/cmake-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.28.3.tar.gz.cksum A util/crossgcc/sum/cmake-3.29.1.tar.gz.cksum D util/crossgcc/sum/compiler-rt-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/gcc-13.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-14-20240331.tar.xz.cksum D util/crossgcc/sum/libunwind-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/libunwind-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/lld-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/lld-18.1.3.src.tar.xz.cksum D util/crossgcc/sum/llvm-17.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-18.1.3.src.tar.xz.cksum A util/crossgcc/sum/runtimes-18.1.3.src.tar.xz.cksum 29 files changed, 52 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81419/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: [test only] upgrade to gcc-14-20240303
by Elyes Haouas (Code Review) 04 Apr '24

04 Apr '24

Elyes Haouas has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80607?usp=email ) Change subject: [test only] upgrade to gcc-14-20240303 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/80607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib96709309e7c71b76a51d3b8600be793312d6a8f Gerrit-Change-Number: 80607 Gerrit-PatchSet: 9 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: abandon

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coreboot-gerrit April 2024