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Change subject: util/crossgcc: Update ACPICA from 20230628 to 20240321
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Blocking until 24.05 release
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Change subject: mb/google/brya: Add new baseboard trulo
......................................................................
Patch Set 10:
(4 comments)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81626/comment/686af233_b59a3ef1 :
PS10, Line 656: chromeos-nissa-16MiB-debugfsp.fmd
chromeos-16MiB-debugfsp.fmd
https://review.coreboot.org/c/coreboot/+/81626/comment/7b3f2ff6_04f151db :
PS10, Line 657: chromeos-nissa-16MiB
chromeos-16MiB.fmd
https://review.coreboot.org/c/coreboot/+/81626/comment/0612e8bb_5c7851b4 :
PS10, Line 658: default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa-32MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_NISSA && BOARD_ROMSIZE_KB_32768
we can drop this
https://review.coreboot.org/c/coreboot/+/81626/comment/4139d1a4_8f0e5e73 :
PS10, Line 659: default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-trulo-16MiB-debugfsp.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_TRULO && BOARD_ROMSIZE_KB_16384 && BUILDING_WITH_DEBUG_FSP
: default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-trulo-16MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_TRULO && BOARD_ROMSIZE_KB_16384
: default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-trulo-32MiB.fmd" if CHROMEOS && BOARD_GOOGLE_BASEBOARD_TRULO && BOARD_ROMSIZE_KB_32768
do we really need yet another layout ? can't we use the same nissa layout. we can always drop `nissa` keyword from the file name
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Change subject: drivers/smmstore/ramstage.c: retry smmstore init up 5 times
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Patch Set 2:
(1 comment)
Patchset:
PS2:
Alternative approach: https://review.coreboot.org/c/coreboot/+/79738
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
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Patch Set 1:
(1 comment)
Patchset:
PS1:
will this also be used for AMD or arm server in the future? this is not Intel specific right?
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
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Patch Set 1: Code-Review+2
(1 comment)
Patchset:
PS1:
> > since the acpi code seems to be part of the acpi spec […]
good point
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/xeon_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/81628/comment/f2f02181_b79d40e7 :
PS3, Line 93: #if CONFIG(XEON_SP_HAVE_IIO_IOAPIC)
i'd say that moving the code inside the #if block into a separate c file and conditionally add that to the build that depending on CONFIG_XEON_SP_HAVE_IIO_IOAPIC would be a bit cleaner solution
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Change subject: drivers/smmstore/ramstage.c: retry smmstore init up 5 times
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Patch Set 2:
(1 comment)
File src/drivers/smmstore/ramstage.c:
https://review.coreboot.org/c/coreboot/+/73981/comment/6b7a4395_df146c50 :
PS1, Line 79: } while (retry--);
> Thank you. […]
Done
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Change subject: drivers/smmstore/ramstage.c: retry smmstore init up 5 times
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/smmstore/ramstage.c:
https://review.coreboot.org/c/coreboot/+/73981/comment/0613301e_40a01dfa :
PS1, Line 79: } while (retry--);
> @Paul I added info on how many retries were done to the error message.
Thank you. Please feel free to mark comments as resolved yourself, once you think you addressed them.
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