coreboot-gerrit April 2024

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[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Maciej Pijanowski (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Alexander Couzens, Michał Kopeć, Paul Menzel. Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ...................................................................... Patch Set 7: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/80609/comment/b3163619_a0c1f4bb : PS6, Line 9: It may come with 8th or 9th Gen CPUs. : i5-8500T has been tested here. > Please do not break lines just because a sentence ends. Ok, changed File src/mainboard/lenovo/m920q/romstage.c: https://review.coreboot.org/c/coreboot/+/80609/comment/4c60dc79_4629d51f : PS6, Line 13: .spd[0] = { > Platform only has 2 DIMMs Correct, updated. This was mostly copied over from the reference board code, I think. https://review.coreboot.org/c/coreboot/+/80609/comment/a04cfd01_bb7097e3 : PS6, Line 33: /* Rcomp target values for CFL-S, DDR4 and 2 DIMMs per channel */ > There's 1 DIMM per channel here Updated the comment. Do you suggest to change the values as well? I have looked into the Rcomp Info tool from Intel, and for CFL-S there is only entry for 2DPC. -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Thu, 04 Apr 2024 20:13:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Cannon Lake)
by Maciej Pijanowski (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Alexander Couzens, Maciej Pijanowski, Paul Menzel. Hello Alexander Couzens, Michał Kopeć, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80609?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/lenovo: Add ThinkCentre M920q (Cannon Lake) ...................................................................... mb/lenovo: Add ThinkCentre M920q (Cannon Lake) It may come with 8th or 9th Gen CPUs. i5-8500T has been tested here. Works: - Serial adapter from daughter board (COM1 connector) - USB ports front and back - USB-C port (charging, data) - HDMI (in Linux and SeaBIOS) - Ethernet - SATA - NVMe - internal speaker - TPM2.0 Does not work: - front audio jacks - HDMI (in edk2) Not tested: - PCIe x8 port - Display Port - WiFi slot Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> --- A src/mainboard/lenovo/m920q/Kconfig A src/mainboard/lenovo/m920q/Kconfig.name A src/mainboard/lenovo/m920q/Makefile.inc A src/mainboard/lenovo/m920q/acpi/ec.asl A src/mainboard/lenovo/m920q/acpi/mainboard.asl A src/mainboard/lenovo/m920q/acpi/superio.asl A src/mainboard/lenovo/m920q/board_info.txt A src/mainboard/lenovo/m920q/bootblock.c A src/mainboard/lenovo/m920q/cmos.default A src/mainboard/lenovo/m920q/cmos.layout A src/mainboard/lenovo/m920q/data.vbt A src/mainboard/lenovo/m920q/devicetree.cb A src/mainboard/lenovo/m920q/dsdt.asl A src/mainboard/lenovo/m920q/gma-mainboard.ads A src/mainboard/lenovo/m920q/gpio.c A src/mainboard/lenovo/m920q/hda_verb.c A src/mainboard/lenovo/m920q/include/mainboard/gpio.h A src/mainboard/lenovo/m920q/ramstage.c A src/mainboard/lenovo/m920q/romstage.c 19 files changed, 1,382 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/80609/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 7 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/common/block/fast_spi: probe for 2nd flash component
by Maciej Pijanowski (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Michał Żygowski, Nico Huber, Paul Menzel. Maciej Pijanowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80608?usp=email ) Change subject: soc/intel/common/block/fast_spi: probe for 2nd flash component ...................................................................... Patch Set 5: (3 comments) Patchset: PS4: > Code change looks ok. But I don't know why the code uses SFDP in general... Thanks for the review, please let me know if you expect some action from me here. File src/soc/intel/common/block/fast_spi/fast_spi_def.h: https://review.coreboot.org/c/coreboot/+/80608/comment/3fdae2d0_73ac260a : PS4, Line 156: #define SPIBAR_PTINX_IDX_MASK 0xffc > Why drop it? Because it is not used anymore. The function used to be limited to reading SPDF parameter. Now the function is more generic, allowing for other actions, depending on the HORD bits. This mask was too limiting, allowing for bits 11:2 only to be set. Instead, we construct the PTINX register value using the existing (and a few new) defines. We do not want PTINX index only (bits 11:2), we need the whole (15:2) to cover the rest of the fields. Do you suggest we should define a mask covering this and use it inside a function? It should be then renamed accordingly to reflect that. File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/80608/comment/b8f76b5b_29e684ab : PS4, Line 308: * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. > This seems a little odd, the code was added in 2017. SPI guides up to […] I cannot possibly comment on this code as a whole, I just needed to get rid of the error and support a scenario with two flashes. Please let me know if you expect some action from me here. -- To view, visit https://review.coreboot.org/c/coreboot/+/80608?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d7449f9e1470dc234fe5ba5217d3ce4c142b49c Gerrit-Change-Number: 80608 Gerrit-PatchSet: 5 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 04 Apr 2024 19:54:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: cpu/x86: Link page tables in stage if possible
by Appukuttan V K (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Arthur Heymans. Appukuttan V K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80337?usp=email ) Change subject: cpu/x86: Link page tables in stage if possible ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: Hi Arthur, We are observing section overlap error when building coreboot in x64 (meteorlake rex) with this patch. Can you please help to resolve this ? Build logs with error given below: make[1]: Circular set_fit_ptr <- add_mcu_fit dependency dropped. make[1]: Circular check-fmap-16mib-crossing <- add_mcu_fit dependency dropped. LINK cbfs/fallback/bootblock.debug HOSTCC cbfstool/cbfstool (link) CC ramstage/cpu/x86/mp_init.o Chromium OS 18.0_pre510928 clang version 18.0.0 (/mnt/host/source/src/third_party/llvm-project 82e851a407c52d65ce65e7aa58453127e67d42a0) Target: x86_64-pc-linux-gnu Thread model: posix InstalledDir: /usr/bin Selected GCC installation: /usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0 Candidate multilib: .;@m64 Candidate multilib: 32;@m32 Selected multilib: .;@m64 "/usr/bin/x86_64-pc-linux-gnu-ld.lld" -pie --hash-style=gnu --build-id --eh-frame-hdr -m elf_x86_64 -dynamic-linker /lib64/ld-linux-x86-64.so.2 -o /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/util/cbfstool/cbfstool /usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0/../../../../lib64/Scrt1.o /usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0/../../../../lib64/crti.o /usr/lib64/clang/18/lib/linux/clang_rt.crtbegin-x86_64.o -L/usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0 -L/usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0/../../../../lib64 -L/lib/../lib64 -L/usr/lib/../lib64 -L/usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0/../../../../x86_64-pc-linux-gnu/lib -L/lib -L/usr/lib / /usr/lib64/clang/18/lib/linux/libclang_rt.builtins-x86_64.a --as-needed -lgcc_s --no-as-needed /usr/lib64/clang/18/lib/linux/clang_rt.crtend-x86_64.o /usr/lib/gcc/x86_64-pc-linux-gnu/10.2.0/../../../../lib64/crtn.o x86_64-elf-ld.bfd: section .init LMA [00000000fffffb50,00000000ffffff37] overlaps section .text LMA [00000000ffff1bc0,0000000100000517] x86_64-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug: section .init lma 0xfffffb50 adjusted to 0x100000518 x86_64-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug: section .id lma 0xffffff47 adjusted to 0x100000900 x86_64-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug: section .fit_pointer lma 0xffffffc0 adjusted to 0x100000939 x86_64-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug: section .reset lma 0xfffffff0 adjusted to 0x100000941 x86_64-elf-ld.bfd: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug: section .header_pointer lma 0xfffffffc adjusted to 0x10000094d OBJCOPY cbfs/fallback/romstage.elf OBJCOPY ramstage/cpu/x86/smm/smmstub.manual /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/bootblock/soc/intel/common/block/cpu/car/cache_as_ram.o: in function `copy_data_section': /build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999/src/cpu/x86/copy_data_section.inc:24:(.init+0x1d5): relocation truncated to fit: R_X86_64_32 against symbol `_data_load' defined in .text section in /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug make[1]: *** [src/arch/x86/Makefile.mk:101: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/cbfs/fallback/bootblock.debug] Error 1 make[1]: *** Waiting for unfinished jobs.... make[1]: Leaving directory '/build/rex/tmp/portage/sys-boot/coreboot-9999/work/coreboot-9999' make: *** [/build/rex/tmp/portage/sys-boot/coreboot-9999/files/coreboot.make:28: /build/rex/tmp/portage/sys-boot/coreboot-9999/work/build/rex0-serial/coreboot.rom] Error 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied54b66b930187cba5fbc578a81ed5859a616562 Gerrit-Change-Number: 80337 Gerrit-PatchSet: 22 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 04 Apr 2024 17:53:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: vc/intel/fsp/mtl: Adding THC UPD in Partial Header
by Name of user not set (Code Review) 04 Apr '24

04 Apr '24

srinivas.kulkarni(a)intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81674?usp=email ) Change subject: vc/intel/fsp/mtl: Adding THC UPD in Partial Header ...................................................................... vc/intel/fsp/mtl: Adding THC UPD in Partial Header Update header files for FSP for Meteor Lake platform to include THC UPD's. FSPS: 1. Added UPD's ThcMode, ThcWakeOnTouch 2. Reserved bit changes BUG=b:332882101 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I9a18b83fbb2d7760bd58027a4203919489b01580 Signed-off-by: Srinivas Kulkarni <srinivas.kulkarni(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h 1 file changed, 51 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/81674/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h index 637bc37..e5c5847 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2023, Intel Corporation. All rights reserved. +Copyright (c) 2024, Intel Corporation. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -1580,7 +1580,22 @@ /** Offset 0x08F2 - Reserved **/ - UINT8 Reserved39[122]; + UINT8 Reserved39[8]; + +/** Offset 0x08FA - Touch Host Controller Mode + Switch between Intel THC protocol and Industry standard HID Over SPI protocol. 0x0:Thc, 0x1:Hid +**/ + UINT8 ThcMode[2]; + +/** Offset 0x08FC - Touch Host Controller Wake On Touch + Based on this setting vGPIO for given THC will be in native mode, and additional + _CRS for wake will be exposed in ACPI +**/ + UINT8 ThcWakeOnTouch[2]; + +/** Offset 0x08FE - Reserved +**/ + UINT8 Reserved40[110]; /** Offset 0x096C - PCIE RP Pcie Speed Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: @@ -1628,7 +1643,7 @@ /** Offset 0x0A54 - Reserved **/ - UINT8 Reserved40[3767]; + UINT8 Reserved41[3767]; /** Offset 0x190B - PCIE RP Enable Peer Memory Write This member describes whether Peer Memory Writes are enabled on the platform. @@ -1651,7 +1666,7 @@ /** Offset 0x1919 - Reserved **/ - UINT8 Reserved41; + UINT8 Reserved42; /** Offset 0x191A - PCH Pm PME_B0_S5_DIS When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. @@ -1684,7 +1699,7 @@ /** Offset 0x191F - Reserved **/ - UINT8 Reserved42[4]; + UINT8 Reserved43[4]; /** Offset 0x1923 - PCH Pm Slp S3 Min Assert SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. @@ -1820,7 +1835,7 @@ /** Offset 0x196C - Reserved **/ - UINT8 Reserved43[2]; + UINT8 Reserved44[2]; /** Offset 0x196E - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. @@ -1862,7 +1877,7 @@ /** Offset 0x1992 - Reserved **/ - UINT8 Reserved44[2]; + UINT8 Reserved45[2]; /** Offset 0x1994 - IEH Mode Integrated Error Handler Mode, 0: Bypass, 1: Enable @@ -1872,7 +1887,7 @@ /** Offset 0x1995 - Reserved **/ - UINT8 Reserved45[11]; + UINT8 Reserved46[11]; /** Offset 0x19A0 - PCH Thermal Throttling Custimized T0Level Value Custimized T0Level value. @@ -1910,7 +1925,7 @@ /** Offset 0x19A9 - Reserved **/ - UINT8 Reserved46[9]; + UINT8 Reserved47[9]; /** Offset 0x19B2 - DMI Thermal Sensor Autonomous Width Enable DMI Thermal Sensor Autonomous Width Enable. @@ -2018,7 +2033,7 @@ /** Offset 0x19C5 - Reserved **/ - UINT8 Reserved47; + UINT8 Reserved48; /** Offset 0x19C6 - Thermal Device Temperature Decides the temperature. @@ -2043,7 +2058,7 @@ /** Offset 0x19E3 - Reserved **/ - UINT8 Reserved48; + UINT8 Reserved49; /** Offset 0x19E4 - xHCI High Idle Time LTR override Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting @@ -2086,7 +2101,7 @@ /** Offset 0x19F3 - Reserved **/ - UINT8 Reserved49[5]; + UINT8 Reserved50[5]; /** Offset 0x19F8 - BgpdtHash[4] BgpdtHash values @@ -2100,7 +2115,7 @@ /** Offset 0x1A1C - Reserved **/ - UINT8 Reserved50[4]; + UINT8 Reserved51[4]; /** Offset 0x1A20 - BiosGuardModulePtr BiosGuardModulePtr default values @@ -2126,7 +2141,7 @@ /** Offset 0x1A32 - Reserved **/ - UINT8 Reserved51[22]; + UINT8 Reserved52[22]; /** Offset 0x1A48 - Skip Ssid Programming. When set to TRUE, silicon code will not do any SSID programming and platform code @@ -2137,7 +2152,7 @@ /** Offset 0x1A49 - Reserved **/ - UINT8 Reserved52; + UINT8 Reserved53; /** Offset 0x1A4A - Change Default SVID Change the default SVID used in FSP to programming internal devices. This is only @@ -2153,7 +2168,7 @@ /** Offset 0x1A4E - Reserved **/ - UINT8 Reserved53[2]; + UINT8 Reserved54[2]; /** Offset 0x1A50 - SVID SDID table Poniter. The address of the table of SVID SDID to customize each SVID SDID entry. This is @@ -2227,7 +2242,7 @@ /** Offset 0x1A6E - Reserved **/ - UINT8 Reserved54[127]; + UINT8 Reserved55[127]; /** Offset 0x1AED - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3 Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each @@ -2292,7 +2307,7 @@ /** Offset 0x1B3F - Reserved **/ - UINT8 Reserved55; + UINT8 Reserved56; /** Offset 0x1B40 - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, @@ -2316,7 +2331,7 @@ /** Offset 0x1B42 - Reserved **/ - UINT8 Reserved56[2]; + UINT8 Reserved57[2]; /** Offset 0x1B44 - Enable TSN Multi-VC Enable/disable Multi Virtual Channels(VC) in TSN. @@ -2326,7 +2341,7 @@ /** Offset 0x1B45 - Reserved **/ - UINT8 Reserved57[11]; + UINT8 Reserved58[11]; /** Offset 0x1B50 - LogoPixelHeight Address Address of LogoPixelHeight @@ -2340,7 +2355,7 @@ /** Offset 0x1B58 - Reserved **/ - UINT8 Reserved58; + UINT8 Reserved59; /** Offset 0x1B59 - ITbt Usb4CmMode value ITbt Usb4CmMode value. 0:Firmware CM, 1:Software CM @@ -2349,7 +2364,7 @@ /** Offset 0x1B5A - Reserved **/ - UINT8 Reserved59[75]; + UINT8 Reserved60[75]; /** Offset 0x1BA5 - RSR feature Enable or Disable RSR feature; 0: Disable; 1: Enable @@ -2359,7 +2374,7 @@ /** Offset 0x1BA6 - Reserved **/ - UINT8 Reserved60[4]; + UINT8 Reserved61[4]; /** Offset 0x1BAA - Enable or Disable HWP Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the @@ -2756,7 +2771,7 @@ /** Offset 0x1C1A - Reserved **/ - UINT8 Reserved61[2]; + UINT8 Reserved62[2]; /** Offset 0x1C1C - Package Long duration turbo mode power limit Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming. @@ -2796,7 +2811,7 @@ /** Offset 0x1C2C - Reserved **/ - UINT8 Reserved62[4]; + UINT8 Reserved63[4]; /** Offset 0x1C30 - Tcc Offset Time Window for RATL **/ @@ -2873,7 +2888,7 @@ /** Offset 0x1C54 - Reserved **/ - UINT8 Reserved63; + UINT8 Reserved64; /** Offset 0x1C55 - Race To Halt Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency @@ -2885,7 +2900,7 @@ /** Offset 0x1C56 - Reserved **/ - UINT8 Reserved64; + UINT8 Reserved65; /** Offset 0x1C57 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. @@ -2895,7 +2910,7 @@ /** Offset 0x1C58 - Reserved **/ - UINT8 Reserved65[4]; + UINT8 Reserved66[4]; /** Offset 0x1C5C - Enable or Disable C1 Cstate Demotion Enable or Disable C1 Cstate Auto Demotion. Disable; 1: Enable @@ -2953,7 +2968,7 @@ /** Offset 0x1C64 - Reserved **/ - UINT8 Reserved66; + UINT8 Reserved67; /** Offset 0x1C65 - Dual Tau Boost Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W @@ -2964,7 +2979,7 @@ /** Offset 0x1C66 - Reserved **/ - UINT8 Reserved67[34]; + UINT8 Reserved68[34]; /** Offset 0x1C88 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3002,7 +3017,7 @@ /** Offset 0x1C8D - Reserved **/ - UINT8 Reserved68[17]; + UINT8 Reserved69[17]; /** Offset 0x1C9E - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. @@ -3031,7 +3046,7 @@ /** Offset 0x1CA2 - Reserved **/ - UINT8 Reserved69[2]; + UINT8 Reserved70[2]; /** Offset 0x1CA4 - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -3080,7 +3095,7 @@ /** Offset 0x1E1D - Reserved **/ - UINT8 Reserved70; + UINT8 Reserved71; /** Offset 0x1E1E - PCIE RP Slot Power Limit Value Specifies upper limit on power supplie by slot. Leave as 0 to set to default. @@ -3127,7 +3142,7 @@ /** Offset 0x1E5E - Reserved **/ - UINT8 Reserved71[105]; + UINT8 Reserved72[105]; /** Offset 0x1EC7 - PMC C10 dynamic threshold dajustment enable Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs @@ -3137,7 +3152,7 @@ /** Offset 0x1EC8 - Reserved **/ - UINT8 Reserved72[36]; + UINT8 Reserved73[36]; /** Offset 0x1EEC - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -3146,7 +3161,7 @@ /** Offset 0x1EF0 - Reserved **/ - UINT8 Reserved73[32]; + UINT8 Reserved74[32]; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/81674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9a18b83fbb2d7760bd58027a4203919489b01580 Gerrit-Change-Number: 81674 Gerrit-PatchSet: 1 Gerrit-Owner: srinivas.kulkarni(a)intel.com Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch,toolchain,xcompile: Use GCC as linker
by Jacob Garber (Code Review) 04 Apr '24

04 Apr '24

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40811 ) Change subject: arch,toolchain,xcompile: Use GCC as linker ...................................................................... arch,toolchain,xcompile: Use GCC as linker Code generation when using LTO is not done until after linking, so the compiler must be invoked at all linking stages instead of the linker. Replace $(LD) with GCC, and prefix all linker-specific flags with -Wl so they will be passed to the linker. Change-Id: Ia551cf84c8f6eb3b010450fc572876a318a257d1 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile.inc M src/arch/arm/Makefile.inc M src/arch/arm64/Makefile.inc M src/arch/ppc64/Makefile.inc M src/arch/riscv/Makefile.inc M src/arch/x86/Makefile.inc M src/cpu/x86/smm/Makefile.inc M src/lib/Makefile.inc M toolchain.inc M util/xcompile/xcompile 10 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/40811/1 diff --git a/Makefile.inc b/Makefile.inc index e315732..ef95870 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -479,7 +479,7 @@ # Disable style checks for now ADAFLAGS_common += -gnatyN -LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs +LDFLAGS_common := -nostdlib -nostartfiles -static -Wl,--emit-relocs,--gc-sections ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y) CFLAGS_common += -Werror diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index a8abfaf..f13bf1e 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -54,11 +54,11 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(bootblock-objs)) -Wl,--end-group $(objcbfs)/decompressor.debug: $$(decompressor-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(decompressor-objs)) -Wl,--end-group endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -70,7 +70,7 @@ $(objcbfs)/verstage.debug: $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(verstage-objs)) -Wl,--end-group verstage-y += boot.c verstage-y += div0.c @@ -103,7 +103,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(romstage-objs)) -Wl,--end-group endif # CONFIG_ARCH_ROMSTAGE_ARM @@ -132,6 +132,6 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) -Wl,--end-group endif # CONFIG_ARCH_RAMSTAGE_ARM diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index c3d1fe5..e9d6d05 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -50,11 +50,11 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) --end-group -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(bootblock-objs)) -Wl,--end-group -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) $(objcbfs)/decompressor.debug: $$(decompressor-objs) $(obj)/config.h @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(decompressor-objs)) --end-group -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(decompressor-objs)) -Wl,--end-group -T $(call src-to-obj,decompressor,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) endif # CONFIG_ARCH_BOOTBLOCK_ARM64 @@ -66,7 +66,7 @@ $(objcbfs)/verstage.debug: $$(verstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(verstage-objs)) --end-group -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_verstage) $(LDFLAGS_verstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(verstage-objs)) -Wl,--end-group -T $(call src-to-obj,verstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) verstage-y += boot.c verstage-y += div0.c @@ -104,7 +104,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(romstage-objs)) -Wl,--end-group -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) endif # CONFIG_ARCH_ROMSTAGE_ARM64 @@ -139,7 +139,7 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) -Wl,--end-group -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) # Build ARM Trusted Firmware (BL31) diff --git a/src/arch/ppc64/Makefile.inc b/src/arch/ppc64/Makefile.inc index 1c35f6f..b8da940 100644 --- a/src/arch/ppc64/Makefile.inc +++ b/src/arch/ppc64/Makefile.inc @@ -29,8 +29,8 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ - $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) + -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(bootblock-objs)) \ + $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group $(COMPILER_RT_bootblock) endif @@ -55,7 +55,7 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(romstage-objs)) -Wl,--end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(ppc64_flags) romstage-S-ccopts += $(ppc64_asm_flags) @@ -88,7 +88,7 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) -Wl,--end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(ppc64_flags) ramstage-S-ccopts += $(ppc64_asm_flags) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 17f225a..fd18e55 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -69,14 +69,14 @@ $(objcbfs)/bootblock.debug: $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" $(LD_bootblock) $(LDFLAGS_bootblock) -o $@ -L$(obj) \ - -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(bootblock-objs)) \ - $(LIBGCC_FILE_NAME_bootblock) --end-group $(COMPILER_RT_bootblock) + -T $(call src-to-obj,bootblock,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(bootblock-objs)) \ + $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group $(COMPILER_RT_bootblock) bootblock-c-ccopts += $(riscv_flags) bootblock-S-ccopts += $(riscv_asm_flags) ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_bootblock += -m elf32lriscv +LDFLAGS_bootblock += -Wl,-m,elf32lriscv endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_BOOTBLOCK_RISCV @@ -104,13 +104,13 @@ $(objcbfs)/romstage.debug: $$(romstage-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(romstage-objs)) --end-group $(COMPILER_RT_romstage) + $(LD_romstage) $(LDFLAGS_romstage) -o $@ -L$(obj) -T $(call src-to-obj,romstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(romstage-objs)) -Wl,--end-group $(COMPILER_RT_romstage) romstage-c-ccopts += $(riscv_flags) romstage-S-ccopts += $(riscv_asm_flags) ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_romstage += -m elf32lriscv +LDFLAGS_romstage += -Wl,-m,elf32lriscv endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_ROMSTAGE_RISCV @@ -153,13 +153,13 @@ $(objcbfs)/ramstage.debug: $$(ramstage-objs) @printf " CC $(subst $(obj)/,,$(@))\n" - $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group $(COMPILER_RT_ramstage) + $(LD_ramstage) $(LDFLAGS_ramstage) -o $@ -L$(obj) -T $(call src-to-obj,ramstage,src/mainboard/$(MAINBOARDDIR)/memlayout.ld) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) -Wl,--end-group $(COMPILER_RT_ramstage) ramstage-c-ccopts += $(riscv_flags) ramstage-S-ccopts += $(riscv_asm_flags) ifeq ($(CONFIG_ARCH_RISCV_RV32),y) -LDFLAGS_ramstage += -m elf32lriscv +LDFLAGS_ramstage += -Wl,-m,elf32lriscv endif #CONFIG_ARCH_RISCV_RV32 endif #CONFIG_ARCH_RAMSTAGE_RISCV diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 2d00709..af52f70 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -77,7 +77,7 @@ $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n" - $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) --whole-archive --start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) --no-whole-archive $$(COMPILER_RT_$(1)) --end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) --oformat $(2) + $$(LD_$(1)) $$(LDFLAGS_$(1)) -o $$@ -L$$(obj) $$(COMPILER_RT_FLAGS_$(1)) -Wl,--whole-archive,--start-group $$(filter-out %.ld,$$($(1)-objs)) $$($(1)-libs) -Wl,--no-whole-archive $$(COMPILER_RT_$(1)) -Wl,--end-group -T $(call src-to-obj,$(1),$(dir)/memlayout.ld) -Wl,--oformat=$(2) -LANG=C LC_ALL= $$(OBJCOPY_$(1)) --only-section .illegal_globals $$(@) $$(objcbfs)/$(1)_null.offenders >/dev/null 2>&1 if [ -z "$$$$($$(NM_$(1)) $$(objcbfs)/$(1)_null.offenders 2>&1 | grep 'no symbols')" ];then \ echo "Forbidden global variables in $(1):"; \ @@ -209,11 +209,11 @@ postcar-y += postcar.c postcar-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c -LDFLAGS_postcar += -Map $(objcbfs)/postcar.map +LDFLAGS_postcar += -Wl,-Map,$(objcbfs)/postcar.map $(objcbfs)/postcar.debug: $$(postcar-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) --whole-archive --start-group $(filter-out %.ld,$^) --no-whole-archive $(COMPILER_RT_postcar) --end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) + $(LD_postcar) $(LDFLAGS_postcar) -o $@ -L$(obj) $(COMPILER_RT_FLAGS_postcar) -Wl,--whole-archive,--start-group $(filter-out %.ld,$^) -Wl,--no-whole-archive $(COMPILER_RT_postcar) -Wl,--end-group -T $(call src-to-obj,postcar,src/arch/x86/memlayout.ld) $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ @@ -314,9 +314,9 @@ $(objgenerated)/ramstage.o: $$(ramstage-objs) $(COMPILER_RT_ramstage) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - $(LD_ramstage) -m elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group + $(LD_ramstage) -Wl,-m,elf_i386 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group else - $(LD_ramstage) -m elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) --whole-archive --start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) --no-whole-archive $(COMPILER_RT_ramstage) --end-group + $(LD_ramstage) -Wl,-m,elf_x86_64 -r -o $@ $(COMPILER_RT_FLAGS_ramstage) -Wl,--whole-archive,--start-group $(filter-out %.ld,$(ramstage-objs)) $(ramstage-libs) -Wl,--no-whole-archive $(COMPILER_RT_ramstage) -Wl,--end-group endif endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64 diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 11a4e67..2e63fb3 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -26,7 +26,7 @@ smm-c-deps:=$$(OPTION_TABLE_H) $(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) - $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group + $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) -Wl,--whole-archive,--start-group $(smm-objs) -Wl,--no-whole-archive $(COMPILER_RT_smm) -Wl,--end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. @@ -53,7 +53,7 @@ # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. $(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(COMPILER_RT_smmstub) - $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) --whole-archive --start-group $(smmstub-objs) --no-whole-archive $(COMPILER_RT_smmstub) --end-group + $(LD_smmstub) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smmstub) -Wl,--whole-archive,--start-group $(smmstub-objs) -Wl,--no-whole-archive $(COMPILER_RT_smmstub) -Wl,--end-group # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 085f6b2..adcd16a 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -290,7 +290,7 @@ # rmdoule is named $(1).rmod define rmodule_link $(strip $(1)): $(strip $(2)) $$(COMPILER_RT_rmodules_$(4)) $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) | $$(RMODTOOL) - $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) --defsym=__heap_size=$(strip $(3)) -o $$@ --whole-archive --start-group $(filter-out %.ld,$(2)) --end-group + $$(LD_rmodules_$(4)) $$(LDFLAGS_rmodules_$(4)) $(RMODULE_LDFLAGS) -T $(call src-to-obj,rmodules_$(4),src/lib/rmodule.ld) -Wl,--defsym=__heap_size=$(strip $(3)) -o $$@ -Wl,--whole-archive,--start-group $(filter-out %.ld,$(2)) -Wl,--end-group $$(NM_rmodules_$(4)) -n $$@ > $$(basename $$(a)).map endef diff --git a/toolchain.inc b/toolchain.inc index 865227b..f52a518 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -117,7 +117,7 @@ $(error Check your .config file for CONFIG_ARCH_$(1)_* settings)) CC_$(1) := $(CC_$(2)) GCC_$(1) := $(GCC_CC_$(2)) -LD_$(1) := $(LD_$(2)) +LD_$(1) := $(CC_$(2)) NM_$(1) := $(NM_$(2)) AR_$(1) := $(AR_$(2)) GNATBIND_$(1) := $(GNATBIND_$(2)) @@ -130,7 +130,7 @@ CPPFLAGS_$(1) = $$(CPPFLAGS_common) $$(CPPFLAGS_$(2)) -D__ARCH_$(2)__ COMPILER_RT_$(1) := $$(COMPILER_RT_$(2)) COMPILER_RT_FLAGS_$(1) := $$(COMPILER_RT_FLAGS_$(2)) -LDFLAGS_$(1) = $$(LDFLAGS_common) $$(LDFLAGS_$(2)) +LDFLAGS_$(1) = $$(CFLAGS_$(1)) $$(LDFLAGS_common) $$(LDFLAGS_$(2)) endef # define_class: Allows defining any program as dynamic class and compiler tool diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 18e08a0..5e32120 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -363,7 +363,7 @@ TCLIST="i386 x86_64" TWIDTH="32" TABI="elf" - CC_RT_EXTRA_GCC="--wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3" + CC_RT_EXTRA_GCC="-Wl,--wrap=__divdi3,--wrap=__udivdi3,--wrap=__moddi3,--wrap=__umoddi3" } arch_config_ppc64() { -- To view, visit https://review.coreboot.org/c/coreboot/+/40811 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia551cf84c8f6eb3b010450fc572876a318a257d1 Gerrit-Change-Number: 40811 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

10 49

[M] Change in coreboot[main]: [for test] upgrade crossgcc
by Elyes Haouas (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81419?usp=email ) Change subject: [for test] upgrade crossgcc ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: would you check why Jenkins didn't mind at all here https://qa.coreboot.org/job/coreboot-toolchain/1592/consoleFull for nds32le-elf 😊 "Building LLVM v18.1.3 for host ... failed. Check 'build-LLVM/build.log'. make[1]: *** [Makefile:28: build_clang] Error 1 make: *** [util/crossgcc/Makefile.mk:38: clang] Error 2" -- To view, visit https://review.coreboot.org/c/coreboot/+/81419?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I463c303694c304bb3bf664bc1d914462e7af5dbb Gerrit-Change-Number: 81419 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 15:46:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
by Matt DeVillier (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Dinesh Gehlot, Elyes Haouas, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Kapil Porwal, Paul Menzel, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81615?usp=email ) Change subject: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Gerrit-Change-Number: 81615 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Apr 2024 15:42:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: lib: Refactor bmp_load_logo() implementation
by Matt DeVillier (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Dinesh Gehlot, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Kapil Porwal, Ronak Kanabar, Sean Rhodes, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81618?usp=email ) Change subject: lib: Refactor bmp_load_logo() implementation ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Gerrit-Change-Number: 81618 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Apr 2024 15:41:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3
by Arthur Heymans (Code Review) 04 Apr '24

04 Apr '24

Attention is currently required from: Felix Singer, Martin L Roth, Zebreus. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80314?usp=email ) Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3 ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: > > Arthur, could you have a look on the Jenkins issues? > > https://review.coreboot.org/c/coreboot/+/81434 is likely needed. I just merged it. So try a rebase on main? -- To view, visit https://review.coreboot.org/c/coreboot/+/80314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I03a44e0c23a925396f614f282882405dc886ba58 Gerrit-Change-Number: 80314 Gerrit-PatchSet: 9 Gerrit-Owner: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Zebreus <lennarteichhorn(a)googlemail.com> Gerrit-Comment-Date: Thu, 04 Apr 2024 15:12:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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