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Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS10:
> > https://lore.kernel.org/all/20240220204843.809772604@linuxfoundation.org/ […]
Great. Thanks for looking into it. I've rebased the patch. Let's see.
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Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
> https://lore.kernel.org/all/20240220204843.809772604@linuxfoundation.org/
>
> Apparently LLVM uses .ltext.* instead of text when -ffunction-sections and -mcmodel=large are used, which is the case for 64bit x86. I'll write a patch that accounts for this in the linker script.
CB:81675 would deal with it.
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Change subject: lib/program.ld: Account for .ltext section
......................................................................
lib/program.ld: Account for .ltext section
Starting with version 18 LLVM puts code generated with
-ffunction-section -mcmodel=large inside .ltext rather than .text so
account for that in the linker script.
Change-Id: Ib755673dfa9e71172bbef0a5aec075154c89a97b
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/lib/program.ld
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81675/1
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 1784447..fa9826a 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -23,6 +23,11 @@
KEEP(*(.metadata_hash_anchor));
*(.text);
*(.text.*);
+ /* Starting with version 18 LLVM the combination -ffunction-section -mcmodel=large
+ * puts code in .ltext rather than .text.
+ */
+ *(.ltext);
+ *(.ltext.*);
#if ENV_HAS_CBMEM
. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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Change subject: util/crossgcc: Update LLVM from 17.0.6 to 18.1.3
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS10:
https://lore.kernel.org/all/20240220204843.809772604@linuxfoundation.org/
Apparently LLVM uses .ltext.* instead of text when -ffunction-sections and -mcmodel=large are used, which is the case for 64bit x86. I'll write a patch that accounts for this in the linker script.
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Change subject: mb/google/nissa/var/anraggar: Delay deassert RST pin for TCHSCR
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81636/comment/84ed2fd1_182ea8b3 :
PS3, Line 7: Delay to deassert RST pin for TCHSCR
> Since it is configuring both RST and EN pin for touchscreen, may be […]
EN pin is not changed.
https://review.coreboot.org/c/coreboot/+/81636/comment/4ec2a372_d79aabc9 :
PS3, Line 9: Change to pull up
> “Change to” is redundant in the commit message: Pull up GPP_C1 (RST pin of touchscreen) in override […]
Done
https://review.coreboot.org/c/coreboot/+/81636/comment/1bccd688_bf436540 :
PS3, Line 15: touchscreen function workable
> may be "Build, Boot anraggar board and check touchscreen working" ?
Done
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81636?usp=email
to look at the new patch set (#4).
Change subject: mb/google/nissa/var/anraggar: Delay deassert RST pin for TCHSCR
......................................................................
mb/google/nissa/var/anraggar: Delay deassert RST pin for TCHSCR
Pull up GPP_C1 (RST pin of touchscreen) in override GPIO table instead of early GPIO table to make RST (GPP_C1) delay VDD (GPP_C0) raising by more than 10ms to adapt to SPEC "ILI2901 Data Sheet_V1.4_20230328.pdf"
requirements.
BUG=b:314744757
TEST=Build, Boot anraggar board and check touchscreen working
Change-Id: I4bd17ecf8ffbe6ca8791fa1bc4577f4dfb4ea8e8
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81636/4
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Change subject: mb/google/brya: Sort Kconfig option alphabetically
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/brya/Kconfig:
https://review.coreboot.org/c/coreboot/+/81631/comment/38ee11c0_6b2381e1 :
PS3, Line 574: config DRIVER_TPM_I2C_BUS
> that would result in quite long line, […]
Lines can be continued with backslashes. I feel this way it's much better structured and readable. Otherwise I would go for numerical ordering instead of alphabetical, I guess.
Anyway, I'm not intending to block. I just wanted to raise the idea this case.
Marking as resolved.
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Change subject: lib: Refactor bmp_load_logo() implementation
......................................................................
Patch Set 4:
(1 comment)
File src/soc/amd/mendocino/fsp_s_params.c:
https://review.coreboot.org/c/coreboot/+/81618/comment/dca3701b_265a1b91 :
PS4, Line 59: supd->FspsConfig.logo_bmp_buffer = (uint32_t)(uintptr_t)bmp_load_logo(&logo_size);
> I'm curious why the logo size isn't updated in the FspsConfig.
because this is Intel owned and managed by FSP. FSP UPDs are unified for API and dispatch mode hence in summary, to make any change in FspsConfig, we need to change the FSP source code.
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