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Change subject: soc/intel/xeon_sp/spr: Enable BROKEN_FSP_NEEDS_STACK_ABOVE_BSS
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Patch Set 2:
(1 comment)
Patchset:
PS2:
Superseeded by CB:80579
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Change subject: soc/intel/xeon_sp/spr: Drop microcode constraints
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81635/comment/f0fab676_54b3a3eb :
PS1, Line 7: constrains
> typo: constrain**t**s
Done
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Change subject: drivers/intel: Align FSP debug handler with EFI calling convention
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Patch Set 4:
(1 comment)
Patchset:
PS4:
> > When mixing 32bit FSP with 64bit coreboot using trampolines, this might not work so well: see https://review.coreboot.org/c/coreboot/+/79823 . Any thoughts?
>
> To be clear, that code was WIP and does not work yet, so it should not be stalling your effort here. Just wondering what your take would be on this.
Thanks for sharing the CL.
So far (this patch train and few are in another thread) we are testing 32-bit FSP with 32-bit build/booting and likewise for 64-bit FSP/coreboot combination. There are CLs in the pipeline that we are testing to complete the Meteor Lake 64-bit transition as POC. Featurewise there is no regression.
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Change subject: drivers/intel/fsp2_0: Introduce fsp print helper macros
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Patch Set 5:
(1 comment)
Patchset:
PS5:
> can you remove, WIP tag?
Done. I am still verifying changes in the MTL x32 and x64
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Change subject: drivers/intel/fsp2_0: Introduce fsp print helper macros
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Set Ready For Review
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