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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 36:
(1 comment)
Patchset:
PS32:
> I tentatively split this one into 2. Could you please have a look? […]
Done
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Change subject: soc/intel/xeon_sp: Share unlock_pam_regions()
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/google/nissa/var/anraggar: Delay to deassert RST pin for TCHSCR
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81636/comment/66af37be_a7062ac3 :
PS2, Line 9: touchscree
> touchscreen
Done
https://review.coreboot.org/c/coreboot/+/81636/comment/28a05eaf_99cf357b :
PS2, Line 11: SPEC requirements.
> It would be good if you could mention the spec which you are referring to and the version of that sp […]
Done
https://review.coreboot.org/c/coreboot/+/81636/comment/7bbe3376_c08bb260 :
PS2, Line 13: BUG=314744757
> "BUG=b:314744757" ?
Done
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81636?usp=email
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Change subject: mb/google/nissa/var/anraggar: Delay to deassert RST pin for TCHSCR
......................................................................
mb/google/nissa/var/anraggar: Delay to deassert RST pin for TCHSCR
Change to pull up the GPP_C1 (RST pin of touchscreen) from early table
to override table, make RST (GPP_C1) delay VDD (GPP_C0) raising by
more than 10ms to adapt to SPEC "ILI2901 Data Sheet_V1.4_20230328.pdf"
requirements.
BUG=b:314744757
TEST=touchscreen function workable
Change-Id: I4bd17ecf8ffbe6ca8791fa1bc4577f4dfb4ea8e8
Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/gpio.c
1 file changed, 6 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81636/3
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Change subject: soc/amd/genoa_poc: Fix DEBUG_SMI compilation error
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81072/comment/2a928d2d_5e0ded25 :
PS1, Line 7: Fix DEBUG_SMI compilation error
> I’d make it more about the action.
Something like this?
> soc/amd/genoa_poc: Allow using UART with DEBUG_SMI=y
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Change subject: soc/intel/xeon_sp/spr: Use official microcodes
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/xeon_sp: Compress FSP-S
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81634/comment/26977407_bba28c7e :
PS1, Line 12: Test: Still boots on ibm/sbp1.
> Are there boot time differences? (Probably small compared to server boot time. […]
That wasn't measured.
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81637?usp=email )
Change subject: soc/intel/xeon_sp/spr: Use official microcodes
......................................................................
soc/intel/xeon_sp/spr: Use official microcodes
Use the official microcode updates from intel-microcode submodule
by default. Downstream users can still decide to use their own files.
Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/soc/intel/xeon_sp/spr/Kconfig
M src/soc/intel/xeon_sp/spr/Makefile.mk
2 files changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81637/1
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 18efbe5..af3e8eb 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -3,7 +3,6 @@
config SOC_INTEL_SAPPHIRERAPIDS_SP
bool
select FSP_NVS_DATA_POST_SILICON_INIT
- select MICROCODE_BLOB_NOT_HOOKED_UP
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select DISABLE_ACPI_HIBERNATE
select DEFAULT_X2APIC_RUNTIME
diff --git a/src/soc/intel/xeon_sp/spr/Makefile.mk b/src/soc/intel/xeon_sp/spr/Makefile.mk
index d288df6..a3d6af5 100644
--- a/src/soc/intel/xeon_sp/spr/Makefile.mk
+++ b/src/soc/intel/xeon_sp/spr/Makefile.mk
@@ -19,4 +19,7 @@
ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02
+
endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP
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