coreboot-gerrit April 2024

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[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Jianeng Ceng (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Dolan Liu, Eric Lai, Jianeng Ceng, Subrata Banik. Hello Dolan Liu, Eric Lai, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81773?usp=email to look at the new patch set (#4). Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... drivers/i2c/rt5645: Add RT5645 amp driver Add RT5645 AMP support. Add acpi name cbj-sleeve-gpios for sleeve power gate GPIO. Realtek upstream link:(https://lore.kernel.org/all/20240404035747.118064-1-derek.fang@realte… BUG=None TEST=RT5645 driver can probe properly. Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- A src/drivers/i2c/rt5645/Kconfig A src/drivers/i2c/rt5645/Makefile.mk A src/drivers/i2c/rt5645/chip.h A src/drivers/i2c/rt5645/rt5645.c 4 files changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81773/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 4 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Jianeng Ceng (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Dolan Liu, Eric Lai, Jianeng Ceng, Subrata Banik. Hello Dolan Liu, Eric Lai, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81773?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Code-Review+1 by Dolan Liu, Verified+1 by build bot (Jenkins) Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... drivers/i2c/rt5645: Add RT5645 amp driver Add RT5645 AMP support. Add acpi name cbj-sleeve-gpios for sleeve power gate GPIO. Realtek upstream link:(https://lore.kernel.org/all/20240404035747.11 8064-1-derek.fang(a)realtek.com/) BUG=None TEST=RT5645 driver can probe properly. Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- A src/drivers/i2c/rt5645/Kconfig A src/drivers/i2c/rt5645/Makefile.mk A src/drivers/i2c/rt5645/chip.h A src/drivers/i2c/rt5645/rt5645.c 4 files changed, 154 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/81773/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 3 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/haswell: Fully disable iGPU when dGPU is used
by Arthur Heymans (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Angel Pons, Leah Rowe. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81644?usp=email ) Change subject: nb/haswell: Fully disable iGPU when dGPU is used ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81644/comment/1bcbf7a0_2b52e2f7 : PS1, Line 11: you also need to disable the iGPU entirely. What do you mean by 'need to' ? Also a dGPU does not need to be on the PEG slot and probably works fine if installed in a PCH PCIe slot. -- To view, visit https://review.coreboot.org/c/coreboot/+/81644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I944123d41ba0e69d74de424e655de33691089c85 Gerrit-Change-Number: 81644 Gerrit-PatchSet: 1 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Apr 2024 13:28:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: Makefile.mk: Account for large code model sections in cbfs_struct
by Arthur Heymans (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81777?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: Makefile.mk: Account for large code model sections in cbfs_struct ...................................................................... Makefile.mk: Account for large code model sections in cbfs_struct Starting with version 18 LLVM puts code and data generated with -ffunction-section -mcmodel=large inside sections with an 'l' prefix. Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.mk 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81777/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7 Gerrit-Change-Number: 81777 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms
by Sergii Dmytruk (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Julius Werner, Patrick Rudolph. Hello Julius Werner, Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81800?usp=email to look at the new patch set (#2). Change subject: configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms ...................................................................... configs: enable TPM PPI for asrock_b85m_pro4.tpm2_txt_placeholder_acms This is a good board for compiling TPM PPI sources for the following reasons (based on `config TPM_PPI` definition): - uses TPM - the board is not related to ChromeOS - ACPI tables are enabled - it doesn't use EDK2 payload At the moment drivers/tpm/ppi.c seems to not be compiled by CI at all, see CB:69161 and CB:81590. `CONFIG_TPM_PPI` is off by default but at least several configurations under `configs/` (Protectli, MSI) should exercise the file because they use EDK2 payload which changes default value. This is however negated by abuild disabling all payloads and thus effectively preventing `CONFIG_TPM_PPI` from being set. This board not using EDK2 also ensures that `CONFIG_TPM_PPI=y` will not disappear after some future `make savedefconfig`. Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7 Signed-off-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> --- M configs/config.asrock_b85m_pro4.tpm2_txt_placeholder_acms 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/81800/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81800?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I316747a79b3142e9d6188c5986b344c7751d92d7 Gerrit-Change-Number: 81800 Gerrit-PatchSet: 2 Gerrit-Owner: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: amdfwtool: Add a unified function to add combo entries
by Bao Zheng (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81779?usp=email to review the following change. Change subject: amdfwtool: Add a unified function to add combo entries ...................................................................... amdfwtool: Add a unified function to add combo entries TEST=Binary identical test on all AMD SOC platform with use_combo Change-Id: Ib72d59341708acf4df84502b4973ec190b33aeb6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/81779/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7f5b0cb..900dc56 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1470,6 +1470,20 @@ ctx->current_table = current_table_save; } +static void add_combo_entry(void *combo_dir, void *dir, uint32_t combo_index, + context *ctx, amd_cb_config *cb_config) +{ + psp_combo_directory *cdir = combo_dir; + /* 0 -Compare PSP ID, 1 -Compare chip family ID */ + assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, ctx); + cdir->entries[combo_index].id_sel = 0; + cdir->entries[combo_index].id = get_psp_id(cb_config->soc_id); + cdir->entries[combo_index].lvl2_addr = + BUFF_TO_RUN_MODE(*ctx, dir, AMD_ADDR_REL_BIOS); + + fill_dir_header(combo_dir, combo_index + 1, ctx); +} + static int set_efs_table(uint8_t soc_id, amd_cb_config *cb_config, embedded_firmware *amd_romsig) { @@ -1747,14 +1761,7 @@ fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); } else { fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config); - /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); - ctx.psp_combo_dir->entries[combo_index].id_sel = 0; - ctx.psp_combo_dir->entries[combo_index].id = get_psp_id(cb_config.soc_id); - ctx.psp_combo_dir->entries[combo_index].lvl2_addr = - BUFF_TO_RUN_MODE(ctx, ctx.pspdir, AMD_ADDR_REL_BIOS); - - fill_dir_header(ctx.psp_combo_dir, combo_index + 1, &ctx); + add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config); } if (have_bios_tables(amd_bios_table)) { @@ -1787,14 +1794,7 @@ */ fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.bhd_combo_dir, &ctx, &cb_config); - assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); - ctx.bhd_combo_dir->entries[combo_index].id_sel = 0; - ctx.bhd_combo_dir->entries[combo_index].id = - get_psp_id(cb_config.soc_id); - ctx.bhd_combo_dir->entries[combo_index].lvl2_addr = - BUFF_TO_RUN_MODE(ctx, ctx.biosdir, AMD_ADDR_REL_BIOS); - - fill_dir_header(ctx.bhd_combo_dir, combo_index + 1, &ctx); + add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, combo_index, &ctx, &cb_config); } } if (cb_config.debug) -- To view, visit https://review.coreboot.org/c/coreboot/+/81779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib72d59341708acf4df84502b4973ec190b33aeb6 Gerrit-Change-Number: 81779 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: amdfwtool: Set the field when the header is created
by Bao Zheng (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81778?usp=email to review the following change. Change subject: amdfwtool: Set the field when the header is created ...................................................................... amdfwtool: Set the field when the header is created Only update the count, size and fletcher in later calls. TEST=Binary identical test on all AMD SOC platform Change-Id: If363b4bc3f148c18432c9b2e0240554a62b51c68 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81778/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1dac476..7f5b0cb 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -492,6 +492,8 @@ ((psp_directory_header *)ptr)->num_entries = 0; ((psp_directory_header *)ptr)->additional_info = 0; ((psp_directory_header *)ptr)->additional_info_fields.address_mode = ctx->address_mode; + ((psp_directory_header *)ptr)->additional_info_fields.spi_block_size = 1; + ((psp_directory_header *)ptr)->additional_info_fields.base_addr = 0; adjust_current_pointer(ctx, sizeof(psp_directory_header) + MAX_PSP_ENTRIES * sizeof(psp_directory_entry), 1); @@ -515,6 +517,11 @@ adjust_current_pointer(ctx, 0, TABLE_ALIGNMENT); ptr = BUFF_CURRENT(*ctx); ((psp_combo_header *)ptr)->cookie = cookie; + /* lookup mode is hardcoded for now. */ + ((psp_combo_header *)ptr)->lookup = 1; + ((psp_combo_header *)ptr)->reserved[0] = 0; + ((psp_combo_header *)ptr)->reserved[1] = 0; + adjust_current_pointer(ctx, sizeof(psp_combo_header) + MAX_COMBO_ENTRIES * sizeof(psp_combo_entry), 1); @@ -541,11 +548,7 @@ switch (cookie) { case PSP2_COOKIE: case BHD2_COOKIE: - /* lookup mode is hardcoded for now. */ - cdir->header.lookup = 1; cdir->header.num_entries = count; - cdir->header.reserved[0] = 0; - cdir->header.reserved[1] = 0; /* checksum everything that comes after the Checksum field */ cdir->header.checksum = fletcher32(&cdir->header.num_entries, count * sizeof(psp_combo_entry) @@ -569,8 +572,6 @@ table_size / TABLE_ALIGNMENT; } dir->header.num_entries = count; - dir->header.additional_info_fields.spi_block_size = 1; - dir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ dir->header.checksum = fletcher32(&dir->header.num_entries, count * sizeof(psp_directory_entry) @@ -591,8 +592,6 @@ table_size / TABLE_ALIGNMENT; } bdir->header.num_entries = count; - bdir->header.additional_info_fields.spi_block_size = 1; - bdir->header.additional_info_fields.base_addr = 0; /* checksum everything that comes after the Checksum field */ bdir->header.checksum = fletcher32(&bdir->header.num_entries, count * sizeof(bios_directory_entry) @@ -600,7 +599,6 @@ + sizeof(bdir->header.additional_info)); break; } - } static void fill_psp_directory_to_efs(embedded_firmware *amd_romsig, void *pspdir, @@ -1131,6 +1129,8 @@ ((bios_directory_hdr *) ptr)->cookie = cookie; ((bios_directory_hdr *) ptr)->additional_info = 0; ((bios_directory_hdr *) ptr)->additional_info_fields.address_mode = ctx->address_mode; + ((bios_directory_hdr *) ptr)->additional_info_fields.spi_block_size = 1; + ((bios_directory_hdr *) ptr)->additional_info_fields.base_addr = 0; adjust_current_pointer(ctx, sizeof(bios_directory_hdr) + MAX_BIOS_ENTRIES * sizeof(bios_directory_entry), 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/81778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If363b4bc3f148c18432c9b2e0240554a62b51c68 Gerrit-Change-Number: 81778 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: driver/i2c/rt5645: add RT5645 codec driver
by Paul Menzel (Code Review) 08 Apr '24

08 Apr '24

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[M] Change in coreboot[main]: driver/i2c/rt5645: add RT5645 codec driver
by Paul Menzel (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Dolan Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81776?usp=email ) Change subject: driver/i2c/rt5645: add RT5645 codec driver ...................................................................... Patch Set 1: (9 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81776/comment/2c8039d8_29a9f4e9 : PS1, Line 2: Dolan Use Dolan Liu? $ git config --global user.name "Dolan Liu" $ git commmit --amend -s --author="Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com>" https://review.coreboot.org/c/coreboot/+/81776/comment/d94ab984_50b80c1c : PS1, Line 9: Add rt5645 codec support. Please summarize the features of the RT5645, and mention the datasheet name and revision. https://review.coreboot.org/c/coreboot/+/81776/comment/356cdbb6_2a8a9e53 : PS1, Line 13: Test: Test on anraggar, RT5645 driver can probe properly TEST=Successfully probe RT5645 on anraggar, and notice the log line: … https://review.coreboot.org/c/coreboot/+/81776/comment/ab5a8787_7e093c0d : PS1, Line 14: Change-Id: I23407b451c728fb0cfad813552afc6d24e95608a Missing Signed-off-by Line. File src/drivers/i2c/rt5645/rt5645.c: https://review.coreboot.org/c/coreboot/+/81776/comment/f4ab6437_28f34110 : PS1, Line 32: int hp_mic_index = -1, irq_gpio_index = -1, hp_detect_index=-1; > `spaces required around that '=' (ctx:VxO)` Please fix. https://review.coreboot.org/c/coreboot/+/81776/comment/f654bfdc_c774ee5d : PS1, Line 91: if (config->hp_mic.pin_count) > `trailing whitespace` Please fix. https://review.coreboot.org/c/coreboot/+/81776/comment/1f257ab7_eee75c2f : PS1, Line 92: acpi_dp_add_gpio(dp, "hp-mic-gpios", path, hp_mic_index, 0, config->hp_mic.active_low); Indent? https://review.coreboot.org/c/coreboot/+/81776/comment/fbaa2679_b80917de : PS1, Line 93: if (config->hp_detect.pin_count) What is the scope? https://review.coreboot.org/c/coreboot/+/81776/comment/02753ff4_05709823 : PS1, Line 129: .name="ASoC RT5645 Codec driver", > `spaces required around that '=' (ctx:VxV)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/81776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23407b451c728fb0cfad813552afc6d24e95608a Gerrit-Change-Number: 81776 Gerrit-PatchSet: 1 Gerrit-Owner: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Apr 2024 13:08:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/acpi/thermal_zone: Correct Kelvin constant used for conversion
by Paul Menzel (Code Review) 08 Apr '24

08 Apr '24

Attention is currently required from: Nicholas Sudsgaard. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81197?usp=email ) Change subject: drivers/acpi/thermal_zone: Correct Kelvin constant used for conversion ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81197?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I845bc750681c7ae6f2d1342b32983b990ce6d296 Gerrit-Change-Number: 81197 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Comment-Date: Mon, 08 Apr 2024 13:01:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2024