Werner Zeh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81678?usp=email )
Change subject: src/arch/x86/bootblock.ld: Preserve space for the .init section
......................................................................
Abandoned
Turned out that the issue I was seeing was caused by the old linker 2.37 (coreboot toolchain from 2022) and it indeed is an error in ld. The patch that fixes it in ld is can be found in [1].
TLDR: ld has evaluated SIZEOF() wrong as zero under certain conditions which then led to a wrongly placed .text-section in the bootblock which then caused the overlap with the section .init.
Switching just ld to the new version 2.42 (while keep the rest of the tools untouched at the state of 2022) fixes the issue reliably.
[1]: https://github.com/bminor/binutils-gdb/commit/648f6099d4dcadf446f3f00790ad4…
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 38:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81316/comment/ad0e72ac_3d9b7907 :
PS32, Line 20:
> Sorry, the SoC is not launched yet and hence the datasheet is not made public. […]
Please allow me to close the open now and if any opens please feel free to reopen. Thanks!
File src/soc/intel/xeon_sp/gnr/Kconfig:
https://review.coreboot.org/c/coreboot/+/81316/comment/4456cea5_76ac3e6c :
PS37, Line 68: default 0x142000
: help
: On xeon_sp/gnr FSP-M has two separate heap managers, one regular
: whose size and base are controllable via the StackBase and
: StackSize UPDs and a 'rc' heap manager that is statically
: allocated at 0xfe800000 (the CAR base) and consumes about 0x150000
: bytes of memory.
> helpt text says 0x150000, but option 0x142000
Sure, updated.
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Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/chip_gen1.c
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/uncore.c
23 files changed, 1,311 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/39
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Zoey Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81782?usp=email )
Change subject: mb/google/aurash: Skip sending the MBP HOB to save boot time
......................................................................
mb/google/aurash: Skip sending the MBP HOB to save boot time
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~100msec.
Boot time data:
Before:
* 955:returning from FspSiliconInit 1,198,533 (192,302)
After:
* 955:returning from FspSiliconInit 1,087,750 (76,972)
BUG=b:
TEST=Verified that boot time is reduced by ~100msec.
Change-Id: I5dc91f7a6ec53c2baddd98408185c4a1bbf6a3ae
Signed-off-by: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/aurash/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/81782/1
diff --git a/src/mainboard/google/brya/variants/aurash/overridetree.cb b/src/mainboard/google/brya/variants/aurash/overridetree.cb
index 2b9ebfe..45d017d 100644
--- a/src/mainboard/google/brya/variants/aurash/overridetree.cb
+++ b/src/mainboard/google/brya/variants/aurash/overridetree.cb
@@ -53,6 +53,9 @@
register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{
.tdp_pl1_override = 64,
}"
+
+ register "skip_mbp_hob" = "1"
+
device domain 0 on
device ref dtt on
chip drivers/intel/dptf
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Hello Felix Singer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: Makefile.mk: Account for large code model sections in cbfs_struct
......................................................................
Makefile.mk: Account for large code model sections in cbfs_struct
Starting with version 18 LLVM puts code and data generated with
-ffunction-section -mcmodel=large inside sections with an 'l' prefix.
This would now also pick up const data in .rodata.
Change-Id: Ie07779ef548337772183ffe2d642f971d8cceae7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M Makefile.mk
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81777/3
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Change subject: mb/google/corsola: Add new board variant Skitty
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81772/comment/56d63c66_04798982 :
PS4, Line 12: emerge-corsola coreboot
> I don't think it can pass the build.
follow the CB:81218
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