coreboot-gerrit April 2024

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[L] Change in coreboot[main]: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, TangYiwei. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email ) Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City ...................................................................... Patch Set 11: (2 comments) File configs/builder/config.intel.crb.bnc: https://review.coreboot.org/c/coreboot/+/81322/comment/14d2c67b_503622d6 : PS11, Line 27: # : CONFIG_IFD_BIN_PATH="site-local/beechnutcity/descriptor.bin" : CONFIG_CPU_UCODE_BINARIES="site-local/beechnutcity/ucode.mcb" : CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd" : CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd" : CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd" : CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/graniterapids/sp/" > I'm not sure if upstream code should have references to site-local stuff? This is aligned with configs/builder/config.intel.crb.ac, should it be okay? File src/mainboard/intel/beechnutcity_crb/Kconfig: https://review.coreboot.org/c/coreboot/+/81322/comment/91080fe3_55d2c305 : PS11, Line 8: select MAINBOARD_USES_FSP2_0 > This should be removed (also from all other xeon_sp boards) Sure, raised a new one for this, https://review.coreboot.org/c/coreboot/+/81783 and let us discuss there. -- To view, visit https://review.coreboot.org/c/coreboot/+/81322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Gerrit-Change-Number: 81322 Gerrit-PatchSet: 11 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 09 Apr 2024 09:46:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: southbridge/intel/common/acpi: Update sleepstates.asl
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81784?usp=email ) Change subject: southbridge/intel/common/acpi: Update sleepstates.asl ...................................................................... southbridge/intel/common/acpi: Update sleepstates.asl sleepstates.asl will be widely used by Xeon-SP as well. For Xeon-SP, only S0 and S5 are supported. Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/southbridge/intel/common/acpi/sleepstates.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/81784/1 diff --git a/src/southbridge/intel/common/acpi/sleepstates.asl b/src/southbridge/intel/common/acpi/sleepstates.asl index 14ed86e..51475d8 100644 --- a/src/southbridge/intel/common/acpi/sleepstates.asl +++ b/src/southbridge/intel/common/acpi/sleepstates.asl @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ +#if CONFIG(XEON_SP_COMMON_BASE) +Name (SSFG, 0x00) +#else #if CONFIG(HAVE_ACPI_RESUME) Name (SSFG, 0x0D) #else Name (SSFG, 0x09) #endif +#endif If (CONFIG(ACPI_S1_NOT_SUPPORTED)) { SSFG &= 0xfe -- To view, visit https://review.coreboot.org/c/coreboot/+/81784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Gerrit-Change-Number: 81784 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81783?usp=email ) Change subject: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 ...................................................................... soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 MAINBOARD_USES_FSP2_0 selects PLATFORM_USES_FSP2_0 and POSTCAR_STAGE which are used by all Xeon-SP platforms. After the removal of MAINBOARD_USES_FSP2_0, PLATFORM_USES_FSP2_0 is implicitly selected by SoC Kconfigs in PLATFORM_USES_FSP2_X, POSTCAR_STAGE is selected by XEON_SP_COMMON_BASE. Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/mainboard/bytedance/bd_egs/Kconfig M src/mainboard/ibm/sbp1/Kconfig M src/mainboard/intel/archercity_crb/Kconfig M src/mainboard/intel/cedarisland_crb/Kconfig M src/mainboard/inventec/transformers/Kconfig M src/mainboard/ocp/deltalake/Kconfig M src/mainboard/ocp/tiogapass/Kconfig M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 10 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/81783/1 diff --git a/src/mainboard/bytedance/bd_egs/Kconfig b/src/mainboard/bytedance/bd_egs/Kconfig index 4293181..433d962 100644 --- a/src/mainboard/bytedance/bd_egs/Kconfig +++ b/src/mainboard/bytedance/bd_egs/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig index d56f301..cb5b3fd 100644 --- a/src/mainboard/ibm/sbp1/Kconfig +++ b/src/mainboard/ibm/sbp1/Kconfig @@ -8,7 +8,6 @@ select IPMI_KCS select MAINBOARD_HAS_TPM2 select MEMORY_MAPPED_TPM - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select HAVE_ACPI_TABLES select MAINBOARD_USES_IFD_GBE_REGION diff --git a/src/mainboard/intel/archercity_crb/Kconfig b/src/mainboard/intel/archercity_crb/Kconfig index 87f274b..200fa49 100644 --- a/src/mainboard/intel/archercity_crb/Kconfig +++ b/src/mainboard/intel/archercity_crb/Kconfig @@ -11,7 +11,6 @@ select IPMI_OCP select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/intel/cedarisland_crb/Kconfig b/src/mainboard/intel/cedarisland_crb/Kconfig index 034ca3b..4e3a1cc 100644 --- a/src/mainboard/intel/cedarisland_crb/Kconfig +++ b/src/mainboard/intel/cedarisland_crb/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_65536 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/inventec/transformers/Kconfig b/src/mainboard/inventec/transformers/Kconfig index d0fdb82..108bf43 100644 --- a/src/mainboard/inventec/transformers/Kconfig +++ b/src/mainboard/inventec/transformers/Kconfig @@ -11,7 +11,6 @@ select IPMI_KCS_ROMSTAGE select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_SAPPHIRERAPIDS_SP select SUPERIO_ASPEED_AST2400 select HAVE_ACPI_TABLES diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index 039e6f9..27c8c34 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -7,7 +7,6 @@ select BOARD_ROMSIZE_KB_65536 select CONSOLE_OVERRIDE_LOGLEVEL select HAVE_ACPI_TABLES - select MAINBOARD_USES_FSP2_0 select SOC_INTEL_COOPERLAKE_SP select SUPERIO_ASPEED_AST2400 select IPMI_KCS diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 886743c..cbfb5c8 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -9,7 +9,6 @@ select IPMI_KCS select IPMI_KCS_ROMSTAGE select IPMI_OCP - select MAINBOARD_USES_FSP2_0 select OCP_DMI select SOC_INTEL_SKYLAKE_SP select SUPERIO_ASPEED_AST2400 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 78227ed..51f407e 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -45,15 +45,10 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE + select POSTCAR_STAGE if XEON_SP_COMMON_BASE -config MAINBOARD_USES_FSP2_0 - bool - default y - select PLATFORM_USES_FSP2_0 - select POSTCAR_STAGE - config MAX_SOCKET int default 2 diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig index 4a9e683..25e35bd 100644 --- a/src/soc/intel/xeon_sp/skx/Kconfig +++ b/src/soc/intel/xeon_sp/skx/Kconfig @@ -11,13 +11,8 @@ if SOC_INTEL_SKYLAKE_SP -config MAINBOARD_USES_FSP2_0 - bool - default y - config FSP_HEADER_PATH string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 default "src/vendorcode/intel/fsp/fsp2_0/skylake_sp" config MAX_SOCKET diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 2e0ad01..b40a534 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -28,7 +28,6 @@ config FSP_HEADER_PATH string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 default "src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp" config MAX_CPUS -- To view, visit https://review.coreboot.org/c/coreboot/+/81783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Gerrit-Change-Number: 81783 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#40). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=Build and boot on intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 23 files changed, 1,310 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 40 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: driver/i2c/rt5645: add RT5645 codec driver
by Dolan Liu (Code Review) 09 Apr '24

09 Apr '24

Dolan Liu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81776?usp=email ) Change subject: driver/i2c/rt5645: add RT5645 codec driver ...................................................................... Abandoned used CL 81773 -- To view, visit https://review.coreboot.org/c/coreboot/+/81776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23407b451c728fb0cfad813552afc6d24e95608a Gerrit-Change-Number: 81776 Gerrit-PatchSet: 1 Gerrit-Owner: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[main]: tree: Remove blank lines before '}' and after '{'
by Felix Held (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Angel Pons, Christian Walter, Elyes Haouas, Julius Werner, Maxim, Michał Żygowski, Philipp Hug, Piotr Król, Sean Rhodes, Uwe Poeche, Werner Zeh, ron minnich. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81455?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: tree: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 2: (1 comment) File util/intelp2m/parser/parser.go: https://review.coreboot.org/c/coreboot/+/81455/comment/0c682646_750de282 : PS2, Line 54: if !strings.Contains(info.function, "GPIO Community 0") { this is likely unrelated -- To view, visit https://review.coreboot.org/c/coreboot/+/81455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Gerrit-Change-Number: 81455 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 09:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/samsung: Move 'inline' between storage class and type
by Felix Held (Code Review) 09 Apr '24

09 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81593?usp=email ) Change subject: soc/samsung: Move 'inline' between storage class and type ...................................................................... soc/samsung: Move 'inline' between storage class and type Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81593 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/samsung/exynos5420/smp.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 13e9489..92c5175 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -64,14 +64,14 @@ * switching), we are not sure if the destination is Thumb or ARM mode. * So a BX command is required. */ -inline static void jump_bx(void *address) +static inline void jump_bx(void *address) { asm volatile ("bx %0" : : "r"(address)); /* never returns. */ } /* Extracts arbitrary bits from a 32-bit unsigned int. */ -inline static uint32_t get_bits(uint32_t value, uint32_t start, uint32_t len) +static inline uint32_t get_bits(uint32_t value, uint32_t start, uint32_t len) { return ((value << (sizeof(value) * 8 - len - start)) >> (sizeof(value) * 8 - len)); -- To view, visit https://review.coreboot.org/c/coreboot/+/81593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccdb4770890751b7f9d1b35248fe57993342fd50 Gerrit-Change-Number: 81593 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/gfx: Remove unnecessary line continuations
by Felix Held (Code Review) 09 Apr '24

09 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81594?usp=email ) Change subject: drivers/gfx: Remove unnecessary line continuations ...................................................................... drivers/gfx: Remove unnecessary line continuations Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81594 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/gfx/generic/generic.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/drivers/gfx/generic/generic.c b/src/drivers/gfx/generic/generic.c index 0714565..f07a471 100644 --- a/src/drivers/gfx/generic/generic.c +++ b/src/drivers/gfx/generic/generic.c @@ -119,8 +119,8 @@ if (!config->device[i].addr && config->device[i].type) /* Though not strictly necessary, set the display index and port attachment to the device index, to ensure uniqueness */ - config->device[i].addr = DOD_DID_STD | DOD_FW_DETECT | \ - (config->device[i].type << 8) | \ + config->device[i].addr = DOD_DID_STD | DOD_FW_DETECT | + (config->device[i].type << 8) | (i << 4) | (i); acpigen_write_dword(config->device[i].addr); } -- To view, visit https://review.coreboot.org/c/coreboot/+/81594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic71516ae73d61c9f13876a5acc071645bbe8e866 Gerrit-Change-Number: 81594 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/mediatek/common/include/soc: Include header file for check_member
by Felix Held (Code Review) 09 Apr '24

09 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81684?usp=email ) Change subject: soc/mediatek/common/include/soc: Include header file for check_member ...................................................................... soc/mediatek/common/include/soc: Include header file for check_member To fix the build error below when include i2c_common.h, we should include the necessary header for check_member. """ src/soc/mediatek/common/include/soc/i2c_common.h:24:42: error: expected ')' before numeric constant 24 | check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); | ^~~~~ | ) """ TEST=abuild -t google/geralt -b ciri -a Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: I266571686e452e2b7514afee42ff0a48f8891831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81684 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/include/soc/i2c_common.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved Elyes Haouas: Looks good to me, approved cong yang: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/common/include/soc/i2c_common.h b/src/soc/mediatek/common/include/soc/i2c_common.h index 4f4449c..63eef92 100644 --- a/src/soc/mediatek/common/include/soc/i2c_common.h +++ b/src/soc/mediatek/common/include/soc/i2c_common.h @@ -3,6 +3,7 @@ #ifndef MTK_COMMON_I2C_H #define MTK_COMMON_I2C_H +#include <commonlib/bsd/helpers.h> #include <device/i2c.h> /* I2C DMA Registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I266571686e452e2b7514afee42ff0a48f8891831 Gerrit-Change-Number: 81684 Gerrit-PatchSet: 2 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: drivers/mipi: Fine tune clock for BOE_NV110WUM_L60
by Felix Held (Code Review) 09 Apr '24

09 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81438?usp=email ) Change subject: drivers/mipi: Fine tune clock for BOE_NV110WUM_L60 ...................................................................... drivers/mipi: Fine tune clock for BOE_NV110WUM_L60 Fine tune the panel clock to prevent mipi noise from affecting wifi band. After tuning, the panel refresh rate keeps at 60Hz and wifi test passed. Just keep consistent with the Linux kernel panel driver panel-boe-tv101wum-nl6 [1] configuration. [1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/… BUG=b:330807136 TEST=fw screen display normally Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81438 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/drivers/mipi/panel-BOE_NV110WUM_L60.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: cong yang: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/drivers/mipi/panel-BOE_NV110WUM_L60.c b/src/drivers/mipi/panel-BOE_NV110WUM_L60.c index d30a1cf..029537b 100644 --- a/src/drivers/mipi/panel-BOE_NV110WUM_L60.c +++ b/src/drivers/mipi/panel-BOE_NV110WUM_L60.c @@ -9,10 +9,10 @@ .panel_bits_per_color = 8, .panel_bits_per_pixel = 24, .mode = { - .pixel_clock = 162760, + .pixel_clock = 166400, .lvds_dual_channel = 0, .refresh = 60, - .ha = 1200, .hbl = 120, .hso = 50, .hspw = 20, + .ha = 1200, .hbl = 150, .hso = 65, .hspw = 20, .va = 1920, .vbl = 135, .vso = 115, .vspw = 8, .phsync = '-', .pvsync = '-', .x_mm = 147, .y_mm = 235, -- To view, visit https://review.coreboot.org/c/coreboot/+/81438?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic44c86f062d4e836f403ee97f2fc6370fff02797 Gerrit-Change-Number: 81438 Gerrit-PatchSet: 8 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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