Jianeng Ceng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81786?usp=email )
Change subject: drivers/i2c/rt5645: Add i2c_acpi_write_gpio for public
......................................................................
drivers/i2c/rt5645: Add i2c_acpi_write_gpio for public
Add the function i2c_acpi_write_gpio to write gpio for acpi device.
Make sure it can be use for other driver.
BUG=None
TEST= Build BIOS FW pass and it can be use for other driver.
Change-Id: Ie4d2a0bf0506cd9a5f3859eeb3c568bbecd429b5
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
M src/drivers/i2c/rt5645/rt5645.c
M src/include/acpi/acpi_device.h
2 files changed, 7 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81786/1
diff --git a/src/drivers/i2c/rt5645/rt5645.c b/src/drivers/i2c/rt5645/rt5645.c
index f800173..9c4ee96 100644
--- a/src/drivers/i2c/rt5645/rt5645.c
+++ b/src/drivers/i2c/rt5645/rt5645.c
@@ -11,7 +11,7 @@
#define RT5645_DP_INT(key, val) \
acpi_dp_add_integer(dp, "realtek," key, (val))
-static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index)
+int i2c_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index)
{
int ret = -1;
@@ -66,15 +66,15 @@
/* Use either Interrupt() or GpioInt() */
if (config->irq_gpio.pin_count)
- irq_gpio_index = i2c_generic_write_gpio(&config->irq_gpio,
+ irq_gpio_index = i2c_acpi_write_gpio(&config->irq_gpio,
&curr_index);
else
acpi_device_write_interrupt(&config->irq);
/* Add I2C GPIO index */
- cbj_sleeve_index = i2c_generic_write_gpio(&config->cbj_sleeve,
+ cbj_sleeve_index = i2c_acpi_write_gpio(&config->cbj_sleeve,
&curr_index);
- hp_detect_index = i2c_generic_write_gpio(&config->hp_detect,
+ hp_detect_index = i2c_acpi_write_gpio(&config->hp_detect,
&curr_index);
acpigen_write_resourcetemplate_footer();
diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h
index 9ce5e0a..58cb5c2 100644
--- a/src/include/acpi/acpi_device.h
+++ b/src/include/acpi/acpi_device.h
@@ -313,6 +313,9 @@
/* Write I2cSerialBus() descriptor to SSDT AML output */
void acpi_device_write_i2c(const struct acpi_i2c *i2c);
+/* Write I2C GPIO for acpi device */
+int i2c_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index);
+
/*
* ACPI SPI Bus
*/
--
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email )
Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/intel/beechnutcity_crb/romstage.c:
https://review.coreboot.org/c/coreboot/+/81322/comment/53b515d6_4695a694 :
PS11, Line 21: /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */
: mupd->FspmConfig.BiosRegionBase = FMAP_SECTION_SI_ALL_START + FMAP_SECTION_SI_ALL_SIZE;
: mupd->FspmConfig.BiosRegionSize = FMAP_SECTION_FLASH_SIZE - FMAP_SECTION_SI_ALL_SIZE;
> This is not mainboard specific. […]
Sure, updated.
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Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
......................................................................
mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
---
A configs/builder/config.intel.crb.bnc
A src/mainboard/intel/beechnutcity_crb/Kconfig
A src/mainboard/intel/beechnutcity_crb/Kconfig.name
A src/mainboard/intel/beechnutcity_crb/Makefile.mk
A src/mainboard/intel/beechnutcity_crb/board.fmd
A src/mainboard/intel/beechnutcity_crb/board_info.txt
A src/mainboard/intel/beechnutcity_crb/bootblock.c
A src/mainboard/intel/beechnutcity_crb/devicetree.cb
A src/mainboard/intel/beechnutcity_crb/dsdt.asl
A src/mainboard/intel/beechnutcity_crb/include/config/iio.h
A src/mainboard/intel/beechnutcity_crb/ramstage.c
A src/mainboard/intel/beechnutcity_crb/romstage.c
12 files changed, 286 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/12
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Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
......................................................................
mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
A configs/builder/config.intel.crb.avc
A src/mainboard/intel/avenuecity_crb/Kconfig
A src/mainboard/intel/avenuecity_crb/Kconfig.name
A src/mainboard/intel/avenuecity_crb/Makefile.mk
A src/mainboard/intel/avenuecity_crb/board.fmd
A src/mainboard/intel/avenuecity_crb/board_info.txt
A src/mainboard/intel/avenuecity_crb/bootblock.c
A src/mainboard/intel/avenuecity_crb/devicetree.cb
A src/mainboard/intel/avenuecity_crb/dsdt.asl
A src/mainboard/intel/avenuecity_crb/include/config/iio.h
A src/mainboard/intel/avenuecity_crb/ramstage.c
A src/mainboard/intel/avenuecity_crb/romstage.c
12 files changed, 289 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/31
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Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils
......................................................................
soc/intel/xeon_sp/gnr: Add IIO config utils
GraniteRapids boards should use _IIO_PE_CFG_STRUCT_BEGIN() to
define IIO configurations and invokes soc_config_iio() to apply
the settings.
Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/include/soc/iio.h
A src/soc/intel/xeon_sp/gnr/soc_iio.c
3 files changed, 186 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/31
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Jianeng Ceng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81773?usp=email )
Change subject: drivers/i2c/rt5645: Add RT5645 amp driver
......................................................................
Patch Set 4:
(1 comment)
File src/drivers/i2c/rt5645/rt5645.c:
https://review.coreboot.org/c/coreboot/+/81773/comment/9d41914a_c3d17b63 :
PS4, Line 14: static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index)
> We may want to export https://source.chromium. […]
Okay, I will commit another CL to export this for other driver use.
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Change subject: mb/google/*: Drop unused header file console/console.h
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> @ruihai, do you want to take the chance to drop `console/console.h` in […]
please see https://review.coreboot.org/c/coreboot/+/81811
Thx
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