coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: nb/haswell: Fully disable iGPU when dGPU is used
by Angel Pons (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Leah Rowe, Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81644?usp=email ) Change subject: nb/haswell: Fully disable iGPU when dGPU is used ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81644/comment/d0461f6f_7d27d7c2 : PS1, Line 9: My earlier patch It's hard to know what "my earlier patch" refers to without reading the rest of the commit message first. So, I would preface the commit message with something like: > This commit brings some parts of commit 1e2821882f (nb/haswell: Disable iGPU when dGPU is used) that were lost during review. I'm not too inspired today, feel free to reword. https://review.coreboot.org/c/coreboot/+/81644/comment/38b5dcbd_02762878 : PS1, Line 11: you also need to disable the iGPU entirely. > What do you mean by 'need to' ? Also a dGPU does not need to be on the PEG slot and probably works f […] Without this patch, what happens on a system with both an iGPU and a dGPU? https://review.coreboot.org/c/coreboot/+/81644/comment/611badf3_1c02676f : PS1, Line 18: For more context, see: : : Author: Leah Rowe <info(a)minifree.org> : Date: Fri Feb 23 13:33:31 2024 +0000 : : nb/haswell: Disable iGPU when dGPU is used : : And now, look at the Gerrit comments for explanation: : : https://review.coreboot.org/c/coreboot/+/80717/ Please use commit hashes to reference stuff. I can't find a specific recommendation in the docs, but I think shortening hashes to the first 10 characters is OK. If not, I think the bot will complain. > For more context, see commit 1e2821882f (nb/haswell: Disable iGPU when dGPU is used) and its review on Gerrit. Notice how Gerrit highlights the commit part as a link? It's automatic 😊 https://review.coreboot.org/c/coreboot/+/81644/comment/484316e1_2beff0db : PS1, Line 30: This patch fixes the issue. I tested on iGPU and dGPU, with both : broadwell and haswell mrc.bin. Please make sure that, when `CONFIG_ONBOARD_VGA_IS_PRIMARY=y` (used for Optimus setups): - The iGPU is enabled and primary - The dGPU is enabled Even if the OptiPlex 9020 SFF is not an Optimus-enabled system, setting `CONFIG_ONBOARD_VGA_IS_PRIMARY=y` should still result in the same behaviour. Patchset: PS1: I would earnestly appreciate a thorough description of the issue you're encountering. File src/northbridge/intel/haswell/gma.c: https://review.coreboot.org/c/coreboot/+/81644/comment/c1455e10_3c952c48 : PS1, Line 469: Required > It works when it's disabled? That might need additional context. Please elaborate on "doesn't work". -- To view, visit https://review.coreboot.org/c/coreboot/+/81644?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I944123d41ba0e69d74de424e655de33691089c85 Gerrit-Change-Number: 81644 Gerrit-PatchSet: 1 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 11:40:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/i2c/rt5645: Add i2c_acpi_write_gpio for public
by Jianeng Ceng (Code Review) 09 Apr '24

09 Apr '24

Jianeng Ceng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81786?usp=email ) Change subject: drivers/i2c/rt5645: Add i2c_acpi_write_gpio for public ...................................................................... drivers/i2c/rt5645: Add i2c_acpi_write_gpio for public Add the function i2c_acpi_write_gpio to write gpio for acpi device. Make sure it can be use for other driver. BUG=None TEST= Build BIOS FW pass and it can be use for other driver. Change-Id: Ie4d2a0bf0506cd9a5f3859eeb3c568bbecd429b5 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/drivers/i2c/rt5645/rt5645.c M src/include/acpi/acpi_device.h 2 files changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/81786/1 diff --git a/src/drivers/i2c/rt5645/rt5645.c b/src/drivers/i2c/rt5645/rt5645.c index f800173..9c4ee96 100644 --- a/src/drivers/i2c/rt5645/rt5645.c +++ b/src/drivers/i2c/rt5645/rt5645.c @@ -11,7 +11,7 @@ #define RT5645_DP_INT(key, val) \ acpi_dp_add_integer(dp, "realtek," key, (val)) -static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index) +int i2c_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index) { int ret = -1; @@ -66,15 +66,15 @@ /* Use either Interrupt() or GpioInt() */ if (config->irq_gpio.pin_count) - irq_gpio_index = i2c_generic_write_gpio(&config->irq_gpio, + irq_gpio_index = i2c_acpi_write_gpio(&config->irq_gpio, &curr_index); else acpi_device_write_interrupt(&config->irq); /* Add I2C GPIO index */ - cbj_sleeve_index = i2c_generic_write_gpio(&config->cbj_sleeve, + cbj_sleeve_index = i2c_acpi_write_gpio(&config->cbj_sleeve, &curr_index); - hp_detect_index = i2c_generic_write_gpio(&config->hp_detect, + hp_detect_index = i2c_acpi_write_gpio(&config->hp_detect, &curr_index); acpigen_write_resourcetemplate_footer(); diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 9ce5e0a..58cb5c2 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -313,6 +313,9 @@ /* Write I2cSerialBus() descriptor to SSDT AML output */ void acpi_device_write_i2c(const struct acpi_i2c *i2c); +/* Write I2C GPIO for acpi device */ +int i2c_acpi_write_gpio(struct acpi_gpio *gpio, int *curr_index); + /* * ACPI SPI Bus */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4d2a0bf0506cd9a5f3859eeb3c568bbecd429b5 Gerrit-Change-Number: 81786 Gerrit-PatchSet: 1 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, TangYiwei. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81322?usp=email ) Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City ...................................................................... Patch Set 12: (1 comment) File src/mainboard/intel/beechnutcity_crb/romstage.c: https://review.coreboot.org/c/coreboot/+/81322/comment/53b515d6_4695a694 : PS11, Line 21: /* Set BIOS regeion UPD, otherwise MTRR might set incorrectly during TempRamExit API */ : mupd->FspmConfig.BiosRegionBase = FMAP_SECTION_SI_ALL_START + FMAP_SECTION_SI_ALL_SIZE; : mupd->FspmConfig.BiosRegionSize = FMAP_SECTION_FLASH_SIZE - FMAP_SECTION_SI_ALL_SIZE; > This is not mainboard specific. […] Sure, updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/81322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Gerrit-Change-Number: 81322 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Tue, 09 Apr 2024 11:39:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, TangYiwei. Hello Arthur Heymans, Chen, Gang C, David Hendricks, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81322?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City ...................................................................... mb/intel/beechnutcity_crb: Add GNR/SRF-SP 2S server board Beechnut City Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP SP SoCs (Granite Rapids SP and Sierra Forest SP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> --- A configs/builder/config.intel.crb.bnc A src/mainboard/intel/beechnutcity_crb/Kconfig A src/mainboard/intel/beechnutcity_crb/Kconfig.name A src/mainboard/intel/beechnutcity_crb/Makefile.mk A src/mainboard/intel/beechnutcity_crb/board.fmd A src/mainboard/intel/beechnutcity_crb/board_info.txt A src/mainboard/intel/beechnutcity_crb/bootblock.c A src/mainboard/intel/beechnutcity_crb/devicetree.cb A src/mainboard/intel/beechnutcity_crb/dsdt.asl A src/mainboard/intel/beechnutcity_crb/include/config/iio.h A src/mainboard/intel/beechnutcity_crb/ramstage.c A src/mainboard/intel/beechnutcity_crb/romstage.c 12 files changed, 286 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81322/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/81322?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a Gerrit-Change-Number: 81322 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[L] Change in coreboot[main]: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Nicholas Chin, Patrick Rudolph, Paul Menzel, TangYiwei, Varshit Pandya. Hello Arthur Heymans, Chen, Gang C, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Varshit Pandya, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81319?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City ...................................................................... mb/intel/avenuecity_crb: Add 2S GNR/SRF-AP server board Avenue City Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP AP SoCs (Granite Rapids AP and Sierra Forest AP). This patch initially sets the code set up as a compilation target with GNR N-1 FSP, and with basic feature supports (Integrated IO Controller (IIO) configuration, BMC, UART, HPET). Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- A configs/builder/config.intel.crb.avc A src/mainboard/intel/avenuecity_crb/Kconfig A src/mainboard/intel/avenuecity_crb/Kconfig.name A src/mainboard/intel/avenuecity_crb/Makefile.mk A src/mainboard/intel/avenuecity_crb/board.fmd A src/mainboard/intel/avenuecity_crb/board_info.txt A src/mainboard/intel/avenuecity_crb/bootblock.c A src/mainboard/intel/avenuecity_crb/devicetree.cb A src/mainboard/intel/avenuecity_crb/dsdt.asl A src/mainboard/intel/avenuecity_crb/include/config/iio.h A src/mainboard/intel/avenuecity_crb/ramstage.c A src/mainboard/intel/avenuecity_crb/romstage.c 12 files changed, 289 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81319/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/81319?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46 Gerrit-Change-Number: 81319 Gerrit-PatchSet: 31 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Attention: TangYiwei Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81318?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... soc/intel/xeon_sp/gnr: Add IIO config utils GraniteRapids boards should use _IIO_PE_CFG_STRUCT_BEGIN() to define IIO configurations and invokes soc_config_iio() to apply the settings. Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/include/soc/iio.h A src/soc/intel/xeon_sp/gnr/soc_iio.c 3 files changed, 186 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 31 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP
by Angel Pons (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Benjamin Doron, Dinesh Gehlot, Kapil Porwal, Nick Vaccaro. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81803?usp=email ) Change subject: soc/intel/alderlake: Support missing CLKREQ workaround on RaptorLake FSP ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81803?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I583a4b257b72f992fdb6390d00e187d04a749177 Gerrit-Change-Number: 81803 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 09 Apr 2024 11:34:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[4.11_branch]: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB
by Werner Zeh (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Angel Pons. Hello build bot (Jenkins), Angel Pons, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81785?usp=email to review the following change. Change subject: Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB ...................................................................... Makefile.inc: Decrease minimal pagesize from 4 kB to 1 kB GCC 12 incorrectly warns about an array out of bounds issue: ``` $ make V=1 # emulation/qemu-i440fx […] CC ramstage/arch/x86/ebda.o x86_64-linux-gnu-gcc-12 -MMD -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -Ibuild -I3rdparty/vboot/firmware/include -include src/include/kconfig.h -include src/include/rules.h -include src/commonlib/bsd/include/commonlib/bsd/compiler.h -I3rdparty -D__BUILD_DIR__=\"build\" -Isrc/arch/x86/include -D__ARCH_x86_32__ -pipe -g -nostdinc -std=gnu11 -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -Wshadow -Wdate-time -Wtype-limits -Wvla -Wdangling-else -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie -Wno-packed-not-aligned -fconserve-stack -Wnull-dereference -Wreturn-type -Wlogical-op -Wduplicated-cond -Wno-unused-but-set-variable -Werror -Os -Wno-address-of-packed-member -m32 -Wl,-b,elf32-i386 -Wl,-melf_i386 -m32 -fuse-ld=bfd -fno-stack-protector -Wl,--build-id=none -fno-delete-null-pointer-checks -Wlogical-op -march=i686 -mno-mmx -MT build/ramstage/arch/x86/ebda.o -D__RAMSTAGE__ -c -o build/ramstage/arch/x86/ebda.o src/arch/x86/ebda.c In file included from src/arch/x86/ebda.c:6: In function 'write_ble8', inlined from 'write_le8' at src/commonlib/include/commonlib/endian.h:155:2, inlined from 'write_le16' at src/commonlib/include/commonlib/endian.h:178:2, inlined from 'setup_ebda' at src/arch/x86/ebda.c:35:2, inlined from 'setup_default_ebda' at src/arch/x86/ebda.c:48:2: src/commonlib/include/commonlib/endian.h:27:26: error: array subscript 0 is outside array bounds of 'void[0]' [-Werror=array-bounds] 27 | *(uint8_t *)dest = val; | ~~~~~~~~~~~~~~~~~^~~~~ […] ``` [In GCC 12 the new parameter `min-pagesize` is added and defaults 4 kB.][1] It treats INTEGER_CST addresses smaller than that as assumed results of pointer arithmetics from NULL while addresses equal or larger than that as expected user constant addresses. For GCC 13 we can represent results from pointer arithmetics on NULL using &MEM[(void*)0 + offset] instead of (void*)offset INTEGER_CSTs. [1]: https://web.archive.org/web/20220711061810/https://gcc.gnu.org/bugzilla/sho… TEST=No compile error with gcc (Debian 12.2.0-3) 12.2.0 Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62830 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/xcompile/xcompile 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/81785/1 diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 2d3da1e..1327324 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -184,7 +184,8 @@ CFLAGS_GCC="$CFLAGS_GCC -fno-stack-protector" testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" - + testcc "$GCC" "$CFLAGS_GCC --param=min-pagesize=1024 $FLAGS_GCC" && + CFLAGS_GCC="$CFLAGS_GCC --param=min-pagesize=1024" case "$architecture" in x86) ;; -- To view, visit https://review.coreboot.org/c/coreboot/+/81785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I6e36633f42cb4dc5af53212c10c919a86e451ee0 Gerrit-Change-Number: 81785 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: drivers/i2c/rt5645: Add RT5645 amp driver
by Jianeng Ceng (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Dolan Liu, Eric Lai, Subrata Banik. Jianeng Ceng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81773?usp=email ) Change subject: drivers/i2c/rt5645: Add RT5645 amp driver ...................................................................... Patch Set 4: (1 comment) File src/drivers/i2c/rt5645/rt5645.c: https://review.coreboot.org/c/coreboot/+/81773/comment/9d41914a_c3d17b63 : PS4, Line 14: static int i2c_generic_write_gpio(struct acpi_gpio *gpio, int *curr_index) > We may want to export https://source.chromium. […] Okay, I will commit another CL to export this for other driver use. -- To view, visit https://review.coreboot.org/c/coreboot/+/81773?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I602fcc4dd8576043943f6e20884edc4703350320 Gerrit-Change-Number: 81773 Gerrit-PatchSet: 4 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 11:26:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tree: Drop unused <delay.h>
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81812?usp=email ) Change subject: tree: Drop unused <delay.h> ...................................................................... tree: Drop unused <delay.h> Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/spi/issi.c M src/ec/clevo/it5570e/commands.c M src/mainboard/google/cherry/mainboard.c M src/mainboard/purism/librem_jsl/bootblock.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/native_raminit/raminit_main.c M src/northbridge/intel/haswell/native_raminit/raminit_native.c M src/soc/intel/alderlake/systemagent.c M src/soc/intel/meteorlake/finalize.c M src/soc/intel/meteorlake/systemagent.c M src/soc/mediatek/mt8195/pcie.c M src/soc/qualcomm/common/display/mdss.c M src/soc/qualcomm/sc7280/display/edp_aux.c M src/soc/qualcomm/sc7280/display/edp_phy_7nm.c M src/soc/sifive/fu740/gpio.c M src/soc/sifive/fu740/spi.c 16 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81812/1 diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c index 884fcdb..f6ccc5e 100644 --- a/src/drivers/spi/issi.c +++ b/src/drivers/spi/issi.c @@ -3,7 +3,6 @@ #include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> -#include <delay.h> #include "spi_flash_internal.h" diff --git a/src/ec/clevo/it5570e/commands.c b/src/ec/clevo/it5570e/commands.c index 7a85b8f..8f53bb1 100644 --- a/src/ec/clevo/it5570e/commands.c +++ b/src/ec/clevo/it5570e/commands.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <ec/acpi/ec.h> #include <swab.h> diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 0e78f62..19638c9 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -3,7 +3,6 @@ #include <boardid.h> #include <bootmode.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/mmio.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/purism/librem_jsl/bootblock.c b/src/mainboard/purism/librem_jsl/bootblock.c index e97fc4d..e0f480e 100644 --- a/src/mainboard/purism/librem_jsl/bootblock.c +++ b/src/mainboard/purism/librem_jsl/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <delay.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> #include <gpio.h> diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c index 5264d48..2e3a97b 100644 --- a/src/northbridge/intel/gm45/thermal.c +++ b/src/northbridge/intel/gm45/thermal.c @@ -4,7 +4,6 @@ #include <device/pci_def.h> #include <spd.h> -#include "delay.h" #include "gm45.h" void raminit_thermal(const sysinfo_t *sysinfo) diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c index b06330c..19ec585 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c @@ -3,7 +3,6 @@ #include <assert.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> -#include <delay.h> #include <device/pci_ops.h> #include <northbridge/intel/haswell/chip.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c index ffb5e82..2fed93d 100644 --- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c +++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c @@ -6,7 +6,6 @@ #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/msr.h> -#include <delay.h> #include <device/pci_ops.h> #include <mrc_cache.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 3df23f2..a9c00a9 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -11,7 +11,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/power_limit.h> diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 06ea13cc..64beb85 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -4,7 +4,6 @@ #include <bootstate.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <device/pci.h> #include <gpio.h> #include <intelblocks/cse.h> diff --git a/src/soc/intel/meteorlake/systemagent.c b/src/soc/intel/meteorlake/systemagent.c index 6b445af..774a99f 100644 --- a/src/soc/intel/meteorlake/systemagent.c +++ b/src/soc/intel/meteorlake/systemagent.c @@ -5,7 +5,6 @@ #include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/msr.h> #include <intelblocks/power_limit.h> diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index fa5bbd7..7f60d68 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <device/resource.h> -#include <delay.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/early_init.h> diff --git a/src/soc/qualcomm/common/display/mdss.c b/src/soc/qualcomm/common/display/mdss.c index 1ff923d..a1c13ee 100644 --- a/src/soc/qualcomm/common/display/mdss.c +++ b/src/soc/qualcomm/common/display/mdss.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <edid.h> #include <soc/clock.h> #include <soc/display/mdssreg.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_aux.c b/src/soc/qualcomm/sc7280/display/edp_aux.c index 2d2821b..a2dda39 100644 --- a/src/soc/qualcomm/sc7280/display/edp_aux.c +++ b/src/soc/qualcomm/sc7280/display/edp_aux.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <console/console.h> #include <edid.h> -#include <delay.h> #include <timer.h> #include <types.h> #include <string.h> diff --git a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c index eebb122..5074317 100644 --- a/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c +++ b/src/soc/qualcomm/sc7280/display/edp_phy_7nm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <edid.h> #include <soc/clock.h> diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index b9fe87e..d5576f2 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -4,7 +4,6 @@ #include <soc/gpio.h> #include <stdint.h> #include <arch/mmio.h> -#include <delay.h> #include <assert.h> #include <device/mmio.h> #include <gpio.h> diff --git a/src/soc/sifive/fu740/spi.c b/src/soc/sifive/fu740/spi.c index 908e6ca..415ba85 100644 --- a/src/soc/sifive/fu740/spi.c +++ b/src/soc/sifive/fu740/spi.c @@ -6,7 +6,6 @@ #include <soc/spi.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <delay.h> #include <lib.h> #include "spi_internal.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/81812?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I265e427254ce9f735e65b0631c43f98bc778a34f Gerrit-Change-Number: 81812 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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