coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: mb/google/*: Drop unused header file console/console.h
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Hung-Te Lin, Ruihai Zhou, Yidi Lin, Yu-Ping Wu. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81685?usp=email ) Change subject: mb/google/*: Drop unused header file console/console.h ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > @ruihai, do you want to take the chance to drop `console/console.h` in […] please see https://review.coreboot.org/c/coreboot/+/81811 Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/81685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3689afe532b63384b7905116c44c598e5fa13ee Gerrit-Change-Number: 81685 Gerrit-PatchSet: 1 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 10:54:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: tree: Drop unused <console/console.h>
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81811?usp=email ) Change subject: tree: Drop unused <console/console.h> ...................................................................... tree: Drop unused <console/console.h> Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/breakpoint.c M src/drivers/smmstore/ramstage.c M src/drivers/spi/issi.c M src/mainboard/bytedance/bd_egs/romstage.c M src/mainboard/emulation/qemu-riscv/cbmem.c M src/mainboard/google/auron/smihandler.c M src/mainboard/google/brya/variants/constitution/variant.c M src/mainboard/google/corsola/panel.c M src/mainboard/google/cyan/smihandler.c M src/mainboard/google/geralt/panel_geralt.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/guybrush/mainboard.c M src/mainboard/google/herobrine/boardid.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/link/smihandler.c M src/mainboard/google/myst/mainboard.c M src/mainboard/google/myst/port_descriptors.c M src/mainboard/google/rambi/smihandler.c M src/mainboard/google/rex/variants/ovis/gpio.c M src/mainboard/google/rex/variants/rex0/gpio.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/mainboard.c M src/mainboard/google/skyrim/variants/baseboard/smihandler.c M src/mainboard/google/slippy/smihandler.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/strago/smihandler.c M src/mainboard/msi/ms7d25/romstage_fsp_params.c M src/mainboard/msi/ms7e06/romstage_fsp_params.c M src/mainboard/purism/librem_jsl/bootblock.c M src/mainboard/purism/librem_jsl/romstage.c M src/mainboard/purism/librem_l1um_v2/romstage.c M src/mainboard/starlabs/lite/bootblock.c M src/mainboard/starlabs/lite/smbios.c M src/mainboard/starlabs/starbook/variants/kbl/romstage.c M src/northbridge/intel/haswell/early_pcie.c M src/northbridge/intel/sandybridge/common.c M src/soc/amd/common/vboot/vboot_bootblock.c M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/genoa_poc/i2c.c M src/soc/intel/common/block/p2sb/ioe_p2sb.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/meteorlake/pcie_rp.c M src/soc/intel/meteorlake/soc_info.c M src/soc/intel/xeon_sp/pch.c M src/soc/intel/xeon_sp/pmc.c M src/soc/intel/xeon_sp/pmutil.c M src/soc/mediatek/common/bl31.c M src/soc/mediatek/common/devapc.c M src/soc/mediatek/common/msdc.c M src/soc/mediatek/mt8186/pmif_spmi.c M src/soc/mediatek/mt8188/lastbus.c M src/soc/mediatek/mt8195/pcie.c M src/soc/sifive/fu740/clock.c M src/soc/sifive/fu740/gpio.c 55 files changed, 0 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81811/1 diff --git a/src/arch/x86/breakpoint.c b/src/arch/x86/breakpoint.c index d3ba783..be9359f 100644 --- a/src/arch/x86/breakpoint.c +++ b/src/arch/x86/breakpoint.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/registers.h> #include <arch/breakpoint.h> -#include <console/console.h> #include <types.h> #define DEBUG_REGISTER_COUNT 4 diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index e897aa2..857fe89 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -4,7 +4,6 @@ #include <cpu/x86/smm.h> #include <commonlib/helpers.h> #include <commonlib/region.h> -#include <console/console.h> #include <smm_call.h> #include <smmstore.h> #include <types.h> diff --git a/src/drivers/spi/issi.c b/src/drivers/spi/issi.c index d2000b9..884fcdb 100644 --- a/src/drivers/spi/issi.c +++ b/src/drivers/spi/issi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <commonlib/helpers.h> #include <spi_flash.h> #include <spi-generic.h> diff --git a/src/mainboard/bytedance/bd_egs/romstage.c b/src/mainboard/bytedance/bd_egs/romstage.c index f33e74e..e1e976b 100644 --- a/src/mainboard/bytedance/bd_egs/romstage.c +++ b/src/mainboard/bytedance/bd_egs/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> diff --git a/src/mainboard/emulation/qemu-riscv/cbmem.c b/src/mainboard/emulation/qemu-riscv/cbmem.c index 10ca2cd..e4d21cc 100644 --- a/src/mainboard/emulation/qemu-riscv/cbmem.c +++ b/src/mainboard/emulation/qemu-riscv/cbmem.c @@ -3,7 +3,6 @@ #include <cbmem.h> #include <symbols.h> #include <ramdetect.h> -#include <console/console.h> uintptr_t cbmem_top_chipset(void) { diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index 9f86abe..e20976c 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/google/brya/variants/constitution/variant.c b/src/mainboard/google/brya/variants/constitution/variant.c index 289481c..ca09253 100644 --- a/src/mainboard/google/brya/variants/constitution/variant.c +++ b/src/mainboard/google/brya/variants/constitution/variant.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <fw_config.h> #include <sar.h> diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c index 0eb9420..01eb243 100644 --- a/src/mainboard/google/corsola/panel.c +++ b/src/mainboard/google/corsola/panel.c @@ -2,7 +2,6 @@ #include <boardid.h> #include <cbfs.h> -#include <console/console.h> #include <device/i2c_simple.h> #include <edid.h> #include <gpio.h> diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 944d033..d0af1d4 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <device/mmio.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 0b59a4e..cd6dbe9 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/i2c.h> #include "gpio.h" diff --git a/src/mainboard/google/glados/smihandler.c b/src/mainboard/google/glados/smihandler.c index b1adb86..744d5d1 100644 --- a/src/mainboard/google/glados/smihandler.c +++ b/src/mainboard/google/glados/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variant.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <gpio.h> diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c index 18d5e8f..49a80e7 100644 --- a/src/mainboard/google/guybrush/mainboard.c +++ b/src/mainboard/google/guybrush/mainboard.c @@ -8,7 +8,6 @@ #include <amdblocks/psp.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/herobrine/boardid.c b/src/mainboard/google/herobrine/boardid.c index 38aeb20..79ed15a 100644 --- a/src/mainboard/google/herobrine/boardid.c +++ b/src/mainboard/google/herobrine/boardid.c @@ -4,7 +4,6 @@ #include <ec/google/chromeec/ec.h> #include "board.h" #include <commonlib/bsd/cb_err.h> -#include <console/console.h> #include <gpio.h> #include <soc/socinfo.h> diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 54666da..076d3fe 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <soc/pm.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> diff --git a/src/mainboard/google/link/smihandler.c b/src/mainboard/google/link/smihandler.c index 81972ff..b75bd4a 100644 --- a/src/mainboard/google/link/smihandler.c +++ b/src/mainboard/google/link/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/bd82x6x/me.h> diff --git a/src/mainboard/google/myst/mainboard.c b/src/mainboard/google/myst/mainboard.c index e5d2858..57bfcd4 100644 --- a/src/mainboard/google/myst/mainboard.c +++ b/src/mainboard/google/myst/mainboard.c @@ -5,7 +5,6 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/myst/port_descriptors.c b/src/mainboard/google/myst/port_descriptors.c index 664b440..323f039 100644 --- a/src/mainboard/google/myst/port_descriptors.c +++ b/src/mainboard/google/myst/port_descriptors.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <baseboard/variants.h> -#include <console/console.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> diff --git a/src/mainboard/google/rambi/smihandler.c b/src/mainboard/google/rambi/smihandler.c index 6f652ed..30f704c 100644 --- a/src/mainboard/google/rambi/smihandler.c +++ b/src/mainboard/google/rambi/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/rex/variants/ovis/gpio.c b/src/mainboard/google/rex/variants/ovis/gpio.c index f188929..5624df9 100644 --- a/src/mainboard/google/rex/variants/ovis/gpio.c +++ b/src/mainboard/google/rex/variants/ovis/gpio.c @@ -10,7 +10,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> -#include <console/console.h> #include <boardid.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 4ccf327..9d8f9ff 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -10,7 +10,6 @@ #include <baseboard/gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> -#include <console/console.h> #include <boardid.h> /* Pad configuration in ramstage */ diff --git a/src/mainboard/google/skyrim/ec.c b/src/mainboard/google/skyrim/ec.c index f265cbf..060119d 100644 --- a/src/mainboard/google/skyrim/ec.c +++ b/src/mainboard/google/skyrim/ec.c @@ -2,7 +2,6 @@ #include <acpi/acpi.h> #include <amdblocks/smi.h> -#include <console/console.h> #include <ec/google/chromeec/ec.h> #include <gpio.h> #include <soc/smi.h> diff --git a/src/mainboard/google/skyrim/mainboard.c b/src/mainboard/google/skyrim/mainboard.c index 8a395a8..5925f29 100644 --- a/src/mainboard/google/skyrim/mainboard.c +++ b/src/mainboard/google/skyrim/mainboard.c @@ -6,7 +6,6 @@ #include <amdblocks/psp.h> #include <amdblocks/xhci.h> #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <device/device.h> #include <drivers/i2c/tpm/chip.h> diff --git a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c index ff59b2b..a14dc98 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/smihandler.c +++ b/src/mainboard/google/skyrim/variants/baseboard/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <baseboard/variants.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index 43c2bf4..cefaf7a 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c index 4e9524d..803056a 100644 --- a/src/mainboard/intel/kblrvp/smihandler.c +++ b/src/mainboard/intel/kblrvp/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 58c7dfb..b53d369 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <cpu/x86/smm.h> #include <ec/google/chromeec/smm.h> #include <soc/iomap.h> diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index d592fdc..3f3a81b 100644 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <console/console.h> #include <cpu/x86/smm.h> #include "ec.h" diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 3ced7f8..7f5ea85 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> diff --git a/src/mainboard/msi/ms7e06/romstage_fsp_params.c b/src/mainboard/msi/ms7e06/romstage_fsp_params.c index d3c3c50..6fa8dc3 100644 --- a/src/mainboard/msi/ms7e06/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7e06/romstage_fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> #include <soc/meminit.h> diff --git a/src/mainboard/purism/librem_jsl/bootblock.c b/src/mainboard/purism/librem_jsl/bootblock.c index c629a6d..e97fc4d 100644 --- a/src/mainboard/purism/librem_jsl/bootblock.c +++ b/src/mainboard/purism/librem_jsl/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <delay.h> #include <device/pci_ops.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/purism/librem_jsl/romstage.c b/src/mainboard/purism/librem_jsl/romstage.c index 65205ad..e516457 100644 --- a/src/mainboard/purism/librem_jsl/romstage.c +++ b/src/mainboard/purism/librem_jsl/romstage.c @@ -5,7 +5,6 @@ #include <soc/meminit.h> #include <soc/romstage.h> #include <device/pci_ops.h> -#include <console/console.h> static const struct mb_cfg board_mem_cfg = { .dq_map[DDR_CH0] = { diff --git a/src/mainboard/purism/librem_l1um_v2/romstage.c b/src/mainboard/purism/librem_l1um_v2/romstage.c index 6cceba3..666adc2 100644 --- a/src/mainboard/purism/librem_l1um_v2/romstage.c +++ b/src/mainboard/purism/librem_l1um_v2/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/mainboard/starlabs/lite/bootblock.c b/src/mainboard/starlabs/lite/bootblock.c index 6bf1723..91e2e23 100644 --- a/src/mainboard/starlabs/lite/bootblock.c +++ b/src/mainboard/starlabs/lite/bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <intelblocks/lpc_lib.h> #include <soc/gpio.h> #include <variants.h> diff --git a/src/mainboard/starlabs/lite/smbios.c b/src/mainboard/starlabs/lite/smbios.c index d9ae270..5b85f50 100644 --- a/src/mainboard/starlabs/lite/smbios.c +++ b/src/mainboard/starlabs/lite/smbios.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <ec/starlabs/merlin/ec.h> diff --git a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c index 72fe9ed..d1e928e 100644 --- a/src/mainboard/starlabs/starbook/variants/kbl/romstage.c +++ b/src/mainboard/starlabs/starbook/variants/kbl/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <option.h> #include <soc/romstage.h> #include <spd_bin.h> diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c index d3940e3..3fc8713 100644 --- a/src/northbridge/intel/haswell/early_pcie.c +++ b/src/northbridge/intel/haswell/early_pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <console/console.h> #include <device/pci_def.h> #include <device/pci_mmio_cfg.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/sandybridge/common.c b/src/northbridge/intel/sandybridge/common.c index a670491..0ee7e1d 100644 --- a/src/northbridge/intel/sandybridge/common.c +++ b/src/northbridge/intel/sandybridge/common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/soc/amd/common/vboot/vboot_bootblock.c b/src/soc/amd/common/vboot/vboot_bootblock.c index 6a7ae13..7eeecb5 100644 --- a/src/soc/amd/common/vboot/vboot_bootblock.c +++ b/src/soc/amd/common/vboot/vboot_bootblock.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> -#include <console/console.h> #include <cpu/x86/tsc.h> #include <psp_verstage/psp_transfer.h> #include <symbols.h> diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index 8f842f9..fc22304 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -7,7 +7,6 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/cpu.h> #include <arch/ioapic.h> -#include <console/console.h> #include <device/device.h> #include <vendorcode/amd/opensil/genoa_poc/opensil.h> diff --git a/src/soc/amd/genoa_poc/i2c.c b/src/soc/amd/genoa_poc/i2c.c index 7261a87..aac73f0 100644 --- a/src/soc/amd/genoa_poc/i2c.c +++ b/src/soc/amd/genoa_poc/i2c.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/i2c.h> -#include <console/console.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include "chip.h" diff --git a/src/soc/intel/common/block/p2sb/ioe_p2sb.c b/src/soc/intel/common/block/p2sb/ioe_p2sb.c index 41b815b..769b853 100644 --- a/src/soc/intel/common/block/p2sb/ioe_p2sb.c +++ b/src/soc/intel/common/block/p2sb/ioe_p2sb.c @@ -2,7 +2,6 @@ #define __SIMPLE_DEVICE__ -#include <console/console.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/p2sb.h> diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 04318c8..e348501 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -3,7 +3,6 @@ #define __SIMPLE_DEVICE__ #include <device/pci_ops.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 1b4045e..9f59ce1 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -4,7 +4,6 @@ #include <soc/pci_devs.h> #include <soc/pcie.h> #include <soc/soc_info.h> -#include <console/console.h> static const struct pcie_rp_group mtlp_rp_groups[] = { { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 }, diff --git a/src/soc/intel/meteorlake/soc_info.c b/src/soc/intel/meteorlake/soc_info.c index 0772c7799..275d568 100644 --- a/src/soc/intel/meteorlake/soc_info.c +++ b/src/soc/intel/meteorlake/soc_info.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <soc/soc_info.h> #include <intelblocks/tcss.h> -#include <console/console.h> uint8_t get_max_usb20_port(void) { diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c index 23af6d9..5f480d6 100644 --- a/src/soc/intel/xeon_sp/pch.c +++ b/src/soc/intel/xeon_sp/pch.c @@ -9,7 +9,6 @@ #include <soc/bootblock.h> #include <soc/pch.h> #include <soc/pmc.h> -#include <console/console.h> void override_hpet_ioapic_bdf(void) { diff --git a/src/soc/intel/xeon_sp/pmc.c b/src/soc/intel/xeon_sp/pmc.c index 4321625..6a784e0 100644 --- a/src/soc/intel/xeon_sp/pmc.c +++ b/src/soc/intel/xeon_sp/pmc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/device.h> #include <device/pci_ops.h> #include <intelblocks/pmc.h> diff --git a/src/soc/intel/xeon_sp/pmutil.c b/src/soc/intel/xeon_sp/pmutil.c index 336e867..0d77a2a 100644 --- a/src/soc/intel/xeon_sp/pmutil.c +++ b/src/soc/intel/xeon_sp/pmutil.c @@ -7,7 +7,6 @@ #define __SIMPLE_DEVICE__ -#include <console/console.h> #include <device/pci.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/mediatek/common/bl31.c b/src/soc/mediatek/common/bl31.c index 6a79098..e6e5bbc 100644 --- a/src/soc/mediatek/common/bl31.c +++ b/src/soc/mediatek/common/bl31.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bl31.h> -#include <console/console.h> #include <gpio.h> #include <soc/bl31.h> diff --git a/src/soc/mediatek/common/devapc.c b/src/soc/mediatek/common/devapc.c index 7838d7d..5873dd5 100644 --- a/src/soc/mediatek/common/devapc.c +++ b/src/soc/mediatek/common/devapc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <console/console.h> #include <soc/devapc.h> #include <soc/devapc_common.h> diff --git a/src/soc/mediatek/common/msdc.c b/src/soc/mediatek/common/msdc.c index e7cd571..df59b0e 100644 --- a/src/soc/mediatek/common/msdc.c +++ b/src/soc/mediatek/common/msdc.c @@ -5,7 +5,6 @@ #include <assert.h> #include <commonlib/bsd/helpers.h> #include <commonlib/storage/sd_mmc.h> -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <lib.h> diff --git a/src/soc/mediatek/mt8186/pmif_spmi.c b/src/soc/mediatek/mt8186/pmif_spmi.c index 28ea739..614985b 100644 --- a/src/soc/mediatek/mt8186/pmif_spmi.c +++ b/src/soc/mediatek/mt8186/pmif_spmi.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <soc/pll.h> #include <soc/pmif_spmi.h> -#include <console/console.h> /* IOCFG_LT, DRV_CFG2 */ DEFINE_BITFIELD(SPMI_SCL, 14, 12) diff --git a/src/soc/mediatek/mt8188/lastbus.c b/src/soc/mediatek/mt8188/lastbus.c index 5d117af..8bf6a87 100644 --- a/src/soc/mediatek/mt8188/lastbus.c +++ b/src/soc/mediatek/mt8188/lastbus.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/lastbus_v2.h> diff --git a/src/soc/mediatek/mt8195/pcie.c b/src/soc/mediatek/mt8195/pcie.c index cb36f8d..fa5bbd7 100644 --- a/src/soc/mediatek/mt8195/pcie.c +++ b/src/soc/mediatek/mt8195/pcie.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ -#include <console/console.h> #include <device/mmio.h> #include <device/resource.h> #include <delay.h> diff --git a/src/soc/sifive/fu740/clock.c b/src/soc/sifive/fu740/clock.c index 419a0e2..91e7992 100644 --- a/src/soc/sifive/fu740/clock.c +++ b/src/soc/sifive/fu740/clock.c @@ -3,7 +3,6 @@ // This file is used for setting up clocks and get devices out of reset // For more Information see FU740-C000 Manual Chapter 7 Clocking and Reset -#include <console/console.h> #include <delay.h> #include <device/mmio.h> #include <soc/addressmap.h> diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index 167844d..b9fe87e 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> #include <soc/addressmap.h> #include <soc/gpio.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/81811?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1a8fc50217c84e835080c70269ff50fc001392c Gerrit-Change-Number: 81811 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: southbridge/intel/common/acpi: Update sleepstates.asl
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Shuo Liu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81784?usp=email ) Change subject: southbridge/intel/common/acpi: Update sleepstates.asl ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Gerrit-Change-Number: 81784 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: southbridge/intel/common/acpi: Update sleepstates.asl
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81784?usp=email ) Change subject: southbridge/intel/common/acpi: Update sleepstates.asl ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/common/acpi/sleepstates.asl: https://review.coreboot.org/c/coreboot/+/81784/comment/831cc0bb_ff30a901 : PS1, Line 4: XEON_SP_COMMON_BASE > This is not needed. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Gerrit-Change-Number: 81784 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 09 Apr 2024 10:45:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: tree: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Angel Pons, Christian Walter, Felix Held, Julius Werner, Maxim, Michał Żygowski, Philipp Hug, Piotr Król, Sean Rhodes, Uwe Poeche, Werner Zeh, ron minnich. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81455?usp=email ) Change subject: tree: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 2: (1 comment) File util/intelp2m/parser/parser.go: https://review.coreboot.org/c/coreboot/+/81455/comment/efdb4921_8becf0f0 : PS2, Line 54: if !strings.Contains(info.function, "GPIO Community 0") { > this is likely unrelated this is to avoid having that blank line in generated file -- To view, visit https://review.coreboot.org/c/coreboot/+/81455?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46a362270f69d0a4a28e5bb9c954f34d632815ff Gerrit-Change-Number: 81455 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 09 Apr 2024 10:37:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: southbridge/intel/common/acpi: Update sleepstates.asl
by Arthur Heymans (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Shuo Liu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81784?usp=email ) Change subject: southbridge/intel/common/acpi: Update sleepstates.asl ...................................................................... Patch Set 1: Code-Review-1 (1 comment) File src/southbridge/intel/common/acpi/sleepstates.asl: https://review.coreboot.org/c/coreboot/+/81784/comment/90d22804_efd0124e : PS1, Line 4: XEON_SP_COMMON_BASE This is not needed. if !HAVE_ACPI_RESUME && ACPI_S1_NOT_SUPPORTED & &DISABLE_ACPI_HIBERNATE are selected you get 0 for SSFG -- To view, visit https://review.coreboot.org/c/coreboot/+/81784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8ee0d8600f72c6d732e685a46dc89c7e24de8334 Gerrit-Change-Number: 81784 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 10:03:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0
by Arthur Heymans (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81783?usp=email ) Change subject: soc/intel/xeon_sp: Remove MAINBOARD_USES_FSP2_0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I45332d49dd21f9749fce458877777a4b783a1b11 Gerrit-Change-Number: 81783 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 10:00:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 40: (1 comment) File src/soc/intel/xeon_sp/gnr/Kconfig: https://review.coreboot.org/c/coreboot/+/81316/comment/5f02cb3b_086b8ce5 : PS37, Line 76: config CPU_MICROCODE_CBFS_LEN : hex : default 0x27b800 > Does FSP-T work without this due to FIT? If so, maybe drop like: https://review.coreboot. […] Sure, we can drop here. Updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 40 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 09:50:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#41). Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=Build and boot on intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 23 files changed, 1,306 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/41 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 41 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 09 Apr '24

09 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 40: (1 comment) File src/soc/intel/xeon_sp/gnr/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/81316/comment/ffe14502_eb2eaf89 : PS33, Line 6: Name (_S0, Package () // mandatory system state : { : 0x00, 0x00, 0x00, 0x00 : }) : : Name (_S5, Package () // mandatory system state : { : 0x07, 0x00, 0x00, 0x00 : }) > I removed the platform.asl first from this patch. I raised https://review.coreboot.org/c/coreboot/+/81784 and let us discuss there. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 40 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 09 Apr 2024 09:48:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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