coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: mb/google/skyrim: Increase SMMSTORE size to 256K
by Felix Held (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81868?usp=email ) Change subject: mb/google/skyrim: Increase SMMSTORE size to 256K ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81868?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f9d27c27ab7148dfc530322f741a576c348de7 Gerrit-Change-Number: 81868 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 16:34:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/myst: Increase SMMSTORE size to 256K
by Felix Held (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Martin Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81867?usp=email ) Change subject: mb/google/myst: Increase SMMSTORE size to 256K ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81867?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic45324b8c5bbd205e889e934c9d5dd17f7775152 Gerrit-Change-Number: 81867 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 16:33:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/sifive/hifive-unleashed: Update devicetree
by Maximilian Brune (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81911?usp=email ) Change subject: mb/sifive/hifive-unleashed: Update devicetree ...................................................................... mb/sifive/hifive-unleashed: Update devicetree source: upstream Linux kernel Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I1ce1b49de089b6b9d1c70439e60895464806d50e --- M src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi M src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts 2 files changed, 177 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81911/1 diff --git a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi index e77036b..1a85fa6 100644 --- a/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi +++ b/src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi @@ -1,4 +1,5 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2019 SiFive, Inc */ /dts-v1/; @@ -10,6 +11,7 @@ aliases { serial0 = &uart0; serial1 = &uart1; + ethernet0 = &eth0; }; chosen { @@ -18,7 +20,6 @@ cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu0: cpu@0 { compatible = "sifive,e51", "sifive,rocket0", "riscv"; device_type = "cpu"; @@ -27,6 +28,9 @@ i-cache-size = <16384>; reg = <0>; riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei", + "zihpm"; status = "disabled"; cpu0_intc: interrupt-controller { #interrupt-cells = <1>; @@ -50,7 +54,11 @@ mmu-type = "riscv,sv39"; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; + next-level-cache = <&l2cache>; cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -58,7 +66,6 @@ }; }; cpu2: cpu@2 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -74,7 +81,11 @@ mmu-type = "riscv,sv39"; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; + next-level-cache = <&l2cache>; cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -82,7 +93,6 @@ }; }; cpu3: cpu@3 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -98,7 +108,11 @@ mmu-type = "riscv,sv39"; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; + next-level-cache = <&l2cache>; cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -106,7 +120,6 @@ }; }; cpu4: cpu@4 { - clock-frequency = <0>; compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>; @@ -122,31 +135,60 @@ mmu-type = "riscv,sv39"; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; tlb-split; + next-level-cache = <&l2cache>; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; soc { #address-cells = <2>; #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; + compatible = "simple-bus"; ranges; plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; + #address-cells = <0>; + #interrupt-cells = <1>; interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; + interrupts-extended = + <&cpu0_intc 0xffffffff>, + <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, + <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, + <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, + <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; + riscv,ndev = <53>; }; prci: clock-controller@10000000 { compatible = "sifive,fu540-c000-prci"; @@ -162,6 +204,15 @@ clocks = <&prci 3>; status = "disabled"; }; + dma: dma-controller@3000000 { + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic0>; + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, + <30>; + dma-channels = <4>; + #dma-cells = <1>; + }; uart1: serial@10011000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; reg = <0x0 0x10011000 0x0 0x1000>; @@ -184,8 +235,8 @@ }; qspi0: spi@10040000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; + reg = <0x0 0x10040000 0x0 0x1000>, + <0x0 0x20000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <51>; clocks = <&prci 3>; @@ -195,8 +246,8 @@ }; qspi1: spi@10041000 { compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; + reg = <0x0 0x10041000 0x0 0x1000>, + <0x0 0x30000000 0x0 0x10000000>; interrupt-parent = <&plic0>; interrupts = <52>; clocks = <&prci 3>; @@ -218,15 +269,58 @@ compatible = "sifive,fu540-c000-gem"; interrupt-parent = <&plic0>; interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; + reg = <0x0 0x10090000 0x0 0x2000>, + <0x0 0x100a0000 0x0 0x1000>; local-mac-address = [00 00 00 00 00 00]; clock-names = "pclk", "hclk"; - clocks = <&prci 2>, <&prci 2>; + clocks = <&prci 2>, + <&prci 2>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; - + pwm0: pwm@10020000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10020000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <42>, <43>, <44>, <45>; + clocks = <&prci 3>; + #pwm-cells = <3>; + status = "disabled"; + }; + pwm1: pwm@10021000 { + compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; + reg = <0x0 0x10021000 0x0 0x1000>; + interrupt-parent = <&plic0>; + interrupts = <46>, <47>, <48>, <49>; + clocks = <&prci 3>; + #pwm-cells = <3>; + status = "disabled"; + }; + l2cache: cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic0>; + interrupts = <1>, <2>, <3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + gpio: gpio@10060000 { + compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; + interrupt-parent = <&plic0>; + interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, + <14>, <15>, <16>, <17>, <18>, <19>, <20>, + <21>, <22>; + reg = <0x0 0x10060000 0x0 0x1000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&prci 3>; + status = "disabled"; + }; }; }; diff --git a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts index f453af9..7ba4ba6 100644 --- a/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts +++ b/src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts @@ -1,18 +1,18 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2018-2019 SiFive, Inc */ /include/ "fu540-c000.dtsi" / { - #address-cells = <2>; - #size-cells = <2>; model = "SiFive HiFive Unleashed A00"; - compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; + compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000", + "sifive,fu540"; chosen { + stdout-path = "serial0"; }; cpus { - /* Clock frequency (in Hz) of the PCB crystal for rtcclk */ timebase-frequency = <1000000>; }; @@ -21,9 +21,6 @@ reg = <0x0 0x80000000 0x2 0x00000000>; }; - soc { - }; - hfclk: hfclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -37,6 +34,46 @@ clock-frequency = <1000000>; clock-output-names = "rtcclk"; }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 10 1>; + }; + + led-controller { + compatible = "pwm-leds"; + + led-d1 { + pwms = <&pwm0 0 7812500 1>; + active-low; + color = <2>; + max-brightness = <255>; + label = "d1"; + }; + + led-d2 { + pwms = <&pwm0 1 7812500 1>; + active-low; + color = <2>; + max-brightness = <255>; + label = "d2"; + }; + + led-d3 { + pwms = <&pwm0 2 7812500 1>; + active-low; + color = <2>; + max-brightness = <255>; + label = "d3"; + }; + + led-d4 { + pwms = <&pwm0 3 7812500 1>; + active-low; + color = <2>; + max-brightness = <255>; + label = "d4"; + }; + }; }; &uart0 { @@ -54,7 +91,7 @@ &qspi0 { status = "okay"; flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; + compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <50000000>; m25p,fast-read; @@ -71,6 +108,7 @@ spi-max-frequency = <20000000>; voltage-ranges = <3300 3300>; disable-wp; + gpios = <&gpio 11 1>; }; }; @@ -79,6 +117,19 @@ phy-mode = "gmii"; phy-handle = <&phy0>; phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.0771"; reg = <0>; }; }; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81911?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ce1b49de089b6b9d1c70439e60895464806d50e Gerrit-Change-Number: 81911 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE
by Maximilian Brune (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81910?usp=email ) Change subject: mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE ...................................................................... mb/sifive/hifive-unleashed: Disable SEPARATE_ROMSTAGE Currently the HiFive Unleashed produces the following exception: [DEBUG] Exception: Load address misaligned [DEBUG] Hart ID: 0 [DEBUG] Previous mode: machine [DEBUG] Bad instruction pc: 0x080010d0 [DEBUG] Bad address: 0x08026ab3 [DEBUG] Stored ra: 0x080010c8 [DEBUG] Stored sp: 0x08010cc8 The coreboot LZ4 decompression code does some misaligned access during decompression which the FU540 apparently does not support in SRAM. Do not compile a separate romstage so that nothing must be decompressed into SRAM. The separate romstage is not needed on the board anyway and probably also gives a little bit of performance improvement. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add --- M src/mainboard/sifive/hifive-unleashed/romstage.c M src/soc/sifive/fu540/Kconfig 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/81910/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index d3ecd2a..f90d2d7 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -5,10 +5,11 @@ #include <console/streams.h> #include <console/uart.h> #include <program_loading.h> +#include <romstage_common.h> #include <soc/clock.h> #include <soc/sdram.h> -void main(void) +void __noreturn romstage_main(void) { console_init(); diff --git a/src/soc/sifive/fu540/Kconfig b/src/soc/sifive/fu540/Kconfig index fb15762..3d1db3b 100644 --- a/src/soc/sifive/fu540/Kconfig +++ b/src/soc/sifive/fu540/Kconfig @@ -15,6 +15,9 @@ select UART_OVERRIDE_REFCLK select RISCV_HAS_OPENSBI +config SEPARATE_ROMSTAGE + default n if SOC_SIFIVE_FU540 + if SOC_SIFIVE_FU540 config MEMLAYOUT_LD_FILE -- To view, visit https://review.coreboot.org/c/coreboot/+/81910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id165829bfd35be2bce2bbb019c208a304f627add Gerrit-Change-Number: 81910 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/sifive/fu540/chip.c: Add RAM resources
by Maximilian Brune (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Philipp Hug, ron minnich. Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81909?usp=email ) Change subject: soc/sifive/fu540/chip.c: Add RAM resources ...................................................................... soc/sifive/fu540/chip.c: Add RAM resources Add RAM region so that the payload can be placed in there without coreboot complaining that the payload doesn't target a RAM region. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855 --- M src/soc/sifive/fu540/chip.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/81909/1 diff --git a/src/soc/sifive/fu540/chip.c b/src/soc/sifive/fu540/chip.c index e33b4a3..ba5d4845 100644 --- a/src/soc/sifive/fu540/chip.c +++ b/src/soc/sifive/fu540/chip.c @@ -1,7 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <cbmem.h> #include <device/device.h> +#include <soc/addressmap.h> + +static void fu540_init(struct device *dev) +{ + int index = 0; + ram_from_to(dev, index++, FU540_DRAM, (uintptr_t)cbmem_top()); +} struct chip_operations soc_sifive_fu540_ops = { .name = "SIFIVE FU540", + .enable_dev = fu540_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/81909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id07eae3560ce69cd8a6a695702fa0b4463c50855 Gerrit-Change-Number: 81909 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/sifive/fu540/memlayout.ld: Enhance OpenSBI size
by Maximilian Brune (Code Review) 15 Apr '24

15 Apr '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81908?usp=email ) Change subject: soc/sifive/fu540/memlayout.ld: Enhance OpenSBI size ...................................................................... soc/sifive/fu540/memlayout.ld: Enhance OpenSBI size OpenSBI is currently overlapping with ramstage and the build therefore fails. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I3523cac152e505b90a8f10ba03ea2b9f8604ab40 --- M src/soc/sifive/fu540/memlayout.ld 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/81908/1 diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld index 8fc875d..74f580c 100644 --- a/src/soc/sifive/fu540/memlayout.ld +++ b/src/soc/sifive/fu540/memlayout.ld @@ -21,8 +21,8 @@ L2LIM_END(FU540_L2LIM + 2M) DRAM_START(FU540_DRAM) - REGION(opensbi, FU540_DRAM, 128K, 4K) - RAMSTAGE(FU540_DRAM + 128K, 2M) - MEM_STACK(FU540_DRAM + 128K + 2M, 20K) + REGION(opensbi, FU540_DRAM, 256K, 4K) + RAMSTAGE(FU540_DRAM + 256K, 2M) + MEM_STACK(FU540_DRAM + 256K + 2M, 20K) POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } -- To view, visit https://review.coreboot.org/c/coreboot/+/81908?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3523cac152e505b90a8f10ba03ea2b9f8604ab40 Gerrit-Change-Number: 81908 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/guybrush: Increase SMMSTORE size to 256K
by Felix Held (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81866?usp=email ) Change subject: mb/google/guybrush: Increase SMMSTORE size to 256K ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4fdacd493d83fa3c1683a06d1276b0190f6db8b Gerrit-Change-Number: 81866 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 16:33:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/soundwire/ALC722: Add ALC722 codec support
by Saurabh Mishra (Code Review) 15 Apr '24

15 Apr '24

Saurabh Mishra has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/80463?usp=email ) Change subject: drivers/soundwire/ALC722: Add ALC722 codec support ...................................................................... Abandoned New patch will be pushed sooner. -- To view, visit https://review.coreboot.org/c/coreboot/+/80463?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dfa1b8cc6bec8f227083e161a6ee876c91808d2 Gerrit-Change-Number: 80463 Gerrit-PatchSet: 1 Gerrit-Owner: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: mb/google/zork: Enable eMMC driver for edk2 payload
by Felix Held (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Jason Nien, Martin Roth, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81893?usp=email ) Change subject: mb/google/zork: Enable eMMC driver for edk2 payload ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81893?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7e98f309594554dbcf1ddd875d47c89bd9e0e44 Gerrit-Change-Number: 81893 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 16:24:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpigen_ps2_keybd: Add support for dictation key
by Aseda Aboagye (Code Review) 15 Apr '24

15 Apr '24

Aseda Aboagye has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81863?usp=email ) Change subject: acpigen_ps2_keybd: Add support for dictation key ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81863/comment/64aefba5_19b1b253 : PS2, Line 14: Flash DUT that emits a scancode for a dictation key, verify that it : is mapped to KEY_DICTATE in the Linux kernel. > Next time, it’d be great if you also documented your comments, so it’s easier for people to reproduc […] ACK, will do. Yes, I used `evtest` to verify. File src/acpi/acpigen_ps2_keybd.c: https://review.coreboot.org/c/coreboot/+/81863/comment/22d7f73b_5b0dd32b : PS2, Line 59: [PS2_KEY_DICTATE] = KEYMAP(0xa7, KEY_DICTATE), /* e027*/ > Please sort the entry. Could you be a bit more specific as to what it should have been sorted by? This table is currently sorted by the enum values. -- To view, visit https://review.coreboot.org/c/coreboot/+/81863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc56662a9d6b29e84ab81ed93cb46d2e8372de9 Gerrit-Change-Number: 81863 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 15 Apr 2024 15:33:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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