April 2024 - coreboot-gerrit - mail.coreboot.org

[XS] Change in coreboot[main]: soc/intel/alderlake: Enable CrashLog config
by Benjamin Doron (Code Review) April 16, 2024

April 16, 2024

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81934?usp=email ) Change subject: soc/intel/alderlake: Enable CrashLog config ...................................................................... soc/intel/alderlake: Enable CrashLog config AlderLake silicon has CrashLog support, mainboards are not required to explicitly select this config to declare support. Change-Id: I5a3e02c6592081ee049be79336c7f59ab5e52696 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/81934/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5086069..b246f76 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -82,6 +82,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CRASHLOG select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_MBUS_JOIN if MAINBOARD_HAS_CHROMEOS && BMP_LOGO -- To view, visit https://review.coreboot.org/c/coreboot/+/81934?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a3e02c6592081ee049be79336c7f59ab5e52696 Gerrit-Change-Number: 81934 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: ec/google/chromeec: Update EC headers
by Caveh Jalali (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Aseda Aboagye. Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81932?usp=email ) Change subject: ec/google/chromeec: Update EC headers ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 21:31:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: ec/google/chromeec: Update EC headers
by Forest Mittelberg (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Aseda Aboagye, Caveh Jalali. Forest Mittelberg has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81932?usp=email ) Change subject: ec/google/chromeec: Update EC headers ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 21:21:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: ec/google/chromeec: Update EC headers
by Aseda Aboagye (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Caveh Jalali, Forest Mittelberg. Hello Caveh Jalali, Forest Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81932?usp=email to look at the new patch set (#3). Change subject: ec/google/chromeec: Update EC headers ...................................................................... ec/google/chromeec: Update EC headers Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 154 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81932/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 3 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: Generated using update_ec_headers.sh [EC-DIR]
by Aseda Aboagye (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Caveh Jalali, Forest Mittelberg. Hello Caveh Jalali, Forest Mittelberg, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81932?usp=email to look at the new patch set (#2). Change subject: Generated using update_ec_headers.sh [EC-DIR] ...................................................................... Generated using update_ec_headers.sh [EC-DIR] The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 154 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81932/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 2 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: Generated using update_ec_headers.sh [EC-DIR].
by Aseda Aboagye (Code Review) April 15, 2024

April 15, 2024

Aseda Aboagye has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81932?usp=email ) Change subject: Generated using update_ec_headers.sh [EC-DIR]. ...................................................................... Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: 9fdd96bfc6 keyboard: Add support for a "Dictation" key The original include/ec_cmd_api.h version in the EC repo is: 562316a71e include: Add fingerprint host commands to ec_cmd_api.h Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Signed-off-by: Aseda Aboagye <aaboagye(a)google.com> --- M src/ec/google/chromeec/ec_cmd_api.h M src/ec/google/chromeec/ec_commands.h 2 files changed, 154 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81932/1 diff --git a/src/ec/google/chromeec/ec_cmd_api.h b/src/ec/google/chromeec/ec_cmd_api.h index 2b0bdde..453f507 100644 --- a/src/ec/google/chromeec/ec_cmd_api.h +++ b/src/ec/google/chromeec/ec_cmd_api.h @@ -107,6 +107,20 @@ NULL, 0); } +static inline int ec_cmd_fp_frame(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_frame *p, + uint8_t *r) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_FRAME, 0, p, sizeof(*p), r, + p->size); +} + +static inline int ec_cmd_fp_template(CROS_EC_COMMAND_INFO *h, + const struct ec_params_fp_template *p, + int size) +{ + return CROS_EC_COMMAND(h, EC_CMD_FP_TEMPLATE, 0, p, size, NULL, 0); +} /* * Section 2: EC interface functions that can be generated with the help * of template macros. @@ -280,9 +294,13 @@ flash_region_info, flash_region_info); _CROS_EC_C0_F_RF(EC_CMD_FLASH_SPI_INFO, flash_spi_info); _CROS_EC_C0_F_PF(EC_CMD_FORCE_LID_OPEN, force_lid_open); -_CROS_EC_C0_F_PF_RF(EC_CMD_FP_MODE, fp_mode); _CROS_EC_C0_F_PF(EC_CMD_FP_SEED, fp_seed); +_CROS_EC_C0_F_PF_RF(EC_CMD_FP_MODE, fp_mode); +_CROS_EC_C0_F_PF_RF(EC_CMD_FP_READ_MATCH_SECRET, fp_read_match_secret); +_CROS_EC_C0_F_RF(EC_CMD_FP_ENC_STATUS, fp_encryption_status); _CROS_EC_C0_F_RF(EC_CMD_FP_STATS, fp_stats); +_CROS_EC_C1_F_PF(EC_CMD_FP_CONTEXT, fp_context); +_CROS_EC_CV_F_R(EC_CMD_FP_INFO, 1, fp_info, fp_info); _CROS_EC_CV_F_R(EC_CMD_GET_BOARD_VERSION, 0, get_board_version, board_version); _CROS_EC_C0_F_RF(EC_CMD_GET_BOOT_TIME, get_boot_time); _CROS_EC_C0_F_RF(EC_CMD_GET_CHIP_INFO, get_chip_info); @@ -292,8 +310,9 @@ _CROS_EC_C0_F_RF(EC_CMD_GET_COMMS_STATUS, get_comms_status); _CROS_EC_C0_F_RF(EC_CMD_GET_FEATURES, get_features); _CROS_EC_CV_F_R(EC_CMD_GET_KEYBD_CONFIG, 0, get_keybd_config, keybd_config); -_CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event); _CROS_EC_C0_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); +_CROS_EC_C1_F_RF(EC_CMD_GET_NEXT_EVENT, get_next_event); +_CROS_EC_CV_F_R(EC_CMD_GET_NEXT_EVENT, 2, get_next_event_v2, get_next_event_v1); _CROS_EC_C0_F_PF_RF(EC_CMD_GET_PD_PORT_CAPS, get_pd_port_caps); _CROS_EC_C0_F_RF(EC_CMD_GET_PROTOCOL_INFO, get_protocol_info); _CROS_EC_CV_F_R(EC_CMD_GET_UPTIME_INFO, 0, get_uptime_info, uptime_info); @@ -304,7 +323,7 @@ _CROS_EC_C0_F_PF(EC_CMD_GPIO_SET, gpio_set); _CROS_EC_CV_F_P_R(EC_CMD_GSV_PAUSE_IN_S5, 0, gsv_pause_in_s5, get_set_value, get_set_value); -_CROS_EC_C0_F_PF(EC_CMD_HANG_DETECT, hang_detect); +_CROS_EC_C0_F_PF_RF(EC_CMD_HANG_DETECT, hang_detect); _CROS_EC_C0_F_PF_RF(EC_CMD_HELLO, hello); _CROS_EC_C0_F_PF_RF(EC_CMD_HIBERNATION_DELAY, hibernation_delay); _CROS_EC_C0_F_PF_RF(EC_CMD_HOST_EVENT, host_event); diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index b66f9d3..0d474cb 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -522,9 +522,9 @@ #define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */ #define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */ -#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f) +#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f) #define EC_ACPI_MEM_USB_RETIMER_OP(x) \ - (((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) + (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT) /* * ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data @@ -690,6 +690,8 @@ EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */ EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */ + EC_RES_COUNT, + EC_RES_MAX = UINT16_MAX, /**< Force enum to be 16 bits */ } __packed; BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t)); @@ -737,6 +739,39 @@ #endif +/* clang-format off */ +#define EC_STATUS_TEXT \ + { \ + EC_MAP_ITEM(EC_RES_SUCCESS, SUCCESS), \ + EC_MAP_ITEM(EC_RES_INVALID_COMMAND, INVALID_COMMAND), \ + EC_MAP_ITEM(EC_RES_ERROR, ERROR), \ + EC_MAP_ITEM(EC_RES_INVALID_PARAM, INVALID_PARAM), \ + EC_MAP_ITEM(EC_RES_ACCESS_DENIED, ACCESS_DENIED), \ + EC_MAP_ITEM(EC_RES_INVALID_RESPONSE, INVALID_RESPONSE), \ + EC_MAP_ITEM(EC_RES_INVALID_VERSION, INVALID_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_CHECKSUM, INVALID_CHECKSUM), \ + EC_MAP_ITEM(EC_RES_IN_PROGRESS, IN_PROGRESS), \ + EC_MAP_ITEM(EC_RES_UNAVAILABLE, UNAVAILABLE), \ + EC_MAP_ITEM(EC_RES_TIMEOUT, TIMEOUT), \ + EC_MAP_ITEM(EC_RES_OVERFLOW, OVERFLOW), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER, INVALID_HEADER), \ + EC_MAP_ITEM(EC_RES_REQUEST_TRUNCATED, REQUEST_TRUNCATED), \ + EC_MAP_ITEM(EC_RES_RESPONSE_TOO_BIG, RESPONSE_TOO_BIG), \ + EC_MAP_ITEM(EC_RES_BUS_ERROR, BUS_ERROR), \ + EC_MAP_ITEM(EC_RES_BUSY, BUSY), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_VERSION, INVALID_HEADER_VERSION), \ + EC_MAP_ITEM(EC_RES_INVALID_HEADER_CRC, INVALID_HEADER_CRC), \ + EC_MAP_ITEM(EC_RES_INVALID_DATA_CRC, INVALID_DATA_CRC), \ + EC_MAP_ITEM(EC_RES_DUP_UNAVAILABLE, DUP_UNAVAILABLE), \ + } +/* clang-format on */ + +#ifndef __cplusplus +#define EC_MAP_ITEM(k, v) [k] = #v +BUILD_ASSERT(ARRAY_SIZE(((const char *[])EC_STATUS_TEXT)) == EC_RES_COUNT); +#undef EC_MAP_ITEM +#endif + /* * Host event codes. ACPI query EC command uses code 0 to mean "no event * pending". We explicitly specify each value in the enum listing so they won't @@ -1658,6 +1693,10 @@ * The EC supports DP2.1 capability */ EC_FEATURE_TYPEC_DP2_1 = 52, + /* + * The MCU is System Companion Processor Core 1 + */ + EC_FEATURE_SCP_C1 = 53, }; #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32) @@ -2864,6 +2903,7 @@ MOTIONSENSE_CHIP_BMI323 = 28, MOTIONSENSE_CHIP_BMI220 = 29, MOTIONSENSE_CHIP_CM32183 = 30, + MOTIONSENSE_CHIP_VEML3328 = 31, MOTIONSENSE_CHIP_MAX, }; @@ -4096,15 +4136,15 @@ } __ec_align2; /* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */ -#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF) -#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F) +#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF) +#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F) #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4 #define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \ - (((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) + (((fpe) & 0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET) #define EC_MKBP_FP_MATCH_IDX_OFFSET 12 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000 #define EC_MKBP_FP_MATCH_IDX(fpe) \ - (((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) + (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET) #define EC_MKBP_FP_ENROLL BIT(27) #define EC_MKBP_FP_MATCH BIT(28) #define EC_MKBP_FP_FINGER_DOWN BIT(29) @@ -4122,6 +4162,7 @@ #define EC_MKBP_FP_ERR_MATCH_NO 0 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6 #define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7 +#define EC_MKBP_FP_ERR_MATCH_NO_AUTH_FAIL 8 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4 #define EC_MKBP_FP_ERR_MATCH_YES 1 @@ -4707,60 +4748,50 @@ } __ec_align1; /*****************************************************************************/ -/* Power button hang detect */ - +/* AP hang detect */ #define EC_CMD_HANG_DETECT 0x009F -/* Reasons to start hang detection timer */ -/* Power button pressed */ -#define EC_HANG_START_ON_POWER_PRESS BIT(0) +#define EC_HANG_DETECT_MIN_TIMEOUT 5 -/* Lid closed */ -#define EC_HANG_START_ON_LID_CLOSE BIT(1) +/* EC hang detect commands */ +enum ec_hang_detect_cmds { + /* Reload AP hang detect timer. */ + EC_HANG_DETECT_CMD_RELOAD = 0x0, -/* Lid opened */ -#define EC_HANG_START_ON_LID_OPEN BIT(2) + /* Stop AP hang detect timer. */ + EC_HANG_DETECT_CMD_CANCEL = 0x1, -/* Start of AP S3->S0 transition (booting or resuming from suspend) */ -#define EC_HANG_START_ON_RESUME BIT(3) + /* Configure watchdog with given reboot timeout and + * cancel currently running AP hand detect timer. + */ + EC_HANG_DETECT_CMD_SET_TIMEOUT = 0x2, -/* Reasons to cancel hang detection */ + /* Get last hang status - whether the AP boot was clear or not */ + EC_HANG_DETECT_CMD_GET_STATUS = 0x3, -/* Power button released */ -#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8) - -/* Any host command from AP received */ -#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9) - -/* Stop on end of AP S0->S3 transition (suspending or shutting down) */ -#define EC_HANG_STOP_ON_SUSPEND BIT(10) - -/* - * If this flag is set, all the other fields are ignored, and the hang detect - * timer is started. This provides the AP a way to start the hang timer - * without reconfiguring any of the other hang detect settings. Note that - * you must previously have configured the timeouts. - */ -#define EC_HANG_START_NOW BIT(30) - -/* - * If this flag is set, all the other fields are ignored (including - * EC_HANG_START_NOW). This provides the AP a way to stop the hang timer - * without reconfiguring any of the other hang detect settings. - */ -#define EC_HANG_STOP_NOW BIT(31) + /* Clear last hang status. Called when AP is rebooting/shutting down + * gracefully. + */ + EC_HANG_DETECT_CMD_CLEAR_STATUS = 0x4 +}; struct ec_params_hang_detect { - /* Flags; see EC_HANG_* */ - uint32_t flags; + uint16_t command; /* enum ec_hang_detect_cmds */ + /* Timeout in seconds before generating reboot */ + uint16_t reboot_timeout_sec; +} __ec_align2; - /* Timeout in msec before generating host event, if enabled */ - uint16_t host_event_timeout_msec; - - /* Timeout in msec before generating warm reboot, if enabled */ - uint16_t warm_reboot_timeout_msec; -} __ec_align4; - +/* Status codes that describe whether AP has boot normally or the hang has been + * detected and EC has reset AP + */ +enum ec_hang_detect_status { + EC_HANG_DETECT_AP_BOOT_NORMAL = 0x0, + EC_HANG_DETECT_AP_BOOT_EC_WDT = 0x1, + EC_HANG_DETECT_AP_BOOT_COUNT, +}; +struct ec_response_hang_detect { + uint8_t status; /* enum ec_hang_detect_status */ +} __ec_align1; /*****************************************************************************/ /* Commands for battery charging */ @@ -4817,7 +4848,7 @@ CS_PARAM_DEBUG_MANUAL_MODE, CS_PARAM_DEBUG_SEEMS_DEAD, CS_PARAM_DEBUG_SEEMS_DISCONNECTED, - CS_PARAM_DEBUG_BATT_REMOVED, + CS_PARAM_DEBUG_BATT_REMOVED, /* Deprecated */ CS_PARAM_DEBUG_MANUAL_CURRENT, CS_PARAM_DEBUG_MANUAL_VOLTAGE, CS_PARAM_DEBUG_MAX = 0x2ffff, @@ -5193,8 +5224,8 @@ * bits[31:28]: port number */ #define EC_MKBP_EVENT_CEC_PACK(events, port) \ - (((events)&GENMASK(27, 0)) | (((port)&0xf) << 28)) -#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event)&GENMASK(27, 0)) + (((events) & GENMASK(27, 0)) | (((port) & 0xf) << 28)) +#define EC_MKBP_EVENT_CEC_GET_EVENTS(event) ((event) & GENMASK(27, 0)) #define EC_MKBP_EVENT_CEC_GET_PORT(event) (((event) >> 28) & 0xf) /* CEC message from the AP to be written on the CEC bus */ @@ -6064,9 +6095,9 @@ #define PD_LOG_PORT_MASK 0xe0 #define PD_LOG_PORT_SHIFT 5 #define PD_LOG_PORT_SIZE(port, size) \ - (((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK)) + (((port) << PD_LOG_PORT_SHIFT) | ((size) & PD_LOG_SIZE_MASK)) #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT) -#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK) +#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK) /* PD event log : entry types */ /* PD MCU events */ @@ -6316,6 +6347,7 @@ /* struct board_batt_params */ CBI_TAG_BATTERY_CONFIG = 12, /* CBI_TAG_BATTERY_CONFIG_1 ~ 15 will use 13 ~ 27. */ + CBI_TAG_BATTERY_CONFIG_15 = 27, /* Last entry */ CBI_TAG_COUNT, @@ -6323,7 +6355,7 @@ union ec_common_control { struct { - uint32_t bcic_enabled : 1; + uint32_t bcic_enabled : 1; /* Unused. Take it over as yours. */ }; uint32_t raw_value; }; @@ -6565,6 +6597,7 @@ enum ec_chip_type { EC_CHIP_TYPE_CBI_EEPROM = 0, EC_CHIP_TYPE_TCPC = 1, + EC_CHIP_TYPE_PDC = 2, EC_CHIP_TYPE_COUNT, EC_CHIP_TYPE_MAX = 0xFF, }; @@ -6760,6 +6793,9 @@ TK_KBD_BKLIGHT_TOGGLE = 18, TK_MICMUTE = 19, TK_MENU = 20, + TK_DICTATE = 21, + + TK_COUNT }; /* @@ -6784,6 +6820,11 @@ */ #define KEYBD_CAP_SCRNLOCK_KEY BIT(2) +/* + * Whether the keyboard has an assistant key. + */ +#define KEYBD_CAP_ASSISTANT_KEY BIT(3) + struct ec_response_keybd_config { /* * Number of top row keys, excluding Esc and Screenlock. @@ -7123,6 +7164,7 @@ #define PD_STATUS_EVENT_VDM_REQ_REPLY BIT(6) #define PD_STATUS_EVENT_VDM_REQ_FAILED BIT(7) #define PD_STATUS_EVENT_VDM_ATTENTION BIT(8) +#define PD_STATUS_EVENT_COUNT 9 /* * Encode and decode for BCD revision response @@ -7428,7 +7470,8 @@ #define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf) #define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT) /* Utility macro for extracting event bits. */ -#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) +#define EC_MKBP_PCHG_EVENT_MASK(e) \ + ((e) & GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0)) #define EC_MKBP_PCHG_UPDATE_OPENED BIT(0) #define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1) @@ -7726,7 +7769,7 @@ uint8_t reserved; } __packed __aligned(2); -/** +/* * The 'config' of a battery. */ struct board_batt_params { @@ -7734,9 +7777,22 @@ struct battery_info batt_info; } __packed __aligned(4); -#define SBS_MAX_STRING_SIZE 32 +/* + * The SBS defines a string object as a block of chars, 32 byte maximum, where + * the first byte indicates the number of chars in the block (excluding the + * first byte). + * + * Thus, the actual string length (i.e. the value strlen returns) is limited to + * 31 (=SBS_MAX_STR_SIZE). + * + * SBS_MAX_STR_OBJ_SIZE can be used as the size of a buffer for an SBS string + * object but also as a buffer for a c-lang string because the null terminating + * char also takes one byte. + */ +#define SBS_MAX_STR_SIZE 31 +#define SBS_MAX_STR_OBJ_SIZE (SBS_MAX_STR_SIZE + 1) -/** +/* * Header describing a battery config stored in CBI. Only struct_version has * size and position independent of struct_version. The rest varies as * struct_version changes. @@ -7776,8 +7832,8 @@ /* manuf_name, device_name, board_batt_params follow after this. */ } __packed; -#define BATT_CONF_MAX_SIZE \ - (sizeof(struct batt_conf_header) + SBS_MAX_STRING_SIZE * 2 + \ +#define BATT_CONF_MAX_SIZE \ + (sizeof(struct batt_conf_header) + SBS_MAX_STR_OBJ_SIZE * 2 + \ sizeof(struct board_batt_params)) /* @@ -7884,7 +7940,7 @@ }; /* Extracts the capture type from the sensor 'mode' word */ #define FP_CAPTURE_TYPE(mode) \ - (((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) + (((mode) & FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT) struct ec_params_fp_mode { uint32_t mode; /* as defined by FP_MODE_ constants */ @@ -7898,7 +7954,7 @@ #define EC_CMD_FP_INFO 0x0403 /* Number of dead pixels detected on the last maintenance */ -#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF) +#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF) /* Unknown number of dead pixels detected on the last maintenance */ #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF) /* No interrupt from the sensor */ @@ -8067,6 +8123,10 @@ #define FP_CONTEXT_STATUS_MATCH_PROCESSED_SET BIT(2) /* FP auth_nonce had been set or not*/ #define FP_CONTEXT_AUTH_NONCE_SET BIT(3) +/* FP user_id had been set or not*/ +#define FP_CONTEXT_USER_ID_SET BIT(4) +/* FP templates are unlocked for nonce context or not */ +#define FP_CONTEXT_TEMPLATE_UNLOCKED_SET BIT(5) struct ec_response_fp_encryption_status { /* Used bits in encryption engine status */ @@ -8184,15 +8244,11 @@ uint8_t enc_secret[FP_POSITIVE_MATCH_SECRET_BYTES]; } __ec_align4; -/* Preload encrypted template into the MCU buffer */ -#define EC_CMD_FP_PRELOAD_TEMPLATE 0x0416 +/* Unlock the fpsensor template with the current nonce context */ +#define EC_CMD_FP_UNLOCK_TEMPLATE 0x0417 -struct ec_params_fp_preload_template { - uint32_t offset; - uint32_t size; - uint16_t fgr; - uint8_t reserved[2]; - uint8_t data[]; +struct ec_params_fp_unlock_template { + uint16_t fgr_num; } __ec_align4; /*****************************************************************************/ @@ -8303,10 +8359,10 @@ uint16_t design_capacity; uint16_t design_voltage; uint32_t cycle_count; - char manufacturer[32]; - char device_name[32]; - char serial[32]; - char chemistry[32]; + char manufacturer[SBS_MAX_STR_OBJ_SIZE]; + char device_name[SBS_MAX_STR_OBJ_SIZE]; + char serial[SBS_MAX_STR_OBJ_SIZE]; + char chemistry[SBS_MAX_STR_OBJ_SIZE]; } __ec_align4; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/81932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ec965d07aa4cb1fe54916845780f342ea3debb9 Gerrit-Change-Number: 81932 Gerrit-PatchSet: 1 Gerrit-Owner: Aseda Aboagye <aaboagye(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Felix Singer (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Joel Linn, Matt DeVillier, Nicholas Chin, Nico Huber. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 20:43:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Angel Pons (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Felix Singer, Joel Linn, Matt DeVillier, Nicholas Chin, Nico Huber. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 20:06:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Joel Linn (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Angel Pons, Felix Singer, Matt DeVillier, Nicholas Chin, Nico Huber. Joel Linn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81368?usp=email ) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... Patch Set 6: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81368/comment/8bbfc85a_5c986163 : PS5, Line 12: All peripherals should work. : Automatic fan control as well as S3 are working. : The board was tested to boot Linux and Windows. EHCI debug is untested. : When using MrChromebox edk2 with secure boot build in, the board will : hang on each boot for about 20 seconds before continuing. > Should probably prefix these with bullet points, e.g. `* `. Done File src/mainboard/hp/pro_3500_series/Makefile.mk: PS5: > Add a blank line between each stage for better distinction. Done File src/mainboard/hp/pro_3500_series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/81368/comment/9103c5eb_c6969dd0 : PS5, Line 11: device ref host_bridge on end > Enabled in chipset devicetree Done https://review.coreboot.org/c/coreboot/+/81368/comment/088df9f1_c5293d57 : PS5, Line 16: register "docking_supported" = "0" > Doesn't have any effect, set to 0 anyway. Done https://review.coreboot.org/c/coreboot/+/81368/comment/b779d368_9619434e : PS5, Line 27: device ref mei1 on end > Enabled in chipset devicetree Done https://review.coreboot.org/c/coreboot/+/81368/comment/71218bbc_ad3b8271 : PS5, Line 36: # LPC bridge > Remove superfluous comment Done https://review.coreboot.org/c/coreboot/+/81368/comment/46934328_9cb4ecb2 : PS5, Line 96: device ref smbus on end > Enabled in chipset devicetree Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Mon, 15 Apr 2024 19:57:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge)
by Joel Linn (Code Review) April 15, 2024

April 15, 2024

Attention is currently required from: Angel Pons, Felix Singer, Joel Linn, Matt DeVillier, Nicholas Chin, Nico Huber. Hello Angel Pons, Felix Singer, Matt DeVillier, Nicholas Chin, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81368?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Felix Singer, Code-Review+2 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) ...................................................................... mb/hp: Add Pro 3500 series (Sandy/Ivy Bridge) This is another readily available (used market) system. Based on autoport. * All peripherals should work. * Automatic fan control as well as S3 are working. * The board was tested to boot Linux and Windows. EHCI debug is untested. * When using MrChromebox edk2 with secure boot build in, the board will hang on each boot for about 20 seconds before continuing. There are some quirks for doing the first flash, see the documentation. Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Signed-off-by: Joel Linn <jl(a)conductive.de> --- A Documentation/mainboard/hp/pro_3500_series.md A Documentation/mainboard/hp/pro_3500_series_flash.avif A Documentation/mainboard/hp/pro_3500_series_jumper.avif M Documentation/mainboard/index.md A src/mainboard/hp/pro_3500_series/Kconfig A src/mainboard/hp/pro_3500_series/Kconfig.name A src/mainboard/hp/pro_3500_series/Makefile.mk A src/mainboard/hp/pro_3500_series/acpi/ec.asl A src/mainboard/hp/pro_3500_series/acpi/platform.asl A src/mainboard/hp/pro_3500_series/acpi/superio.asl A src/mainboard/hp/pro_3500_series/acpi_tables.c A src/mainboard/hp/pro_3500_series/board_info.txt A src/mainboard/hp/pro_3500_series/common_defines.h A src/mainboard/hp/pro_3500_series/data.vbt A src/mainboard/hp/pro_3500_series/devicetree.cb A src/mainboard/hp/pro_3500_series/dsdt.asl A src/mainboard/hp/pro_3500_series/early_init.c A src/mainboard/hp/pro_3500_series/gma-mainboard.ads A src/mainboard/hp/pro_3500_series/gpio.c A src/mainboard/hp/pro_3500_series/hda_verb.c A src/mainboard/hp/pro_3500_series/led.c A src/mainboard/hp/pro_3500_series/led.h A src/mainboard/hp/pro_3500_series/mainboard.c A src/mainboard/hp/pro_3500_series/smihandler.c 24 files changed, 709 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/81368/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81368?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idf793fe915096cf2553572964faec5c7f8526b9a Gerrit-Change-Number: 81368 Gerrit-PatchSet: 6 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newpatchset

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