May 2016 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: soc/intel/apollolake: Increase heap size to 64 KiB
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15038 -gerrit commit 58ea96793cf9f917911d1f45f9483d656119804b Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Wed Apr 20 15:30:16 2016 -0700 soc/intel/apollolake: Increase heap size to 64 KiB We run out of heap space (current default is 16 KiB) when NHLT blobs are loaded. Change-Id: I5d4872178d6e8700da89bf93e8d48cf46c4cd85b Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..0b9c05a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,8 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config HEAP_SIZE + hex + default 0x10000 + endif

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Patch set updated for coreboot: apollolake: Add ACPI device for audio controller
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026 -gerrit commit a6b32dfcb5c7de24277b958c6bcd0e2343aa3321 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Mar 8 17:33:29 2016 -0800 apollolake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/pch.asl | 23 ++++++++ src/soc/intel/apollolake/acpi/pch_hda.asl | 89 +++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pch.asl b/src/soc/intel/apollolake/acpi/pch.asl new file mode 100644 index 0000000..8bcbfd7 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* PCH HDA */ +#include "pch_hda.asl" diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000..ac027e6 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} +

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit e4fd95a5849b1960984f884b3aa7d51491932e33 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 +++ src/mainboard/intel/amenia/dsdt.asl | 1 + src/mainboard/intel/amenia/mainboard.c | 90 +++++++++++++++++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..1be4a9f 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -29,6 +29,7 @@ DefinitionBlock( { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch.asl } } /* Mainboard Specific devices */ diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..40a65ff 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <pc80/keyboard.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +95,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -114,6 +119,9 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ @@ -129,15 +137,95 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; + +struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); mainboard_ec_init(); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

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Patch set updated for coreboot: apollolake/amenia: Adding NHLA and NHLL
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 4d537f484de58fc08dd4ba017e5ec54a7d724bf1 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Adding NHLA and NHLL Address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 3 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 1be4a9f..95ca98b 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: drivers/intel/audio: Add common NHLT audio for Intel platforms
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit f623777bdfd03a541e828947b970abf7901ee314 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 15:53:41 2016 -0700 drivers/intel/audio: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the intel SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/drivers/intel/audio/Kconfig | 48 +++++++++++++ src/drivers/intel/audio/Makefile.inc | 43 +++++++++++ src/drivers/intel/audio/dmic.c | 53 ++++++++++++++ src/drivers/intel/audio/headset.c | 60 ++++++++++++++++ src/drivers/intel/audio/include/drivers/audio.h | 59 +++++++++++++++ src/drivers/intel/audio/nhlt.c | 95 +++++++++++++++++++++++++ src/drivers/intel/audio/speaker.c | 40 +++++++++++ 7 files changed, 398 insertions(+) diff --git a/src/drivers/intel/audio/Kconfig b/src/drivers/intel/audio/Kconfig new file mode 100644 index 0000000..fdc494c --- /dev/null +++ b/src/drivers/intel/audio/Kconfig @@ -0,0 +1,48 @@ +config USE_COMMON_AUDIO + bool + default n + help + Build support for drivers audio code, common to intel + platforms that use NHLT. + +config AUDIO_DMIC_2CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config AUDIO_DMIC_2CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 32B DMIC array. + +config AUDIO_DMIC_4CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + +config AUDIO_DMIC_4CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 32B DMIC array. + +config AUDIO_HEADSET + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for headset codec. + +config AUDIO_SPEAKER + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for speaker amplifier. diff --git a/src/drivers/intel/audio/Makefile.inc b/src/drivers/intel/audio/Makefile.inc new file mode 100644 index 0000000..6bea190 --- /dev/null +++ b/src/drivers/intel/audio/Makefile.inc @@ -0,0 +1,43 @@ +ifeq ($(CONFIG_USE_COMMON_AUDIO),y) +ramstage-y += nhlt.c +ramstage-y += dmic.c +ramstage-y += headset.c +ramstage-y += speaker.c + +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin +DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin + +HEADSET = headset-2ch-48khz-24b.bin + +SPEAKER_RENDER = max98357-render-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_32B) += $(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_32B) += $(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_HEADSET) += $(HEADSET) +$(HEADSET)-file := $(NHLT_BLOB_PATH)/$(HEADSET) +$(HEADSET)-type := raw + +cbfs-files-$(CONFIG_AUDIO_SPEAKER) += $(SPEAKER_RENDER) +$(SPEAKER_RENDER)-file := $(NHLT_BLOB_PATH)/$(SPEAKER_RENDER) +$(SPEAKER_RENDER)-type := raw +endif + +CPPFLAGS_common += -I$(src)/drivers/intel/audio/include diff --git a/src/drivers/intel/audio/dmic.c b/src/drivers/intel/audio/dmic.c new file mode 100644 index 0000000..fe11d51 --- /dev/null +++ b/src/drivers/intel/audio/dmic.c @@ -0,0 +1,53 @@ + /* + * This file is part of the coreboot project. + * + * Copyright 2016 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <string.h> + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_cfg, int fmt_size, int num_channels) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + const struct nhlt_format_config *formats; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + formats = dmic_ch_cfg; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, formats, fmt_size); +} + diff --git a/src/drivers/intel/audio/headset.c b/src/drivers/intel/audio/headset.c new file mode 100644 index 0000000..68acee2 --- /dev/null +++ b/src/drivers/intel/audio/headset.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <console/console.h> + +/* The same DSP firmwware settings are used for both the capture and + * render endpoints. */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + /* The headphone codec has headphones and a mic. Both the capture and + * render endpoints occupy the same virtual slot. */ + const void *fmt_cfg = headset_cfg; + size_t fmt_sz = fmt_size; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + /* Capture Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +} diff --git a/src/drivers/intel/audio/include/drivers/audio.h b/src/drivers/intel/audio/include/drivers/audio.h new file mode 100644 index 0000000..caf1edc --- /dev/null +++ b/src/drivers/intel/audio/include/drivers/audio.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_AUDIO_H_ +#define _DRIVERS_AUDIO_H_ + +#include <nhlt.h> + +/* + * Skylake NHLT device and hardware link types. These values are to be used + * with nhlt_soc_add_endpoint(). + */ + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, /* Only Bluetooth supported on SSP2. */ + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_config, int cfg_size, int num_channels); + +/* + * Add headset codec on provided SSP link. Return 0 on succes, < 0 on error. + */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +/* + * Add speaker amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +#endif diff --git a/src/drivers/intel/audio/nhlt.c b/src/drivers/intel/audio/nhlt.c new file mode 100644 index 0000000..0f8e6e1 --- /dev/null +++ b/src/drivers/intel/audio/nhlt.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <soc/acpi.h> +#include <drivers/audio.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + /* Check link type and device type. */ + switch (soc_hwintf) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP5: + case AUDIO_LINK_SSP2: + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + /* Only DMIC devices on DMIC links. */ + if (soc_devtype != AUDIO_DEV_DMIC) + return NULL; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return NULL; + } + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP links are the hardware port ids proper. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize(nhlt, acpi_addr); +} diff --git a/src/drivers/intel/audio/speaker.c b/src/drivers/intel/audio/speaker.c new file mode 100644 index 0000000..63dba66 --- /dev/null +++ b/src/drivers/intel/audio/speaker.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> + +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, speaker_cfg, fmt_size)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

1 0

Patch set updated for coreboot: apollolake: Add ACPI device for audio controller
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026 -gerrit commit 49635cc3004381ec59c77e2c40f2b985c95e9791 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Mar 8 17:33:29 2016 -0800 apollolake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/pch.asl | 23 ++++++++ src/soc/intel/apollolake/acpi/pch_hda.asl | 89 +++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pch.asl b/src/soc/intel/apollolake/acpi/pch.asl new file mode 100644 index 0000000..8bcbfd7 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* PCH HDA */ +#include "pch_hda.asl" diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000..ac027e6 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} +

1 0

Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit a755fad7f6c2f5018f9d85b4f08b76945faee022 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 +++ src/mainboard/intel/amenia/dsdt.asl | 1 + src/mainboard/intel/amenia/mainboard.c | 90 +++++++++++++++++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..1be4a9f 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -29,6 +29,7 @@ DefinitionBlock( { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch.asl } } /* Mainboard Specific devices */ diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..40a65ff 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <pc80/keyboard.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +95,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -114,6 +119,9 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ @@ -129,15 +137,95 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; + +struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); mainboard_ec_init(); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

1 0

Patch set updated for coreboot: apollolake/amenia: Adding NHLA and NHLL
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 4bc6aa863e603a9ab8da37ece872b2be8f7810c3 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Adding NHLA and NHLL Address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 3 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 1be4a9f..95ca98b 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

1 0

Patch set updated for coreboot: drivers/intel/audio: Add common NHLT audio for Intel platforms
by Saurabh Satija June 1, 2016

June 1, 2016

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit 597f35f6507b40b4b20a704f8ac6cf58714519ef Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 15:53:41 2016 -0700 drivers/intel/audio: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the intel SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/drivers/intel/audio/Kconfig | 48 +++++++++++++ src/drivers/intel/audio/Makefile.inc | 43 +++++++++++ src/drivers/intel/audio/dmic.c | 53 ++++++++++++++ src/drivers/intel/audio/headset.c | 60 ++++++++++++++++ src/drivers/intel/audio/include/drivers/audio.h | 59 +++++++++++++++ src/drivers/intel/audio/nhlt.c | 95 +++++++++++++++++++++++++ src/drivers/intel/audio/speaker.c | 40 +++++++++++ 7 files changed, 398 insertions(+) diff --git a/src/drivers/intel/audio/Kconfig b/src/drivers/intel/audio/Kconfig new file mode 100644 index 0000000..fdc494c --- /dev/null +++ b/src/drivers/intel/audio/Kconfig @@ -0,0 +1,48 @@ +config USE_COMMON_AUDIO + bool + default n + help + Build support for drivers audio code, common to intel + platforms that use NHLT. + +config AUDIO_DMIC_2CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config AUDIO_DMIC_2CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 32B DMIC array. + +config AUDIO_DMIC_4CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + +config AUDIO_DMIC_4CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 32B DMIC array. + +config AUDIO_HEADSET + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for headset codec. + +config AUDIO_SPEAKER + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for speaker amplifier. diff --git a/src/drivers/intel/audio/Makefile.inc b/src/drivers/intel/audio/Makefile.inc new file mode 100644 index 0000000..6bea190 --- /dev/null +++ b/src/drivers/intel/audio/Makefile.inc @@ -0,0 +1,43 @@ +ifeq ($(CONFIG_USE_COMMON_AUDIO),y) +ramstage-y += nhlt.c +ramstage-y += dmic.c +ramstage-y += headset.c +ramstage-y += speaker.c + +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin +DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin + +HEADSET = headset-2ch-48khz-24b.bin + +SPEAKER_RENDER = max98357-render-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_32B) += $(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_32B) += $(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_HEADSET) += $(HEADSET) +$(HEADSET)-file := $(NHLT_BLOB_PATH)/$(HEADSET) +$(HEADSET)-type := raw + +cbfs-files-$(CONFIG_AUDIO_SPEAKER) += $(SPEAKER_RENDER) +$(SPEAKER_RENDER)-file := $(NHLT_BLOB_PATH)/$(SPEAKER_RENDER) +$(SPEAKER_RENDER)-type := raw +endif + +CPPFLAGS_common += -I$(src)/drivers/intel/audio/include diff --git a/src/drivers/intel/audio/dmic.c b/src/drivers/intel/audio/dmic.c new file mode 100644 index 0000000..fe11d51 --- /dev/null +++ b/src/drivers/intel/audio/dmic.c @@ -0,0 +1,53 @@ + /* + * This file is part of the coreboot project. + * + * Copyright 2016 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <string.h> + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_cfg, int fmt_size, int num_channels) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + const struct nhlt_format_config *formats; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + formats = dmic_ch_cfg; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, formats, fmt_size); +} + diff --git a/src/drivers/intel/audio/headset.c b/src/drivers/intel/audio/headset.c new file mode 100644 index 0000000..68acee2 --- /dev/null +++ b/src/drivers/intel/audio/headset.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <console/console.h> + +/* The same DSP firmwware settings are used for both the capture and + * render endpoints. */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + /* The headphone codec has headphones and a mic. Both the capture and + * render endpoints occupy the same virtual slot. */ + const void *fmt_cfg = headset_cfg; + size_t fmt_sz = fmt_size; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + /* Capture Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +} diff --git a/src/drivers/intel/audio/include/drivers/audio.h b/src/drivers/intel/audio/include/drivers/audio.h new file mode 100644 index 0000000..caf1edc --- /dev/null +++ b/src/drivers/intel/audio/include/drivers/audio.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_AUDIO_H_ +#define _DRIVERS_AUDIO_H_ + +#include <nhlt.h> + +/* + * Skylake NHLT device and hardware link types. These values are to be used + * with nhlt_soc_add_endpoint(). + */ + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, /* Only Bluetooth supported on SSP2. */ + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_config, int cfg_size, int num_channels); + +/* + * Add headset codec on provided SSP link. Return 0 on succes, < 0 on error. + */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +/* + * Add speaker amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +#endif diff --git a/src/drivers/intel/audio/nhlt.c b/src/drivers/intel/audio/nhlt.c new file mode 100644 index 0000000..0f8e6e1 --- /dev/null +++ b/src/drivers/intel/audio/nhlt.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <soc/acpi.h> +#include <drivers/audio.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + /* Check link type and device type. */ + switch (soc_hwintf) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP5: + case AUDIO_LINK_SSP2: + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + /* Only DMIC devices on DMIC links. */ + if (soc_devtype != AUDIO_DEV_DMIC) + return NULL; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return NULL; + } + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP links are the hardware port ids proper. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize(nhlt, acpi_addr); +} diff --git a/src/drivers/intel/audio/speaker.c b/src/drivers/intel/audio/speaker.c new file mode 100644 index 0000000..63dba66 --- /dev/null +++ b/src/drivers/intel/audio/speaker.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> + +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, speaker_cfg, fmt_size)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

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New patch to review for coreboot: libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults
by Martin Roth June 1, 2016

June 1, 2016

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15036 -gerrit commit 7a29c2908f0c6d1b2cd87dbbdbdb280d64d1cd45 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon May 16 16:37:56 2016 -0700 libpayload: Reintroduce CONFIG_LP_CHROMEOS to set suitable defaults Chrome OS builds always have some inherent differences to "standard" libpayload configurations: they don't want to use curses or things like storage drivers, they always use the coreboot framebuffer and USB, etc. This patch reintroduces CONFIG_LP_CHROMEOS as an option that only affects Kconfig defaults. This allows Chrome OS builds to select most of what they need in one go and reduces board-specific .config files to only the options that are really specific to that board. Also restricts the 8250_SERIAL_CONSOLE Kconfig to only default to yes on x86 boards, which probably makes sense for all of libpayload (some but far from all ARM boards use 8250-compatible UARTs, and we should probably not default a platform option unless it's going to be correct with very high probability). BRANCH=None BUG=None TEST=Built and booted Jerry and Oak. Change-Id: Ie0c0593ffd399608d2cbfb83d20891f6f1864915 Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Commit-Id: e558f59 Original-Change-Id: I609637cd2ea7dfb4558aa3c04c90b64038c9ab57 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347970 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- payloads/libpayload/Kconfig | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 20f10ee..951d757 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -34,6 +34,7 @@ menu "Generic Options" config GPL bool "GPLv2-licensed Options" + default y if CHROMEOS default n help Prompt for options that will build code licensed under the GNU General @@ -55,6 +56,12 @@ config DEVELOPER Prompt for developer options. These options are only interesting for libpayload developers. +config CHROMEOS + bool "Chrome OS Options" + default n + help + Select configuration defaults appropriate for Chrome OS boards. + choice prompt "Compiler to use" default COMPILER_GCC @@ -117,7 +124,7 @@ endchoice config MULTIBOOT bool "Multiboot header support" depends on ARCH_X86 - default y + default y if !CHROMEOS config HEAP_SIZE int "Heap size" @@ -158,7 +165,7 @@ config LIBC config CURSES bool "Build a curses library" - default y + default y if !CHROMEOS choice prompt "Curses implementation" @@ -208,6 +215,7 @@ menu "Console Options" config SKIP_CONSOLE_INIT bool "Skip initializing the consoles at startup" + default y if CHROMEOS default n help Normally, libpayload will initialize console input/output on startup @@ -225,7 +233,7 @@ config SERIAL_CONSOLE config 8250_SERIAL_CONSOLE bool "8250-compatible serial port driver (including IO and MMIO)" depends on SERIAL_CONSOLE - default y + default y if ARCH_X86 config S5P_SERIAL_CONSOLE bool "Exynos SOC, S5P compatible serial port driver" @@ -289,7 +297,7 @@ config VIDEO_CONSOLE config VGA_VIDEO_CONSOLE bool "VGA video console driver" depends on ARCH_X86 && VIDEO_CONSOLE - default y + default y if !CHROMEOS config GEODELX_VIDEO_CONSOLE bool "Geode LX video console driver" @@ -299,6 +307,7 @@ config GEODELX_VIDEO_CONSOLE config COREBOOT_VIDEO_CONSOLE bool "coreboot video console driver" depends on VIDEO_CONSOLE && !GEODELX_VIDEO_CONSOLE + default y if CHROMEOS default n help Say Y here if coreboot switched to a graphics mode and @@ -352,11 +361,11 @@ config RTC_PORT_EXTENDED_VIA config SPEAKER bool "Support for PC speaker" depends on ARCH_X86 - default y + default y if !CHROMEOS config STORAGE bool "Support for storage devices" - default y + default y if !CHROMEOS help Select this option if you want support for storage devices (like hard drives, memory sticks or optical drives). @@ -513,7 +522,7 @@ config USB config USB_UHCI bool "Support for USB UHCI controllers" depends on USB && ARCH_X86 - default y + default y if !CHROMEOS help Select this option if you are going to use USB 1.1 on an Intel based system. @@ -521,7 +530,7 @@ config USB_UHCI config USB_OHCI bool "Support for USB OHCI controllers" depends on USB - default y + default y if !CHROMEOS help Select this option if you are going to use USB 1.1 on a non-Intel based system. @@ -529,14 +538,14 @@ config USB_OHCI config USB_EHCI bool "Support for USB EHCI controllers" depends on USB - default y + default y if !CHROMEOS help Select this option if you want to use USB 2.0 config USB_XHCI bool "Support for USB xHCI controllers" depends on USB - default y + default y if !CHROMEOS help Select this option if you want to use USB 3.0

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