January 2015 - coreboot-gerrit

Patch set updated for coreboot: 4bf8980 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.
by Vladimir Serbinenko Jan. 31, 2015

Jan. 31, 2015

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8312 -gerrit commit 4bf89808965e5ac11941e2c9c2989552c6cbfbcf Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 31 17:45:50 2015 +0100 bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3. Change-Id: Ica1cc90715c1810668e3f4f7282e5757a5688483 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/bd82x6x/chip.h | 5 +++++ src/southbridge/intel/bd82x6x/usb_xhci.c | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 290bb05..f4be82d 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -89,6 +89,11 @@ struct southbridge_intel_bd82x6x_config { int docking_supported; uint8_t pcie_hotplug_map[8]; + + /* Ports which can be routed to either EHCI or xHCI. */ + uint32_t xhci_switchable_ports; + /* Ports which support SuperSpeed (USB 3.0 additional lanes). */ + uint32_t superspeed_capable_ports; }; #endif /* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */ diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 19c419f..eb89a7d 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -29,6 +29,7 @@ static void usb_xhci_init(struct device *dev) { u32 reg32; + struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "XHCI: Setting up controller.. "); @@ -37,6 +38,9 @@ static void usb_xhci_init(struct device *dev) reg32 |= 1; pci_write_config32(dev, 0x44, reg32); + pci_write_config32(dev, 0xd4, config->xhci_switchable_ports); + pci_write_config32(dev, 0xdc, config->superspeed_capable_ports); + /* Enable clock gating */ reg32 = pci_read_config32(dev, 0x40); reg32 &= ~((1 << 20) | (1 << 21));

1 0

Patch set updated for coreboot: f8673c8 lenovo/x230: Set usb2_3_os_switchable_map.
by Vladimir Serbinenko Jan. 31, 2015

Jan. 31, 2015

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8313 -gerrit commit f8673c886084b0ec00d7470f7abce387afa95e0e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 31 17:46:29 2015 +0100 lenovo/x230: Set usb2_3_os_switchable_map. Fixes USB3 ports degraded to USB2 speeds. Change-Id: Ie71c9fb6e52a3e72bb1e61351ad1cc0492d93cbc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x230/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5130410..3a05b5a 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -67,6 +67,9 @@ chip northbridge/intel/sandybridge register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" + register "xhci_switchable_ports" = "0xf" + register "superspeed_capable_ports" = "0xf" + # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "1" register "c2_latency" = "101" # c2 not supported

1 0

Patch merged into coreboot/master: e1e11e6 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP
by gerrit＠coreboot.org Jan. 31, 2015

Jan. 31, 2015

the following patch was just integrated into master: commit e1e11e63afab8e461ac7e6466c9a7f9f47a10702 Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> Reviewed-on: http://review.coreboot.org/8107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/8107 for details. -gerrit

1 0

Patch set updated for coreboot: e045006 winent/mb6047: symbolic arguments for acpi_create_madt_lapic_nmis()
by Jonathan A. Kollasch Jan. 31, 2015

Jan. 31, 2015

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8317 -gerrit commit e04500673cc2f8911295c4bbcc13ac1e39f636c5 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jan 31 14:18:55 2015 -0600 winent/mb6047: symbolic arguments for acpi_create_madt_lapic_nmis() Change-Id: I19af5f36a55d6c2906d603e940b3aadd2ca97140 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/acpi_tables.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 15443ee..900d25c 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -51,14 +51,10 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ - /* create all subtables for processors */ /* acpi_create_madt_lapic_nmis returns current, not size. */ - current = acpi_create_madt_lapic_nmis(current, 5, 1); + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); return current; }

1 0

Patch set updated for coreboot: f0292f0 winent/mb6047: use correct ACPI SCI interupt trigger
by Jonathan A. Kollasch Jan. 31, 2015

Jan. 31, 2015

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8315 -gerrit commit f0292f09513f13d0b666a631a3cde8825274da63 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jan 31 14:13:27 2015 -0600 winent/mb6047: use correct ACPI SCI interupt trigger Change-Id: I245c0afb66f3a29b5acb40e8d949d8b1aa08cd73 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/acpi_tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 0c7c3a5..2b1084c 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -49,7 +49,7 @@ unsigned long acpi_fill_madt(unsigned long current) /* IRQ9 */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_LOW); + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); /* 0: mean bus 0--->ISA */ /* 0: PIC 0 */

1 0

Patch merged into coreboot/master: 9cd1553 FSP platforms: Clear area in CAR for cbmem
by gerrit＠coreboot.org Jan. 31, 2015

Jan. 31, 2015

the following patch was just integrated into master: commit 9cd155334baa28331f2cf2e6e7bf57c912d7a731 Author: Martin Roth <gaumless(a)gmail.com> Date: Sun Jan 11 14:58:47 2015 -0700 FSP platforms: Clear area in CAR for cbmem This patch clears the CAR area. The FSP loads the entire CAR area with a pattern instead of clearing it. At least the cbmem area needs to be cleared or cbmem will not use it. Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/8195 Reviewed-by: Aaron Durbin <adurbin(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8195 for details. -gerrit

1 0

Patch set updated for coreboot: 23500d5 winent/mb6047: drop inaccurate comment in acpi_tables.c
by Jonathan A. Kollasch Jan. 31, 2015

Jan. 31, 2015

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8314 -gerrit commit 23500d5b24fe92e43eefdc1dad525f8e18fe9bd1 Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sat Jan 31 14:10:32 2015 -0600 winent/mb6047: drop inaccurate comment in acpi_tables.c Change-Id: Ib0bb8bed32b96a5f7fd48407bd111972f89e7907 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/mainboard/winent/mb6047/acpi_tables.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/winent/mb6047/acpi_tables.c b/src/mainboard/winent/mb6047/acpi_tables.c index 15443ee..0c7c3a5 100644 --- a/src/mainboard/winent/mb6047/acpi_tables.c +++ b/src/mainboard/winent/mb6047/acpi_tables.c @@ -1,5 +1,5 @@ /* - * Island Aruma ACPI support + * ACPI support * written by Stefan Reinauer <stepan(a)openbios.org> * (C) 2005 Stefan Reinauer *

1 0

Patch set updated for coreboot: 8853dcf nvidia/ck804: make Message Signaled Interrupts work
by Jonathan A. Kollasch Jan. 31, 2015

Jan. 31, 2015

Jonathan A. Kollasch (jakllsch(a)kollasch.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8276 -gerrit commit 8853dcfc99e5c8c8dd0b385089b281bcfacf081e Author: Jonathan A. Kollasch <jakllsch(a)kollasch.net> Date: Sun Jan 25 12:57:43 2015 -0600 nvidia/ck804: make Message Signaled Interrupts work Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable HT MSI Mapping so that MSIs work. Prior to this change PCIe devices downstream of the CK804 with MSI enabled would fail to actually assert their interrupt. Tested on msi/ms7135 and winent/mb6047 running Debian GNU/Linux 7.0 (wheezy). Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850 Signed-off-by: Jonathan A. Kollasch <jakllsch(a)kollasch.net> --- src/southbridge/nvidia/ck804/ht.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/src/southbridge/nvidia/ck804/ht.c b/src/southbridge/nvidia/ck804/ht.c index 41e2998..f5ea249 100644 --- a/src/southbridge/nvidia/ck804/ht.c +++ b/src/southbridge/nvidia/ck804/ht.c @@ -52,11 +52,21 @@ unsigned long acpi_fill_mcfg(unsigned long current) #endif +static void ht_init(struct device *dev) +{ + u32 htmsi; + + /* Enable HT MSI Mapping in capability register */ + htmsi = pci_read_config32(dev, 0xe0); + htmsi |= (1 << 16); + pci_write_config32(dev, 0xe0, htmsi); +} + static struct device_operations ht_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = 0, + .init = ht_init, .scan_bus = 0, .ops_pci = &ck804_pci_ops, };

1 0

Patch merged into coreboot/master: 4e6f0c2 asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devices
by gerrit＠coreboot.org Jan. 31, 2015

Jan. 31, 2015

the following patch was just integrated into master: commit 4e6f0c289b533155c1e447eedec862523bbf04a1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 30 23:48:52 2015 -0600 asus/kfsn4-dre: Increase maximum logical CPUs for Istanbul devices Test: Single Opteron 2419 with 1GB RAM in slot A1 Booted Ubuntu Linux 14.04 and verified all 6 cores were visible Brief stress test of all 6 cores simultaneously Verified proper ACPI power states for all 6 cores Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8311 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8311 for details. -gerrit

1 0

Patch merged into coreboot/master: 9c81066 cpu/amd (non-AGESA): Fix AP crash during microcode version lookup
by gerrit＠coreboot.org Jan. 31, 2015

Jan. 31, 2015

the following patch was just integrated into master: commit 9c8106696ec7cddfda1c4881145ee385eeef92d8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jan 30 23:47:45 2015 -0600 cpu/amd (non-AGESA): Fix AP crash during microcode version lookup Move mapping tables to struct and prevent OOB array access that was crashing the APs during CAR initialization. Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8310 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8310 for details. -gerrit

1 0