March 2014 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: d618e73 vendorcode/amd/agesa/fam14: Build as a static library
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5441 -gerrit commit d618e730607f0db192a99578c3a633f9b0b80ddb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 1 04:13:26 2014 +1100 vendorcode/amd/agesa/fam14: Build as a static library Following the same reasoning as commit HASHHERE vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 257 ----------------------------- src/vendorcode/amd/agesa/f14/Makefile.inc | 262 +++++++++++++++++++++++++++++- 2 files changed, 261 insertions(+), 258 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 57631b2..c3f1ecc 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -20,262 +20,6 @@ ramstage-y += chip_name.c ramstage-y += model_14_init.c -AGESA_ROOT = ../../../../vendorcode/amd/agesa/f14 - -agesa_lib_src = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbSmu.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbLclkDpm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbFuseTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Pstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14C6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnmcton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbUtilitiesFam14.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnidendimmon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnoton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mndcton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxGmcInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Dmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnregon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtEnvPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpson3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEarlyPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtLatePost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbFam14.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/ON/mmflowon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14MsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtLatePost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxRegisterAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnphyon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mauon3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mason3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieMiscLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbSmuLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c - -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic @@ -283,4 +27,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm - diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 6a266ec..f457277 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -68,4 +68,264 @@ export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) -####################################################################### \ No newline at end of file +####################################################################### + +classes-y += libagesa + +libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c +libagesa-y += Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c +libagesa-y += Proc/GNB/Nb/NbInitAtPost.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +libagesa-y += Proc/CPU/Family/0x14/F14IoCstate.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/Mem/NB/ON/mnprotoon.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c +libagesa-y += Proc/CPU/cpuInitEarlyTable.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbSmu.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtEnv.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtPost.c +libagesa-y += Proc/GNB/Nb/Feature/NbLclkDpm.c +libagesa-y += Proc/GNB/Nb/Feature/NbFuseTable.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c +libagesa-y += Proc/GNB/Common/GnbLibFeatures.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Pstate.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Family/0x14/F14C6State.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/CPU/Family/0x14/cpuCommonF14Utilities.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/GNB/GnbInitAtReset.c +libagesa-y += Proc/Mem/NB/ON/mnmcton.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/GNB/GnbInitAtEarly.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/HT/Fam14/htNbUtilitiesFam14.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerPlane.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14LowPowerInit.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/ON/mnflowon.c +libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa-y += Proc/GNB/PCIe/PcieInit.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtMidPost.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14CacheDefaults.c +libagesa-y += Proc/Mem/Ps/ON/mpuon3.c +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cahaltasm.S +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnPciTables.c +libagesa-y += Proc/GNB/PCIe/PciePortInit.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtPost.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/Mem/Tech/mttsrc.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/Mem/NB/ON/mnidendimmon.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Utilities.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/GNB/Gfx/GfxStrapsInit.c +libagesa-y += Proc/GNB/Nb/NbInitAtEarly.c +libagesa-y += Lib/amdlib.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c +libagesa-y += Proc/GNB/GnbInitAtLate.c +libagesa-y += Proc/Mem/NB/ON/mnoton.c +libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa-y += Proc/GNB/Nb/NbInit.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/Mem/NB/ON/mndcton.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/GNB/Gfx/GfxGmcInit.c +libagesa-y += Proc/CPU/cpuBrandId.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/GNB/GnbInitAtPost.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerCheck.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Dmi.c +libagesa-y += Proc/Mem/NB/ON/mnregon.c +libagesa-y += Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtEnvPost.c +libagesa-y += Proc/CPU/Feature/cpuHwC1e.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Lib/helper.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Ps/ON/mpson3.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PciTables.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/GNB/GnbInitAtMid.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtEarlyPost.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/GNB/Nb/NbInitAtLatePost.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/HT/Fam14/htNbFam14.c +libagesa-y += Proc/GNB/Gfx/GfxConfigData.c +libagesa-y += Proc/Mem/Main/ON/mmflowon.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14MsrTables.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtLatePost.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/GNB/Gfx/GfxRegisterAcc.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/GNB/Nb/NbInitAtReset.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnCpb.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/GNB/GnbInitAtEnv.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Proc/Mem/NB/ON/mnon.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/Mem/NB/ON/mnphyon.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14BrandId.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/GNB/Nb/NbConfigData.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Ardk/ON/mauon3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Ardk/ON/mason3.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/NB/ON/mnS3on.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/GNB/PCIe/PcieLateInit.c +libagesa-y += Proc/GNB/PCIe/PciePortLateInit.c +libagesa-y += Proc/GNB/PCIe/PcieMiscLib.c +libagesa-y += Proc/GNB/Nb/NbSmuLib.c +libagesa-y += Proc/GNB/Nb/NbInitAtEnv.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbServices.c +libagesa-y += Proc/GNB/Gfx/GfxLib.c +libagesa-y += Proc/GNB/Nb/NbPowerMgmt.c +libagesa-y += Proc/Recovery/HT/htInitReset.c +libagesa-y += Proc/Mem/Main/mu.c + +$(obj)/libagesa.fam14.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/libagesa.fam14.a +ramstage-libs += $(obj)/libagesa.fam14.a

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Patch set updated for coreboot: c255497 x86/Makefile: Allow addition of link libraries for rom/ramstage
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5425 -gerrit commit c255497ef8a5bfd34972d9fccc323a47b9af3ced Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Mar 29 13:01:11 2014 -0500 x86/Makefile: Allow addition of link libraries for rom/ramstage This is useful, for example, when using stage-independent code, as it allows us to compile that code only once. It's also useful for vendor code which needs wonky compiler definitions and include paths which we'd rather not include in the other files. Subsequent patches will make use of this when lib-izing AGESA. Change-Id: Ifb0c5d353bf09d23864270b9eefb6b75fd86e6cb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index acb4e98..107abb4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -207,6 +207,8 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug ################################################################################ # Build the coreboot_ram (stage 2) +ramstage-libs := + ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y) $(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE))) @@ -227,12 +229,12 @@ endif endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) $$(ramstage-libs) @printf " CC $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group + $(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(ramstage-objs) $(ramstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif ################################################################################ @@ -404,24 +406,26 @@ endif ################################################################################ # Build the romstage -$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld +romstage-libs := + +$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_null.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \ echo "Forbidden global variables in romstage:"; \ $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" = y; \ else true; fi -$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld +$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld $$(romstage-libs) @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld + $(LD) -nostdlib -nostartfiles -static -o $@ -L$(obj) --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) --end-group -T $(objgenerated)/romstage_xip.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_xip.ld -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,--start-group $(romstage-objs) $(romstage-libs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif $(objgenerated)/romstage_null.ld: $$(ldscripts) $(obj)/ldoptions

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New patch to review for coreboot: 19fe5a6 vendorcode/amd/agesa/fam14: Build as a static library
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5441 -gerrit commit 19fe5a623a2010d4b8cade683697b8972d046c86 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 1 04:13:26 2014 +1100 vendorcode/amd/agesa/fam14: Build as a static library Following the same reasoning as commit HASHHERE vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/agesa/family14/Makefile.inc | 257 ----------------------------- src/vendorcode/amd/agesa/f14/Makefile.inc | 262 +++++++++++++++++++++++++++++- 2 files changed, 261 insertions(+), 258 deletions(-) diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 57631b2..c3f1ecc 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -20,262 +20,6 @@ ramstage-y += chip_name.c ramstage-y += model_14_init.c -AGESA_ROOT = ../../../../vendorcode/amd/agesa/f14 - -agesa_lib_src = $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib/GnbLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14IoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuIoCstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnprotoon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuInitEarlyTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbSmu.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbLclkDpm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Feature/NbFuseTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Common/GnbLibFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Pstate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuC6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/F14C6State.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuCommonF14Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttml.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtrci3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnmcton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttdimbt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtsdi3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mthdi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnfeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbUtilitiesFam14.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBist.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3/mflvddr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerPlane.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14LowPowerInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnreg.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnflowon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV/mfchi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtMidPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14CacheDefaults.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpuon3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cahaltasm.S -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnPciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatureLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttoptsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfParallelTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmEcc.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/Dispatcher.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/MEMCLR/mfmemclr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuDmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttsrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnmct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceNonCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnidendimmon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSrat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3LateRestore.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Table.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Utilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterface.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxStrapsInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEarly.c -agesa_lib_src += $(AGESA_ROOT)/Lib/amdlib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCacheFlushOnHalt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuCpb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/minit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnoton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN/mfintlvrn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM/mfidendimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmflow.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ma.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonInits.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateLeveling.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mndcton.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxGmcInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuBrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnphy.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmConditionalPso.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CommonReturns.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitResume.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PowerCheck.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14Dmi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnregon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitEarly.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuFamilyTranslation.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPostInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mn.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxInitAtEnvPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuHwC1e.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/CreateStruct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuWhea.c -agesa_lib_src += $(AGESA_ROOT)/Lib/helper.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV/mfcsi.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/DMI/mfDMI.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/ON/mpson3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdLateRunApTask.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtMultiSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmUmaAlloc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14PciTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuPowerMgmtSingleSocket.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mt3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmExcludeDimm.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtEarlyPost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceGeneral.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/S3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuFeatures.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ps/mp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mdef.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mtthrc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuGeneralServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNb.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuSlit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ECC/mfemp.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtLatePost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmNodeInterleave.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/Fam14/htNbFam14.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/ON/mmflowon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14MsrTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieInitAtLatePost.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttEdgeDetect.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxRegisterAcc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitLate.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htFeat.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/ON/F14OnCpb.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/hobTransfer.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuApicUtilities.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/GnbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEventLog.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htInterfaceCoherent.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/muc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmLvDdr3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuMicrocodePatch.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/mttecc.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c -agesa_lib_src += $(AGESA_ROOT)/Legacy/Proc/agesaCallouts.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL/mfodthermal.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/PARTRN/mfStandardTraining.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mndct.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmOnlineSpare.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuEarlyInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnphyon.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/merrhdl.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdS3Save.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtspd3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Family/0x14/cpuF14BrandId.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htMain.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/cpuWarmReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbConfigData.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttwl3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/Feature/cpuPstateGather.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mtot3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mmMemClr.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mauon3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/TABLE/mftds.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Ardk/ON/mason3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Feat/S3/mfs3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/HT/htNotify.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mnS3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/CPU/heapManager.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Tech/DDR3/mttecc3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/ON/mnS3on.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/AmdInitMid.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/NB/mntrain3.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/Family/0x14/F14GfxServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3SaveState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Common/S3RestoreState.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PciePortLateInit.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/PCIe/PcieMiscLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbSmuLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbInitAtEnv.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/Family/0x14/F14NbServices.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Gfx/GfxLib.c -agesa_lib_src += $(AGESA_ROOT)/Proc/GNB/Nb/NbPowerMgmt.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Recovery/HT/htInitReset.c -agesa_lib_src += $(AGESA_ROOT)/Proc/Mem/Main/mu.c - -romstage-y += $(agesa_lib_src) -ramstage-y += $(agesa_lib_src) - subdirs-y += ../../mtrr subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/lapic @@ -283,4 +27,3 @@ subdirs-y += ../../../x86/cache subdirs-y += ../../../x86/mtrr subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm - diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 6a266ec..f457277 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -68,4 +68,264 @@ export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS) -####################################################################### \ No newline at end of file +####################################################################### + +classes-y += libagesa + +libagesa-y = Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbLclkDpm.c +libagesa-y += Proc/GNB/Modules/GnbPcieAlibV1/PcieAlib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSiliconServices.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieWorkarounds.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmExitLatency.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePowerMgmt.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspm.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieSbLink.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PerCorePciTables.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14BrandIdFt1.c +libagesa-y += Proc/GNB/Nb/NbInitAtPost.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieAlib.c +libagesa-y += Proc/CPU/Family/0x14/F14IoCstate.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/Mem/NB/ON/mnprotoon.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c +libagesa-y += Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PciePifServices.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c +libagesa-y += Proc/CPU/cpuInitEarlyTable.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbLclkNclkRatio.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbSmu.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtEnv.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtPost.c +libagesa-y += Proc/GNB/Nb/Feature/NbLclkDpm.c +libagesa-y += Proc/GNB/Nb/Feature/NbFuseTable.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbPowerGate.c +libagesa-y += Proc/GNB/Common/GnbLibFeatures.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Pstate.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Family/0x14/F14C6State.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/CPU/Family/0x14/cpuCommonF14Utilities.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnEquivalenceTable.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/GNB/GnbInitAtReset.c +libagesa-y += Proc/Mem/NB/ON/mnmcton.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/GNB/GnbInitAtEarly.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerMgmtSystemTables.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/HT/Fam14/htNbUtilitiesFam14.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieComplexConfig.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerPlane.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14LowPowerInit.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/ON/mnflowon.c +libagesa-y += Proc/Mem/Feat/CHINTLV/mfchi.c +libagesa-y += Proc/GNB/PCIe/PcieInit.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtMidPost.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14CacheDefaults.c +libagesa-y += Proc/Mem/Ps/ON/mpuon3.c +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cahaltasm.S +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnPciTables.c +libagesa-y += Proc/GNB/PCIe/PciePortInit.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtPost.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14WheaInitDataTables.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/Mem/Tech/mttsrc.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/Mem/NB/ON/mnidendimmon.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PcieComplexServices.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Utilities.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/GNB/Gfx/GfxStrapsInit.c +libagesa-y += Proc/GNB/Nb/NbInitAtEarly.c +libagesa-y += Lib/amdlib.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/GNB/PCIe/Family/0x14/F14PciePhyServices.c +libagesa-y += Proc/GNB/GnbInitAtLate.c +libagesa-y += Proc/Mem/NB/ON/mnoton.c +libagesa-y += Proc/Mem/Feat/INTLVRN/mfintlvrn.c +libagesa-y += Proc/GNB/Nb/NbInit.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/Mem/NB/ON/mndcton.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/GNB/Gfx/GfxGmcInit.c +libagesa-y += Proc/CPU/cpuBrandId.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/GNB/GnbInitAtPost.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PowerCheck.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14Dmi.c +libagesa-y += Proc/Mem/NB/ON/mnregon.c +libagesa-y += Proc/GNB/Gfx/GfxIntegratedInfoTableInit.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/GNB/Gfx/GfxInitAtEnvPost.c +libagesa-y += Proc/CPU/Feature/cpuHwC1e.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Lib/helper.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Ps/ON/mpson3.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/CPU/cpuPowerMgmtMultiSocket.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14PciTables.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/GNB/GnbInitAtMid.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtEarlyPost.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/GNB/Nb/NbInitAtLatePost.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/HT/Fam14/htNbFam14.c +libagesa-y += Proc/GNB/Gfx/GfxConfigData.c +libagesa-y += Proc/Mem/Main/ON/mmflowon.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14MsrTables.c +libagesa-y += Proc/GNB/PCIe/PcieInitAtLatePost.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/GNB/Gfx/GfxRegisterAcc.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/GNB/Nb/NbInitAtReset.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x14/ON/F14OnCpb.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/GNB/GnbInitAtEnv.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14SoftwareThermal.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Proc/Mem/NB/ON/mnon.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/Mem/NB/ON/mnphyon.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/CPU/Family/0x14/cpuF14BrandId.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/GNB/Nb/NbConfigData.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Ardk/ON/mauon3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Ardk/ON/mason3.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/NB/ON/mnS3on.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/GNB/Gfx/Family/0x14/F14GfxServices.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/GNB/PCIe/PcieLateInit.c +libagesa-y += Proc/GNB/PCIe/PciePortLateInit.c +libagesa-y += Proc/GNB/PCIe/PcieMiscLib.c +libagesa-y += Proc/GNB/Nb/NbSmuLib.c +libagesa-y += Proc/GNB/Nb/NbInitAtEnv.c +libagesa-y += Proc/GNB/Nb/Family/0x14/F14NbServices.c +libagesa-y += Proc/GNB/Gfx/GfxLib.c +libagesa-y += Proc/GNB/Nb/NbPowerMgmt.c +libagesa-y += Proc/Recovery/HT/htInitReset.c +libagesa-y += Proc/Mem/Main/mu.c + +$(obj)/libagesa.fam14.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/libagesa.fam14.a +ramstage-libs += $(obj)/libagesa.fam14.a

1 0

Patch set updated for coreboot: 657c461 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 657c461a764dd6104905a4a23003246f6d2e1008 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 5 +++-- src/superio/intel/i3100/i3100.h | 6 +++++- 6 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..a7376b7 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..a0a9d15 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); + +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

1 0

Patch set updated for coreboot: 83f9aa2 superio/serverengines/pilot: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439 -gerrit commit 83f9aa2b1a83cf3ce8e84abbdf720a3574ca9ed1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:53:32 2014 +1100 superio/serverengines/pilot: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/dl145_g3/Kconfig | 1 + src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/Makefile.inc | 2 +- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 7 ++++++- src/superio/serverengines/pilot/early_serial.c | 9 +++++---- src/superio/serverengines/pilot/pilot.h | 11 ++++++++++- 10 files changed, 68 insertions(+), 11 deletions(-) diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..3ff5f0b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..b53809a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index e34fa89..2ca57cb 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -23,7 +23,7 @@ subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas -#subdirs-y += serverengines +subdirs-y += serverengines subdirs-y += smsc subdirs-y += via subdirs-y += winbond diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..002210f 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,16 @@ #define BLUBB_DEV PNP_DEV(port, 0x04) +#include <arch/io.h> +#include <console/console.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..82e124c 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,23 +22,24 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/io.h> +#include <device/pnp.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -static void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0x5A, port); } -static void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(device_t dev) { u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -47,7 +48,7 @@ static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase pnp_exit_ext_func_mode(dev); } -static void __attribute__((unused)) pilot_disable_serial(device_t dev) +void pilot_disable_serial(device_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..e19cf37 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,13 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ -#endif +/* should not expose these however early_init needs love */ +void pnp_enter_ext_func_mode(device_t dev); +void pnp_exit_ext_func_mode(device_t dev); + +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); +void pilot_disable_serial(device_t dev); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */

1 0

New patch to review for coreboot: 2cfe118 util/cbmem: handle larger than 1MiB mappings for console
by Aaron Durbin March 31, 2014

March 31, 2014

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5440 -gerrit commit 2cfe1182688b5bfcc7aee83a279d0d5c11a79388 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Mar 31 11:59:58 2014 -0500 util/cbmem: handle larger than 1MiB mappings for console In some cases the cbmem console can be larger than the default mapping size of 1MiB. Therefore, add the ability to do a mapping that is larger than the default mapping using map_memory_size(). The console printing code will unconditionaly map the console based on the size it finds in the cbmem entry. Change-Id: I016420576b9523ce81195160ae86ad16952b761c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 50 ++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 14 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index dd80c08..b241bf7 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -79,19 +79,45 @@ static u16 ipchcksum(const void *addr, unsigned size) * functions always maps 1MB at a time and can only map one area at once. */ static void *mapped_virtual; -static void *map_memory(u64 physical) +static size_t mapped_size; + +static inline size_t size_to_mib(size_t sz) +{ + return sz >> 20; +} + +static void unmap_memory(void) +{ + if (mapped_virtual == NULL) { + fprintf(stderr, "Error unmapping memory\n"); + return; + } + debug("Unmapping %zuMB of virtual memory at %p.\n", + size_to_mib(mapped_size), mapped_virtual); + munmap(mapped_virtual, mapped_size); + mapped_virtual = NULL; + mapped_size = 0; +} + +static void *map_memory_size(u64 physical, size_t size) { void *v; off_t p; u64 page = getpagesize(); - int padding; + size_t padding; + + if (mapped_virtual != NULL) + unmap_memory(); /* Mapped memory must be aligned to page size */ p = physical & ~(page - 1); + padding = physical & (page-1); + size += padding; - debug("Mapping 1MB of physical memory at 0x%jx.\n", (intmax_t)p); + debug("Mapping %zuMB of physical memory at 0x%jx.\n", + size_to_mib(size), (intmax_t)p); - v = mmap(NULL, MAP_BYTES, PROT_READ, MAP_SHARED, fd, p); + v = mmap(NULL, size, PROT_READ, MAP_SHARED, fd, p); if (v == MAP_FAILED) { fprintf(stderr, "Failed to mmap /dev/mem: %s\n", @@ -101,26 +127,20 @@ static void *map_memory(u64 physical) /* Remember what we actually mapped ... */ mapped_virtual = v; + mapped_size = size; /* ... but return address to the physical memory that was requested */ - padding = physical & (page-1); if (padding) - debug(" ... padding virtual address with 0x%x bytes.\n", + debug(" ... padding virtual address with 0x%zx bytes.\n", padding); v += padding; return v; } -static void unmap_memory(void) +static void *map_memory(u64 physical) { - if (mapped_virtual == NULL) { - fprintf(stderr, "Error unmapping memory\n"); - return; - } - debug("Unmapping 1MB of virtual memory at %p.\n", mapped_virtual); - munmap(mapped_virtual, MAP_BYTES); - mapped_virtual = NULL; + return map_memory_size(physical, MAP_BYTES); } /* @@ -464,6 +484,8 @@ static void dump_console(void) exit(1); } + console_p = map_memory_size((unsigned long)console.cbmem_addr, + size + 2*sizeof(uint32_t)); memcpy(console_c, console_p + 8, size); console_c[size] = 0;

1 0

Patch set updated for coreboot: cec7293 superio/serverengines/pilot: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5439 -gerrit commit cec72932151e494a677b64fe2b5f990421cca9ce Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:53:32 2014 +1100 superio/serverengines/pilot: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/dl145_g3/Kconfig | 1 + src/mainboard/hp/dl145_g3/romstage.c | 3 +-- src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 + src/mainboard/hp/dl165_g6_fam10/romstage.c | 3 +-- src/superio/Makefile.inc | 2 +- src/superio/serverengines/Makefile.inc | 20 ++++++++++++++++++++ src/superio/serverengines/pilot/Makefile.inc | 22 ++++++++++++++++++++++ src/superio/serverengines/pilot/early_init.c | 7 ++++++- src/superio/serverengines/pilot/early_serial.c | 3 ++- src/superio/serverengines/pilot/pilot.h | 6 +++++- 10 files changed, 60 insertions(+), 8 deletions(-) diff --git a/src/mainboard/hp/dl145_g3/Kconfig b/src/mainboard/hp/dl145_g3/Kconfig index be3f009..3ff5f0b 100644 --- a/src/mainboard/hp/dl145_g3/Kconfig +++ b/src/mainboard/hp/dl145_g3/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..9deaaba 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -40,8 +40,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index b72b8dd..b53809a 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AMDFAM10 select SOUTHBRIDGE_BROADCOM_BCM21000 select SOUTHBRIDGE_BROADCOM_BCM5785 + select SUPERIO_SERVERENGINES_PILOT select SUPERIO_NSC_PC87417 select DIMM_DDR2 select DIMM_REGISTERED diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 8e109c5..474190b 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -46,8 +46,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" -#include "superio/serverengines/pilot/early_serial.c" -#include "superio/serverengines/pilot/early_init.c" +#include <superio/serverengines/pilot/pilot.h> #include "superio/nsc/pc87417/early_serial.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index e34fa89..2ca57cb 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -23,7 +23,7 @@ subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas -#subdirs-y += serverengines +subdirs-y += serverengines subdirs-y += smsc subdirs-y += via subdirs-y += winbond diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc new file mode 100644 index 0000000..4ba0a24 --- /dev/null +++ b/src/superio/serverengines/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc new file mode 100644 index 0000000..b07438f --- /dev/null +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c +romstage-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 1993c9e..002210f 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -23,11 +23,16 @@ #define BLUBB_DEV PNP_DEV(port, 0x04) +#include <arch/io.h> +#include <console/console.h> +#include <device/pnp.h> +#include "pilot.h" + /* * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -static void pilot_early_init(device_t dev) +void pilot_early_init(device_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 4112901..1b2e38e 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -22,6 +22,7 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ #include <arch/io.h> +#include <device/pnp.h> #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ @@ -38,7 +39,7 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Serial config is a fairly standard procedure. */ -static void __attribute__((unused)) pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a5bddd3..84d1989 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -30,4 +30,8 @@ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ -#endif +void pilot_early_init(device_t dev); + +void pilot_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */

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Patch set updated for coreboot: 2f5fd95 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 2f5fd95e60e85e5fc9190551858ed7f0623c3e9a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 5 +++-- src/superio/intel/i3100/i3100.h | 6 +++++- 6 files changed, 12 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..a7376b7 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "i3100.h" static void pnp_enter_ext_func_mode(device_t dev) @@ -38,14 +39,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..a0a9d15 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); + +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */

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Patch set updated for coreboot: 01e8ec0 superio/fintek/f71872: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5436 -gerrit commit 01e8ec0edef0d92dd4d8a44b561cd0a27b10ce47 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:13:07 2014 +1100 superio/fintek/f71872: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Ia021229154dc90b830a314f3adc2a0dd444bd68d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71872/Makefile.inc | 1 + src/superio/fintek/f71872/chip.h | 2 +- src/superio/fintek/f71872/early_serial.c | 3 ++- src/superio/fintek/f71872/f71872.h | 4 +++- 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/superio/fintek/f71872/Makefile.inc b/src/superio/fintek/f71872/Makefile.inc index ed40eb0..58ba5d5 100644 --- a/src/superio/fintek/f71872/Makefile.inc +++ b/src/superio/fintek/f71872/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71872) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71872) += superio.c diff --git a/src/superio/fintek/f71872/chip.h b/src/superio/fintek/f71872/chip.h index a6ac51f..3368ef2 100644 --- a/src/superio/fintek/f71872/chip.h +++ b/src/superio/fintek/f71872/chip.h @@ -28,4 +28,4 @@ struct superio_fintek_f71872_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F71872_CHIP_H */ diff --git a/src/superio/fintek/f71872/early_serial.c b/src/superio/fintek/f71872/early_serial.c index af5cdb3..bbfc264 100644 --- a/src/superio/fintek/f71872/early_serial.c +++ b/src/superio/fintek/f71872/early_serial.c @@ -21,6 +21,7 @@ /* Pre-RAM driver for the Fintek F71872F/FG Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> #include "f71872.h" static void pnp_enter_conf_state(device_t dev) @@ -36,7 +37,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71872_enable_serial(device_t dev, u16 iobase) +void f71872_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71872/f71872.h b/src/superio/fintek/f71872/f71872.h index 585b142..577f8d1 100644 --- a/src/superio/fintek/f71872/f71872.h +++ b/src/superio/fintek/f71872/f71872.h @@ -32,4 +32,6 @@ #define F71872_VID 0x07 /* VID */ #define F71872_PM 0x0a /* ACPI/PME */ -#endif +void f71872_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71872_F71872_H */

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Patch set updated for coreboot: 7016536 superio/fintek/f71889: Avoid .c includes
by Edward O'Callaghan March 31, 2014

March 31, 2014

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5437 -gerrit commit 70165365bc95dc2e12e5c9db15a6e3db7cb147dd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 15:14:14 2014 +1100 superio/fintek/f71889: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code. Change-Id: Id8a1a2e8c87add636af1506598c2669d72dc3238 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71889/Makefile.inc | 2 +- src/superio/fintek/f71889/chip.h | 2 +- src/superio/fintek/f71889/early_serial.c | 4 ++-- src/superio/fintek/f71889/f71889.h | 4 +++- 4 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/superio/fintek/f71889/Makefile.inc b/src/superio/fintek/f71889/Makefile.inc index ef14b74..9864140 100644 --- a/src/superio/fintek/f71889/Makefile.inc +++ b/src/superio/fintek/f71889/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_FINTEK_F71889) += early_serial.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c - diff --git a/src/superio/fintek/f71889/chip.h b/src/superio/fintek/f71889/chip.h index 2895efc..50312ad 100644 --- a/src/superio/fintek/f71889/chip.h +++ b/src/superio/fintek/f71889/chip.h @@ -29,4 +29,4 @@ struct superio_fintek_f71889_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_FINTEK_F71889_CHIP_H */ diff --git a/src/superio/fintek/f71889/early_serial.c b/src/superio/fintek/f71889/early_serial.c index 9623cbd..5e11474 100644 --- a/src/superio/fintek/f71889/early_serial.c +++ b/src/superio/fintek/f71889/early_serial.c @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> #include <arch/io.h> +#include <device/pnp.h> #include "f71889.h" static void pnp_enter_conf_state(device_t dev) @@ -35,7 +35,7 @@ static void pnp_exit_conf_state(device_t dev) outb(0xaa, port); } -static void f71889_enable_serial(device_t dev, u16 iobase) +void f71889_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/f71889/f71889.h b/src/superio/fintek/f71889/f71889.h index 1b6a369..6dc43b3 100644 --- a/src/superio/fintek/f71889/f71889.h +++ b/src/superio/fintek/f71889/f71889.h @@ -34,4 +34,6 @@ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ -#endif +void f71889_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_FINTEK_F71889_F71889_H */

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