December 2014 - coreboot-gerrit

New patch to review for coreboot: d8ac2a0 [NOTFORMERGE] Intel FSP: Timestamps
by Kyösti Mälkki Dec. 31, 2014

Dec. 31, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8024 -gerrit commit d8ac2a045be48eca04309e82596d412bdc9fcb36 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 21:48:48 2014 +0200 [NOTFORMERGE] Intel FSP: Timestamps Only after BROKEN_CAR_MIGRATE is fixed. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 23 ++++------------------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 11 ++++++----- src/southbridge/intel/fsp_rangeley/romstage.c | 11 ++++++----- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 0823ae2..11d915e 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -182,11 +182,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time); -#endif + timestamp_init(get_initial_timestamp()); + timestamp_add(TS_START_ROMSTAGE); pch_enable_lpc(); @@ -234,11 +231,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time); -#endif + timestamp_add(TS_BEFORE_INITRAM); /* * Call early init to initialize memory and chipset. This function returns @@ -259,11 +252,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { u32 reg32; void *cbmem_hob_ptr; -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t after_initram_time = timestamp_get(); - uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4; - uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4; -#endif + timestamp_add_now(TS_AFTER_INITRAM); /* * HD AUDIO is not used on this system, so we're using some registers @@ -317,10 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_initram_time ); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); /* Load the ramstage. */ diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index ad42e73..cafd329 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -161,6 +161,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); + timestamp_init(get_initial_timestamp()); + timestamp_add(TS_START_ROMSTAGE); + program_base_addresses(); post_code(0x41); @@ -199,6 +202,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x47); + timestamp_add(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -220,9 +225,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { uint32_t prev_sleep_state; struct romstage_handoff *handoff; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x4a); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -265,8 +268,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..86d5274 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -53,6 +53,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ outb(0x40, 0x80); + timestamp_init(get_initial_timestamp()); + timestamp_add(TS_START_ROMSTAGE); + /* Rangeley UART POR state is enabled */ console_init(); post_code(0x41); @@ -75,6 +78,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) read32(func_dis); } + timestamp_add(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -94,9 +99,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -127,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f);

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New patch to review for coreboot: e97342f [NOTFORMERGE]: Enable COLLECT_TIMESTAMPS by default
by Kyösti Mälkki Dec. 31, 2014

Dec. 31, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8023 -gerrit commit e97342f570f6ecb28025a09c49ccd2f744698d92 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 22:12:56 2014 +0200 [NOTFORMERGE]: Enable COLLECT_TIMESTAMPS by default Change-Id: I71b494ec52eb8de601321285b63be87f03f3ac0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 30961a4..9deeac4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -183,7 +183,7 @@ config DYNAMIC_CBMEM config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n + default y help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

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New patch to review for coreboot: eea0f9d baytrail broadwell: Use timestamps internal stash
by Kyösti Mälkki Dec. 31, 2014

Dec. 31, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8022 -gerrit commit eea0f9d18b4b920b974121c81ba85ef091cfba9d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 21:11:51 2014 +0200 baytrail broadwell: Use timestamps internal stash No reason to carry timestamps on CAR stack, as implementation of timestamps internally stashes on CAR_GLOBAL table and migrates those to CBMEM. Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/baytrail/baytrail/romstage.h | 7 ------- src/soc/intel/baytrail/romstage/romstage.c | 23 +++++------------------ src/soc/intel/broadwell/broadwell/romstage.h | 7 ------- src/soc/intel/broadwell/romstage/romstage.c | 23 +++++------------------ 4 files changed, 10 insertions(+), 50 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index 9ea3564..5fbda37 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -28,14 +28,7 @@ #include <arch/cpu.h> #include <baytrail/mrc_wrapper.h> -#define NUM_ROMSTAGE_TS 4 -struct romstage_timestamps { - uint64_t times[NUM_ROMSTAGE_TS]; - int count; -}; - struct romstage_params { - struct romstage_timestamps ts; unsigned long bist; struct mrc_params *mrc_params; }; diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index ac5afab..a989a99 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -99,14 +99,6 @@ static void spi_init(void) write32(bcr, reg); } -static inline void mark_ts(struct romstage_params *rp, uint64_t ts) -{ - struct romstage_timestamps *rt = &rp->ts; - - rt->times[rt->count] = ts; - rt->count++; -} - /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -117,9 +109,10 @@ void * asmlinkage romstage_main(unsigned long bist, }; /* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + /* Save romstage begin */ - mark_ts(&rp, timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); program_base_addresses(); @@ -233,7 +226,7 @@ void romstage_common(struct romstage_params *params) struct chipset_power_state *ps; int prev_sleep_state; - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_BEFORE_INITRAM); ps = fill_power_state(); prev_sleep_state = chipset_prev_sleep_state(ps); @@ -249,7 +242,7 @@ void romstage_common(struct romstage_params *params) /* Initialize RAM */ raminit(params->mrc_params, prev_sleep_state); - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_AFTER_INITRAM); handoff = romstage_handoff_find_or_add(); if (handoff != NULL) @@ -258,12 +251,6 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); chromeos_init(prev_sleep_state); - - /* Save timestamp information. */ - timestamp_init(params->ts.times[0]); - timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); - timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); - timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h index d3702c7..946d1d0 100644 --- a/src/soc/intel/broadwell/broadwell/romstage.h +++ b/src/soc/intel/broadwell/broadwell/romstage.h @@ -23,16 +23,9 @@ #include <stdint.h> #include <arch/cpu.h> -#define NUM_ROMSTAGE_TS 4 -struct romstage_timestamps { - uint64_t times[NUM_ROMSTAGE_TS]; - int count; -}; - struct chipset_power_state; struct pei_data; struct romstage_params { - struct romstage_timestamps ts; unsigned long bist; struct chipset_power_state *power_state; struct pei_data *pei_data; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f234fda..5ca57d0 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,14 +38,6 @@ #include <broadwell/romstage.h> #include <broadwell/spi.h> -static inline void mark_ts(struct romstage_params *rp, uint64_t ts) -{ - struct romstage_timestamps *rt = &rp->ts; - - rt->times[rt->count] = ts; - rt->count++; -} - /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -58,10 +50,10 @@ void * asmlinkage romstage_main(unsigned long bist, post_code(0x30); /* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); /* Save romstage begin */ - mark_ts(&rp, timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); /* System Agent Early Initialization */ systemagent_early_init(); @@ -102,7 +94,7 @@ void romstage_common(struct romstage_params *params) post_code(0x32); - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_BEFORE_INITRAM); params->pei_data->boot_mode = params->power_state->prev_sleep_state; @@ -116,7 +108,8 @@ void romstage_common(struct romstage_params *params) /* Initialize RAM */ raminit(params->pei_data); - mark_ts(params, timestamp_get()); + + timestamp_add_now(TS_AFTER_INITRAM); handoff = romstage_handoff_find_or_add(); if (handoff != NULL) @@ -126,12 +119,6 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); chromeos_init(params->power_state->prev_sleep_state); - - /* Save timestamp information. */ - timestamp_init(params->ts.times[0]); - timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); - timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); - timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void)

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New patch to review for coreboot: 8eca280 ARM romstages: Support and fix COLLECT_TIMESTAMPS
by Kyösti Mälkki Dec. 31, 2014

Dec. 31, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8021 -gerrit commit 8eca2807eeacbb336429ecda46a15d94f2fd5d74 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 08:50:36 2014 +0200 ARM romstages: Support and fix COLLECT_TIMESTAMPS Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/daisy/romstage.c | 12 ++++++++++++ src/mainboard/google/nyan/romstage.c | 12 ++++-------- src/mainboard/google/nyan_big/romstage.c | 12 ++++-------- src/mainboard/google/nyan_blaze/romstage.c | 12 ++++-------- src/mainboard/google/peach_pit/romstage.c | 11 +++++++++++ 5 files changed, 35 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 9b35c4a..46c6593 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -22,6 +22,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -147,6 +148,9 @@ void main(void) void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = setup_clock(); @@ -155,8 +159,13 @@ void main(void) exception_init(); setup_power(is_resume); + + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(mem, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + /* This needs to happen on normal boots and on resume. */ trustzone_init(); @@ -174,5 +183,8 @@ void main(void) cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 248809d..ce4e399 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -23,6 +23,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -234,6 +235,9 @@ void main(void) exynos5420_config_smp(); power_init_failed = setup_power(is_resume); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ system_clock_init(); @@ -248,8 +252,12 @@ void main(void) /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(&mem_timings, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + primitive_mem_test(); trustzone_init(); @@ -272,5 +280,8 @@ void main(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); simple_spi_test(); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); }

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New patch to review for coreboot: a1a99ed timestamps: Switch from tsc_t to uint64_t
by Kyösti Mälkki Dec. 31, 2014

Dec. 31, 2014

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8020 -gerrit commit a1a99ed745e163df5fe3eb517b3e873068f80117 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 1 13:31:44 2013 -0700 timestamps: Switch from tsc_t to uint64_t Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer(a)google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/armv7/Makefile.inc | 2 ++ src/arch/arm/armv7/timestamp.c | 29 ++++++++++++++++++ src/arch/x86/lib/Makefile.inc | 5 +++- src/arch/x86/lib/timestamp.c | 27 +++++++++++++++++ src/include/cpu/x86/tsc.h | 5 ++++ src/include/timestamp.h | 12 +++++--- src/lib/hardwaremain.c | 2 +- src/lib/timestamp.c | 25 +++++++--------- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 41 ++++++++------------------ src/mainboard/via/epia-m850/romstage.c | 2 +- src/soc/intel/baytrail/romstage/romstage.c | 22 +++----------- src/soc/intel/broadwell/romstage/romstage.c | 22 +++----------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 19 +++++------- src/southbridge/intel/bd82x6x/early_pch.c | 8 ++--- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 16 +++++----- src/southbridge/intel/i82801gx/early_lpc.c | 7 ++--- src/southbridge/intel/lynxpoint/early_pch.c | 7 ++--- 20 files changed, 135 insertions(+), 122 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 62d5434..7e67178 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -57,6 +57,7 @@ romstage-y += cpu.S romstage-y += exception.c romstage-y += exception_asm.S romstage-y += mmu.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-c-ccopts += $(armv7_flags) romstage-S-ccopts += $(armv7_asm_flags) @@ -74,6 +75,7 @@ ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += exception_asm.S ramstage-y += mmu.c +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-c-ccopts += $(armv7_flags) ramstage-S-ccopts += $(armv7_asm_flags) diff --git a/src/arch/arm/armv7/timestamp.c b/src/arch/arm/armv7/timestamp.c new file mode 100644 index 0000000..07a209c --- /dev/null +++ b/src/arch/arm/armv7/timestamp.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <timestamp.h> +#include <timer.h> + +uint64_t timestamp_get(void) +{ + struct mono_time timestamp; + timer_monotonic_get(&timestamp); + return (uint64_t)timestamp.microseconds; +} + diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 22306f1..c7e8b62 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -24,6 +24,9 @@ ramstage-y += ebda.c ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c smm-y += memset.c smm-y += memcpy.c @@ -34,4 +37,4 @@ rmodules_x86_32-y += memset.c rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove.c -endif # CONFIG_ARCH_RAMSTAGE_X86_32 \ No newline at end of file +endif # CONFIG_ARCH_RAMSTAGE_X86_32 diff --git a/src/arch/x86/lib/timestamp.c b/src/arch/x86/lib/timestamp.c new file mode 100644 index 0000000..02582a5 --- /dev/null +++ b/src/arch/x86/lib/timestamp.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <cpu/x86/tsc.h> +#include <timestamp.h> + +uint64_t timestamp_get(void) +{ + return rdtscll(); +} + diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 7323599..71d253b 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -53,6 +53,11 @@ static inline unsigned long long rdtscll(void) ); return val; } + +static inline uint64_t tsc_to_uint64(tsc_t tstamp) +{ + return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; +} #endif #if CONFIG_TSC_CONSTANT_RATE diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 66c1d9a..ba73135 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -20,6 +20,8 @@ #ifndef __TIMESTAMP_H__ #define __TIMESTAMP_H__ +#include <stdint.h> + struct timestamp_entry { uint32_t entry_id; uint64_t entry_stamp; @@ -59,12 +61,10 @@ enum timestamp_id { }; #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) -#include <cpu/x86/tsc.h> -void timestamp_init(tsc_t base); -void timestamp_add(enum timestamp_id id, tsc_t ts_time); +void timestamp_init(uint64_t base); +void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); void timestamp_reinit(void); -tsc_t get_initial_timestamp(void); #else #define timestamp_init(base) #define timestamp_add(id, time) @@ -72,4 +72,8 @@ tsc_t get_initial_timestamp(void); #define timestamp_reinit() #endif +/* Implemented by the architecture code */ +uint64_t timestamp_get(void); +uint64_t get_initial_timestamp(void); + #endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index be052b3..e01247b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -452,7 +452,7 @@ static void boot_state_schedule_static_entries(void) void main(void) { /* Record current time, try to locate timestamps in CBMEM. */ - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f0ee48d..67635f8 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -28,16 +28,11 @@ #define MAX_TIMESTAMPS 30 static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; -static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 }; +static uint64_t ts_basetime CAR_GLOBAL = 0; -static void timestamp_stash(enum timestamp_id id, tsc_t ts_time); +static void timestamp_stash(enum timestamp_id id, uint64_t ts_time); -static uint64_t tsc_to_uint64(tsc_t tstamp) -{ - return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; -} - -static void timestamp_real_init(tsc_t base) +static void timestamp_real_init(uint64_t base) { struct timestamp_table* tst; @@ -50,14 +45,14 @@ static void timestamp_real_init(tsc_t base) return; } - tst->base_time = tsc_to_uint64(base); + tst->base_time = base; tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; car_set_var(ts_table_p, tst); } -void timestamp_add(enum timestamp_id id, tsc_t ts_time) +void timestamp_add(enum timestamp_id id, uint64_t ts_time) { struct timestamp_entry *tse; struct timestamp_table *ts_table = NULL; @@ -75,18 +70,18 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time) tse = &ts_table->entries[ts_table->num_entries++]; tse->entry_id = id; - tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time; + tse->entry_stamp = ts_time - ts_table->base_time; } void timestamp_add_now(enum timestamp_id id) { - timestamp_add(id, rdtsc()); + timestamp_add(id, timestamp_get()); } #define MAX_TIMESTAMP_CACHE 8 struct timestamp_cache { enum timestamp_id id; - tsc_t time; + uint64_t time; } timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL; static int timestamp_entries CAR_GLOBAL = 0; @@ -99,7 +94,7 @@ static int timestamp_entries CAR_GLOBAL = 0; * part of CAR migration for romstage, and in ramstage main(). */ -static void timestamp_stash(enum timestamp_id id, tsc_t ts_time) +static void timestamp_stash(enum timestamp_id id, uint64_t ts_time) { struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); int ts_entries = car_get_var(timestamp_entries); @@ -124,7 +119,7 @@ static void timestamp_do_sync(void) car_set_var(timestamp_entries, 0); } -void timestamp_init(tsc_t base) +void timestamp_init(uint64_t base) { if (!boot_cpu()) return; diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index c617a0a..8992a57 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -50,7 +50,7 @@ void main(unsigned long bist) cbmem_was_initted = !cbmem_recovery(0); - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); } diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 658051c..6f08b6a 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -52,7 +52,7 @@ void main(unsigned long bist) cbmem_was_initted = !cbmem_recovery(0); - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 6580ab9..0823ae2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -183,14 +183,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); #if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t before_initram_time; - - start_romstage_time = rdtsc(); - + uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time.lo >> 4 | - start_romstage_time.lo << 28); + pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time); #endif pch_enable_lpc(); @@ -240,11 +235,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); #if CONFIG_COLLECT_TIMESTAMPS - before_initram_time= rdtsc(); + uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4); /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time.lo >> 4 | - before_initram_time.lo << 28); - + pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time); #endif /* @@ -267,20 +260,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { void *cbmem_hob_ptr; #if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t base_time; - tsc_t before_initram_time; - tsc_t after_initram_time = rdtsc(); - u32 timebase = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0); - u32 time_romstage_start = pci_read_config32(PCI_DEV(0, 27, 0), 0x2c); - u32 time_before_initram = pci_read_config32(PCI_DEV(0, 27, 0), 0x14); - - base_time.lo = timebase << 4; - base_time.hi = timebase >> 28; - start_romstage_time.lo = time_romstage_start << 4; - start_romstage_time.hi = time_romstage_start >> 28; - before_initram_time.lo = time_before_initram << 4; - before_initram_time.hi = time_before_initram >> 28; + uint64_t after_initram_time = timestamp_get(); + uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4; + uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4; #endif /* @@ -335,13 +317,11 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_initram_time ); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif /* Load the ramstage. */ copy_and_run(); @@ -353,3 +333,8 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) /* No overrides needed */ return; } + +uint64_t get_initial_timestamp(void) +{ + return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4; +} diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 899c5a6..01d955a 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -46,7 +46,7 @@ void main(unsigned long bist) { u32 tolm; - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); /* First thing we need to do on the VX900, before anything else */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index b69b532..ac5afab 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -44,20 +44,6 @@ #include <baytrail/smm.h> #include <baytrail/spi.h> -static inline uint64_t timestamp_get(void) -{ - return rdtscll(); -} - -static inline tsc_t ts64_to_tsc(uint64_t ts) -{ - tsc_t tsc = { - .lo = ts, - .hi = ts >> 32, - }; - return tsc; -} - /* The cache-as-ram assembly file calls romstage_main() after setting up * cache-as-ram. romstage_main() will then call the mainboards's * mainboard_romstage_entry() function. That function then calls @@ -274,10 +260,10 @@ void romstage_common(struct romstage_params *params) chromeos_init(prev_sleep_state); /* Save timestamp information. */ - timestamp_init(ts64_to_tsc(params->ts.times[0])); - timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); - timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); - timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); + timestamp_init(params->ts.times[0]); + timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); + timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); + timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4a5a47c..f234fda 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,20 +38,6 @@ #include <broadwell/romstage.h> #include <broadwell/spi.h> -static inline uint64_t timestamp_get(void) -{ - return rdtscll(); -} - -static inline tsc_t ts64_to_tsc(uint64_t ts) -{ - tsc_t tsc = { - .lo = ts, - .hi = ts >> 32, - }; - return tsc; -} - static inline void mark_ts(struct romstage_params *rp, uint64_t ts) { struct romstage_timestamps *rt = &rp->ts; @@ -142,10 +128,10 @@ void romstage_common(struct romstage_params *params) chromeos_init(params->power_state->prev_sleep_state); /* Save timestamp information. */ - timestamp_init(ts64_to_tsc(params->ts.times[0])); - timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); - timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); - timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); + timestamp_init(params->ts.times[0]); + timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); + timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); + timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..ad42e73 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -221,10 +221,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { struct romstage_handoff *handoff; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - tsc_t after_initram_time = rdtsc(); - tsc_t base_time; - base_time.hi = 0; - base_time.lo = 0; + uint64_t after_initram_time = timestamp_get(); #endif post_code(0x4a); @@ -244,9 +241,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { report_platform_info(); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - after_initram_time = rdtsc(); -#endif post_code(0x4b); late_mainboard_romstage_entry(); @@ -271,13 +265,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - timestamp_init(base_time); - timestamp_reinit(); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif post_code(0x4f); @@ -285,3 +275,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { copy_and_run(); while (1); } + +uint64_t get_initial_timestamp(void) +{ + return 0; +} diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 3438a0a..95182ce 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,21 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include "pch.h" #include <arch/acpi.h> #include <console/console.h> -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif - int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 61ff301..9b3e97a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) * only storing the low nibble of the high dword of the tsc. Even this * is probably 0 by the time we get here, so storing 64 bits is overkill.S */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); } /* diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..fba9eb6 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -95,11 +95,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { void *cbmem_hob_ptr; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - tsc_t after_initram_time = rdtsc(); - tsc_t base_time; - base_time.hi = 0; - base_time.lo = 0; + uint64_t after_initram_time = timestamp_get(); #endif + post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); @@ -129,12 +127,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - timestamp_init(base_time); - timestamp_reinit(); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif post_code(0x4f); @@ -142,3 +137,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { copy_and_run(); while (1); } + +uint64_t get_initial_timestamp(void) +{ + return 0; +} diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 69bbfb2..b08a964 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -20,20 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801gx.h" -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index fdbb2a3..5378428 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -71,16 +72,14 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif static int sleep_type_s3(void) {

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Patch merged into coreboot/master: 2663a55 samus: Combine mainboard patches to build soc/intel/broadwell
by gerrit＠coreboot.org Dec. 31, 2014

Dec. 31, 2014

the following patch was just integrated into master: commit 2663a55caf2c04c0ee8793c3ac3ccaa63ab4da6c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 14 15:59:37 2014 -0700 samus: Combine mainboard patches to build soc/intel/broadwell Combine four patches dependencies. These will not build individually, so combine them for coreboot.org upstream. samus: Move SPD handling to separate file The code to find the SPD data for the mainboard based on GPIOs is moved from romstage.c into spd.c. It relies on the updated pei_data structure from broadwell instead of the haswell interface. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199920 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> samus: Move PEI data structure init to separate file This needs to be executed in both romstage and ramstage for the different PEI binary stages. It uses the broadwell interface now instead of haswell. BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199921 (cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> samus: Convert mainboard to use soc/intel/broadwell Switch from the haswell cpu/northbridge/southbridge interface to the soc/intel/broadwell interface. - Use new headers where appropriate - Remove code that is now done by the SOC generic code - Update GPIO map to drop LP specific handling - Update INT15 handlers, drop all but the boot display hook BUG=chrome-os-partner:28234 TEST=Build and boot on samus CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199923 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199922 (cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> samus: Add some code to print basic info from SPD The handling of LPDDR is a bit messy in Intel platforms. There is no traditional SPD so instead one is created by hand from the provided datasheets. These have varying (and sometimes unexpected) geometry and it can be important during bringup to know what configuration is being passed to the memory training code. This could in theory be put in a more generic location, but for now this is the only board with LPDDR3 where I have found it valuable. BUG=chrome-os-partner:28234 TEST=Build and boot on samus, look for SPD details on the console. CQ-DEPEND=CL:199920 CQ-DEPEND=CL:199921 CQ-DEPEND=CL:199922 CQ-DEPEND=CL:199943 CQ-DEPEND=CL:*163751 Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199923 (cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d Reviewed-on: http://review.coreboot.org/7943 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7943 for details. -gerrit

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Patch merged into coreboot/master: 229958e broadwell: Hook into the build system
by gerrit＠coreboot.org Dec. 31, 2014

Dec. 31, 2014

the following patch was just integrated into master: commit 229958e0b93e5b8d398a8357d7df6509b422ca31 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 14 14:13:42 2014 -0700 broadwell: Hook into the build system Hook the soc/intel/broadwell directory into the configuration and build system so it can be used by mainboards. BUG=chrome-os-partner:28234 TEST=build and boot on wtm2 Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199893 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b Reviewed-on: http://review.coreboot.org/7940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7940 for details. -gerrit

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Patch merged into coreboot/master: a6354a1 broadwell: Preparations for building
by gerrit＠coreboot.org Dec. 31, 2014

Dec. 31, 2014

the following patch was just integrated into master: commit a6354a1acadc7825364c6a6e7fd3b24a405a62a1 Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri Dec 26 22:11:14 2014 -0700 broadwell: Preparations for building Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7939 for details. -gerrit

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Patch merged into coreboot/master: dffd892 ipq8064: modify SPI controller driver to work in coreboot
by gerrit＠coreboot.org Dec. 31, 2014

Dec. 31, 2014

the following patch was just integrated into master: commit dffd892e47bb8bbfb920447275a2d6b00be904ce Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 30 13:25:12 2014 -0700 ipq8064: modify SPI controller driver to work in coreboot A typical SPI operation consists of two phases - command and data transfers. Command transfer is always from the host to the chip (i.e. is going in the 'write' direction), data transfer could be either read or write. We don't want the receive FIFO to be operating while the command phase is in progress. A simple way to keep the receive FIFO shut down is to not to enable it until the command phase is completed. Selective control of the receive FIFO allows to consolidate the receive and transmit functions in a single spi_xfer() function, as it happens in other SPI controller drivers. The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the next byte can be written or received, respectively. While data is being received the 0xFF bytes are transmitted per each received byte, to keep the SPI bus clocking. The data structure describing the three GSBI ports is moved from the .h file into .c file. A version of the clrsetbits macro is added to work with integer addresses instead of pointers. BUG=chrome-os-partner:27784 TEST=not yet, but with the res of the changes the bootblock loads and starts the rombase section successfully. Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197779 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f Reviewed-on: http://review.coreboot.org/7983 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7983 for details. -gerrit

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Patch merged into coreboot/master: 11c4c92 ipq8064/storm: UART enable and various fixes
by gerrit＠coreboot.org Dec. 31, 2014

Dec. 31, 2014

the following patch was just integrated into master: commit 11c4c92d918df878f052a501ce22b3eee2199cef Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 23 14:26:01 2014 -0700 ipq8064/storm: UART enable and various fixes The original patch from chromium was a bit of a mishmash. Between that, rebasing and using the coreboot.org UART infrastructure, the patch has changed a bit from the original. It seems reasonable to keep these changes together. - build in the ipq UART and turn on bootblock console - sets LPAE and ROM header address - adds cpd.c to storm The original commit: ipq8064: make UART driver work in bootblock This patch it the last one in the chain adapting the ipq9064 UART driver for use in coreboot. A new config option (CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of the driver. The previously introduced uart_wrapper.c is now included in the build to provide the console driver structure used by ramstage. Necessary configuration options are added to allow use of UART in the bootblock. BUG=chrome-os-partner:27784 TEST=with this change the coreboot image on AP148 prints a banner on start up: coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting... Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196663 (cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91 Reviewed-on: http://review.coreboot.org/7875 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7875 for details. -gerrit

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