May 2013 - coreboot-gerrit - mail.coreboot.org

New patch to review for coreboot: ca2544a abuild: Add xgcc tools to the path
by Marc Jones May 31, 2013

May 31, 2013

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3350 -gerrit commit ca2544ac1d579f89932d6ff1ea4a6128bc0aa49f Author: Marc Jones <marc.jones(a)se-eng.com> Date: Fri May 31 13:33:30 2013 -0600 abuild: Add xgcc tools to the path abuild checks the path for toolchains prior to building a mainboard. It didn't check xgcc/, which would be picked up by the coreboot make, and fail to build when it shouldn't. Change-Id: If0ca4238e8c57a6b015fdad623ccdbf237ef1ba6 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> --- util/abuild/abuild | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index aad066c..d419e87 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -6,6 +6,7 @@ # # (C) 2004 by Stefan Reinauer <stepan(a)openbios.org> # (C) 2006-2010 by coresystems GmbH <info(a)coresystems.de> +# (C) 2013 Sage Electronic Engineering, LLC # # This file is subject to the terms and conditions of the GNU General # Public License. See the file COPYING in the main directory of this @@ -14,8 +15,8 @@ #set -x # Turn echo on.... -ABUILD_DATE="December 10th, 2010" -ABUILD_VERSION="0.9.1" +ABUILD_DATE="May 31, 2013" +ABUILD_VERSION="0.9.2" TOP=$PWD @@ -27,6 +28,14 @@ REAL_XMLFILE=$XMLFILE # path to payload. Should be more generic PAYLOAD=/dev/null +# path to coreboot XGCC +XGCCPATH="`pwd`/util/crossgcc/xgcc/bin/" + +# Add XGCC to the path. +if [ -d "$XGCCPATH" ] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then + PATH="$XGCCPATH:$PATH" +fi + # Lines of error context to be printed in FAILURE case CONTEXT=6

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New patch to review for coreboot: d21bb01 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture
by Ronald G. Minnich May 31, 2013

May 31, 2013

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3349 -gerrit commit d21bb0123953d4bcf878fce11e5dc1a272f5a32e Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri May 31 19:36:52 2013 +0200 Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architecture The MARK_GRAPHICS_MEM_WRCOMB was spreading like a cancer since it was defined in sandybridge. It is really more of an x86 thing however, and we now have three systems that can use it. I considered making this more general, since it technically can apply to PTE-based systems like ARM, and maybe we should. But the 'WRCOMB' moniker is usually closely tied to the x86. Change-Id: I3eb6eb2113843643348a5e18e78c53d113899ff8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/x86/Kconfig | 8 ++++++++ src/northbridge/intel/haswell/Kconfig | 8 -------- src/northbridge/intel/sandybridge/Kconfig | 8 -------- 3 files changed, 8 insertions(+), 16 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 5f46145..a1ab904 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -1,5 +1,13 @@ menu "Architecture (x86)" +config MARK_GRAPHICS_MEM_WRCOMB + bool "Mark graphics memory as write-combining." + default n + help + The graphics performance may increase if the graphics + memory is set as write-combining cache type. This option + enables marking the graphics memory as write-combining. + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 12f865a..f689780 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -82,14 +82,6 @@ config DCACHE_RAM_ROMSTAGE_STACK_SIZE The amount of anticipated stack usage from the data cache during pre-ram rom stage execution. -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 6c9ae99..56d2cd7 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -107,14 +107,6 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x4000 -config MARK_GRAPHICS_MEM_WRCOMB - bool "Mark graphics memory as write-combining." - default n - help - The graphics performance may increase if the graphics - memory is set as write-combining cache type. This option - enables marking the graphics memory as write-combining. - config HAVE_MRC bool "Add a System Agent binary" help

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Patch merged into coreboot/master: 8977b6a Lenovo ThinkPad X60: cleanup Native VGA init.
by gerrit＠coreboot.org May 31, 2013

May 31, 2013

the following patch was just integrated into master: commit 8977b6ac5ca4e99289c1f49a878e6901094c8cc2 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Apr 26 14:49:27 2013 +0200 Lenovo ThinkPad X60: cleanup Native VGA init. Change-Id: Iaefa23a6257fd0295357465eb03ccadbef0f70da Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: http://review.coreboot.org/3272 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3272 for details. -gerrit

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Patch merged into coreboot/master: 474eeed AMD Trinity boards: Add reserved memory area for SPI base address in ACPI
by gerrit＠coreboot.org May 31, 2013

May 31, 2013

the following patch was just integrated into master: commit 474eeedbc85545fce4e5feba21e79bd043d2f858 Author: Steven Sherk <steven.sherk(a)se-eng.com> Date: Wed May 22 13:49:18 2013 -0600 AMD Trinity boards: Add reserved memory area for SPI base address in ACPI - SPI controller base address gets overwritten by SD controller under Linux. - Reason for overwrite is the SPI base address isn't in a standard BAR and doesn't get automatically reserved. Solution is to add it as a reserved memory area in ACPI. - This issue was found on the ASUS F2A85-M platform. Currently a workaround on this platform was made as part of: http://review.coreboot.org/#/c/3167/3 - Once approved a follow-on patch for other southbridges using a non-standard BAR for the spi controller. Change-Id: I1b67da3045729a6754e245141cd83c5b3cc9009e Signed-off-by: Steven Sherk <steven.sherk(a)se-eng.com> Reviewed-on: http://review.coreboot.org/3270 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3270 for details. -gerrit

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Patch merged into coreboot/master: 0390112 AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'
by gerrit＠coreboot.org May 31, 2013

May 31, 2013

the following patch was just integrated into master: commit 0390112407c042211428a2aee1ab77422caab338 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Fri May 31 19:36:30 2013 +0800 AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. I have tested on Parmer. Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Reviewed-on: http://review.coreboot.org/3347 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/3347 for details. -gerrit

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New patch to review for coreboot: f25e905 AMD Hudson: Add support for the SD controller
by Dave Frodin May 31, 2013

May 31, 2013

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3348 -gerrit commit f25e90540bb440832602d497e9c05d6caa007619 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Fri May 31 08:15:57 2013 -0600 AMD Hudson: Add support for the SD controller Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/include/device/pci_ids.h | 1 + src/southbridge/amd/agesa/hudson/Makefile.inc | 1 + src/southbridge/amd/agesa/hudson/chip.h | 1 + src/southbridge/amd/agesa/hudson/sd.c | 79 +++++++++++++++++++++++++++ 4 files changed, 82 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e9e5ab7..e4e76ca 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -361,6 +361,7 @@ #define PCI_DEVICE_ID_ATI_SB900_USB_19_2 0x7808 #define PCI_DEVICE_ID_ATI_SB900_USB_20_5 0x7809 #define PCI_DEVICE_ID_ATI_SB900_GEC 0x7806 +#define PCI_DEVICE_ID_AMD_YANGTZE_SD 0x7813 #define PCI_DEVICE_ID_ATI_RS690_HT 0x7910 #define PCI_DEVICE_ID_ATI_RS740_HT 0x7911 diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 7802600..80dacdf 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -8,6 +8,7 @@ ramstage-y += sata.c ramstage-y += hda.c ramstage-y += pci.c ramstage-y += pcie.c +ramstage-y += sd.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/chip.h b/src/southbridge/amd/agesa/hudson/chip.h index d54a396..d5f14ff 100644 --- a/src/southbridge/amd/agesa/hudson/chip.h +++ b/src/southbridge/amd/agesa/hudson/chip.h @@ -28,6 +28,7 @@ struct southbridge_amd_agesa_hudson_config u32 boot_switch_sata_ide : 1; u32 hda_viddid; u8 gpp_configuration; + u8 sd_mode; #endif }; diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c new file mode 100644 index 0000000..ad30f14 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "hudson.h" + +static void sd_init(struct device *dev) +{ +u32 stepping; + + if (dev->enabled == 0) { + /* turn off the SDHC controller in the PM regs */ + outb(0xE8, PM_INDEX); + outb(0x00, PM_DATA); + return; + } + + stepping = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xFC); + + dev = dev_find_slot(0, PCI_DEVFN(0x14, 7)); + + struct southbridge_amd_agesa_hudson_config *sd_chip = + (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); + + if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + pci_write_config32(dev, 0xA4, 0x31FEC8B2); + pci_write_config32(dev, 0xA8, 0x00002503); + pci_write_config32(dev, 0xB0, 0x02180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + else { /* SD 2.0 mode */ + if ((stepping & 0x0000000F)==0) { /* Stepping A0 */ + pci_write_config32(dev, 0xA4, 0x31DE32B2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000058B); + } + else { /* Stepping >= A1 */ + pci_write_config32(dev, 0xA4, 0x31FE3FB2); + pci_write_config32(dev, 0xB0, 0x01180C19); + pci_write_config32(dev, 0xD0, 0x0000078B); + } + } +} + +static struct device_operations sd_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .scan_bus = 0, +}; + +static const struct pci_driver sd_driver __pci_driver = { + .ops = &sd_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_AMD_YANGTZE_SD, +};

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New patch to review for coreboot: 4857106 AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard'
by Siyuan Wang May 31, 2013

May 31, 2013

Siyuan Wang (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3347 -gerrit commit 48571067a93f5acbdafcb8e75bf7287a10f6fcf7 Author: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> Date: Fri May 31 19:36:30 2013 +0800 AMD Parmer: fix issue 'S3 fails to suspend after wake up from USB keyboard' This issue can be reproduced in Linux by the following steps: 1) use pm-suspend to suspend. 2) use USB keyboard to wake up. 3) use pm-suspend to suspend. FAIL To SUSPEND. The cause of this issue is: USB devices use bit 11(0x0b) of GP0_STS represents S3 wake up event, but this bit is not clear after wake up. So OS thinks there is a wake up signal and wake up immediately. In this patch, I add AcpiGpe0Blk using MMIO access and write 1 on bit 11. I have tested on Parmer. Change-Id: Iec3078bf29de99683e7cd3ef4e178fbeb4dc09c1 Signed-off-by: Siyuan Wang <SiYuan.Wang(a)amd.com> Signed-off-by: Siyuan Wang <wangsiyuanbuaa(a)gmail.com> --- src/mainboard/amd/parmer/dsdt.asl | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/amd/parmer/dsdt.asl b/src/mainboard/amd/parmer/dsdt.asl index faf3ad7..3e408c8 100644 --- a/src/mainboard/amd/parmer/dsdt.asl +++ b/src/mainboard/amd/parmer/dsdt.asl @@ -202,6 +202,14 @@ DefinitionBlock ( /* PM1 Event Block * First word is PM1_Status, Second word is PM1_Enable */ + + /* AcpiGpe0Blk */ + OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) + Field(GP0B, ByteAcc, NoLock, Preserve) { + , 11, + USBS, 1, + } + Scope(\_SB) { /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ OperationRegion(PCFG, SystemMemory, PCBA, PCLN) @@ -844,6 +852,7 @@ DefinitionBlock ( * Store(Arg0, Index(WKST,1)) * } */ + Store(1, USBS) Return(WKST) } /* End Method(\_WAK) */

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New patch to review for coreboot: 32393b0 qemu: add southbridge devices to device tree
by Gerd Hoffmann May 31, 2013

May 31, 2013

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3346 -gerrit commit 32393b059d0b18b70ecbeb7f8ca311089b7f27bc Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri May 31 13:39:24 2013 +0200 qemu: add southbridge devices to device tree Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-x86/devicetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index eebe3d4..9f38cc5 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -8,8 +8,10 @@ chip mainboard/emulation/qemu-x86 device pci 0.0 on end chip southbridge/intel/i82371eb # southbridge - device pci 01.0 on end - device pci 01.1 on end + device pci 01.0 on end # ISA bridge + device pci 01.1 on end # IDE + device pci 01.2 on end # UHCI (only present with "qemu -usb") + device pci 01.3 on end # ACPI register "ide0_enable" = "1" register "ide1_enable" = "1" register "gpo" = "0x7fffbbff"

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New patch to review for coreboot: 26d5b56 qemu: add x86 cpu
by Gerd Hoffmann May 31, 2013

May 31, 2013

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3344 -gerrit commit 26d5b56f46f04e1ed2ef9005657eceb4bb837aed Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri May 31 09:23:26 2013 +0200 qemu: add x86 cpu This patch adds a qemu x86 cpu chip. It has no initialization function as this isn't needed on virtual hardware. A virtual machine can have pretty much any CPU: qemu emulates a wide range of x86 CPUs (try 'qemu -cpu ? for a list), also with 'qemu -cpu host' the guest will see a cpu which is (almost) identical to the one on the host machine. So I've added X86_VENDOR_ANY as wildcard match for the cpu_table. Change-Id: Ib01210694b09702e41ed806f31d0033e840a863f Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/arch/x86/include/arch/cpu.h | 1 + src/arch/x86/lib/cpu.c | 3 +++ src/cpu/Kconfig | 1 + src/cpu/Makefile.inc | 1 + src/cpu/qemu-x86/Kconfig | 22 ++++++++++++++++++++++ src/cpu/qemu-x86/Makefile.inc | 22 ++++++++++++++++++++++ src/cpu/qemu-x86/qemu.c | 37 +++++++++++++++++++++++++++++++++++++ 7 files changed, 87 insertions(+) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 1fe12e5..7363132 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -138,6 +138,7 @@ static inline unsigned int cpuid_edx(unsigned int op) #define X86_VENDOR_TRANSMETA 8 #define X86_VENDOR_NSC 9 #define X86_VENDOR_SIS 10 +#define X86_VENDOR_ANY 0xfe #define X86_VENDOR_UNKNOWN 0xff #if !defined(__PRE_RAM__) && !defined(__SMM__) diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c index be8e38d..2a855f8 100644 --- a/src/arch/x86/lib/cpu.c +++ b/src/arch/x86/lib/cpu.c @@ -223,6 +223,9 @@ struct cpu_driver *find_cpu_driver(struct device *cpu) { return driver; } + if (X86_VENDOR_ANY == id->vendor) { + return driver; + } } } return NULL; diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index dd28cb7..d1e5237 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -14,6 +14,7 @@ if ARCH_X86 source src/cpu/amd/Kconfig source src/cpu/intel/Kconfig source src/cpu/via/Kconfig +source src/cpu/qemu-x86/Kconfig source src/cpu/x86/Kconfig config CACHE_AS_RAM diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc index 25ef424..8b9d074 100644 --- a/src/cpu/Makefile.inc +++ b/src/cpu/Makefile.inc @@ -8,6 +8,7 @@ subdirs-y += samsung subdirs-y += ti subdirs-y += via subdirs-y += x86 +subdirs-$(CONFIG_CPU_QEMU_X86) += qemu-x86 ################################################################################ ## Rules for building the microcode blob in CBFS diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig new file mode 100644 index 0000000..127a4c6 --- /dev/null +++ b/src/cpu/qemu-x86/Kconfig @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_QEMU_X86 + bool + diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc new file mode 100644 index 0000000..028f5a5 --- /dev/null +++ b/src/cpu/qemu-x86/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-y += qemu.c +subdirs-y += ../x86/mtrr +subdirs-y += ../x86/lapic + diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c new file mode 100644 index 0000000..c27a1ee --- /dev/null +++ b/src/cpu/qemu-x86/qemu.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cpu/cpu.h> +#include <device/device.h> + +static struct device_operations cpu_dev_ops = { +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_ANY, 0 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + +struct chip_operations cpu_x86_qemu_ops = { + CHIP_NAME("QEMU x86 CPU") +};

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New patch to review for coreboot: 1c6263c qemu: windup new cpu chip
by Gerd Hoffmann May 31, 2013

May 31, 2013

Gerd Hoffmann (kraxel(a)redhat.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3345 -gerrit commit 1c6263c542b579b52598d693f60d98acece28f61 Author: Gerd Hoffmann <kraxel(a)redhat.com> Date: Fri May 31 09:26:55 2013 +0200 qemu: windup new cpu chip Add boot cpu to the device tree. Figure the number of CPUs installed and add cpu devices for them, so they show up in all generated BIOS tables correctly. This gets SMP going. Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644 Signed-off-by: Gerd Hoffmann <kraxel(a)redhat.com> --- src/mainboard/emulation/qemu-x86/Kconfig | 1 + src/mainboard/emulation/qemu-x86/devicetree.cb | 5 +++ src/mainboard/emulation/qemu-x86/northbridge.c | 46 ++++++++++++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/src/mainboard/emulation/qemu-x86/Kconfig b/src/mainboard/emulation/qemu-x86/Kconfig index bf21acd..f816794 100644 --- a/src/mainboard/emulation/qemu-x86/Kconfig +++ b/src/mainboard/emulation/qemu-x86/Kconfig @@ -3,6 +3,7 @@ if BOARD_EMULATION_QEMU_X86 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select ARCH_X86 + select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82371EB select CACHE_AS_RAM select HAVE_OPTION_TABLE diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb index ed64eef..eebe3d4 100644 --- a/src/mainboard/emulation/qemu-x86/devicetree.cb +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -1,4 +1,9 @@ chip mainboard/emulation/qemu-x86 + device cpu_cluster 0 on + chip cpu/qemu-x86 + device lapic 0 on end + end + end device domain 0 on device pci 0.0 on end diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c index d785beb..8b9d402 100644 --- a/src/mainboard/emulation/qemu-x86/northbridge.c +++ b/src/mainboard/emulation/qemu-x86/northbridge.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <cpu/cpu.h> #include <cpu/x86/lapic_def.h> #include <arch/io.h> #include <arch/ioapic.h> @@ -11,6 +12,8 @@ #include <smbios.h> #include <cbmem.h> +#include "fw_cfg.h" + #include "memory.c" static void cpu_pci_domain_set_resources(device_t dev) @@ -130,6 +133,46 @@ static struct device_operations pci_domain_ops = { #endif }; +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static unsigned int cpu_bus_scan(device_t bus, unsigned int max) +{ + int max_cpus = fw_cfg_max_cpus(); + device_t cpu; + int i; + + if (max_cpus < 0) + return 0; + + /* + * TODO: This only handles the simple "qemu -smp $nr" case + * correctly. qemu also allows to also specify number of + * cores, threads & sockets. + */ + printk(BIOS_INFO, "QEMU: max_cpus is %d\n", max_cpus); + for (i = 0; i < max_cpus; i++) { + cpu = add_cpu_device(bus->link_list, i, 1); + if (cpu) + set_cpu_topology(cpu, 1, 0, i, 0); + } + return max_cpus; +} + +static void cpu_bus_noop(device_t dev) +{ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = cpu_bus_noop, + .set_resources = cpu_bus_noop, + .enable_resources = cpu_bus_noop, + .init = cpu_bus_init, + .scan_bus = cpu_bus_scan, +}; + static void northbridge_enable(struct device *dev) { /* Set the operations if it is a special bus type */ @@ -137,6 +180,9 @@ static void northbridge_enable(struct device *dev) dev->ops = &pci_domain_ops; pci_set_method(dev); } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } } struct chip_operations mainboard_emulation_qemu_x86_ops = {

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