Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81923?usp=email )
Change subject: mb/asus/p8z77-m[_pro]: Blink power LED during suspend
......................................................................
mb/asus/p8z77-m[_pro]: Blink power LED during suspend
Set GPIO27 of PCH to blink before going to sleep. This blinks the
power LED. Revert after waking up.
Tested on p8z77-m. Power LED blinks in suspend.
Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Signed-off-by: Keith Hui <buurin(a)gmail.com>
---
M src/mainboard/asus/p8x7x-series/acpi/platform.asl
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/81923/1
diff --git a/src/mainboard/asus/p8x7x-series/acpi/platform.asl b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
index 7da03bf..b16ced5 100644
--- a/src/mainboard/asus/p8x7x-series/acpi/platform.asl
+++ b/src/mainboard/asus/p8x7x-series/acpi/platform.asl
@@ -2,9 +2,19 @@
Method(_PTS, 1)
{
+#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
+ /* blink power LED if not turning off */
+ If (Arg0 != 0x05)
+ {
+ GB27 = 1
+ }
+#endif
}
Method(_WAK, 1)
{
+#if (CONFIG(BOARD_ASUS_P8Z77_M) || CONFIG(BOARD_ASUS_P8Z77_M_PRO))
+ GB27 = 0
+#endif
Return(Package(){0, 0})
}
--
To view, visit https://review.coreboot.org/c/coreboot/+/81923?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Gerrit-Change-Number: 81923
Gerrit-PatchSet: 1
Gerrit-Owner: Keith Hui <buurin(a)gmail.com>
Gerrit-MessageType: newchange
Attention is currently required from: Karthik Ramasubramanian, Shelley Chen.
Hello Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81817?usp=email
to look at the new patch set (#5).
Change subject: mb/google/brox: Create lotso variant
......................................................................
mb/google/brox: Create lotso variant
Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO
Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/Kconfig.name
A src/mainboard/google/brox/variants/lotso/Makefile.mk
A src/mainboard/google/brox/variants/lotso/gpio.c
A src/mainboard/google/brox/variants/lotso/include/variant/ec.h
A src/mainboard/google/brox/variants/lotso/include/variant/gpio.h
A src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
A src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/lotso/overridetree.cb
10 files changed, 84 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/81817/5
--
To view, visit https://review.coreboot.org/c/coreboot/+/81817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Gerrit-Change-Number: 81817
Gerrit-PatchSet: 5
Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Attention: Shelley Chen <shchen(a)google.com>
Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Kun Liu, Shelley Chen.
Hello Shelley Chen, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81817?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/google/brox: Create lotso variant
......................................................................
mb/google/brox: Create lotso variant
Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO
Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brox/Kconfig
M src/mainboard/google/brox/Kconfig.name
A src/mainboard/google/brox/variants/lotso/Makefile.mk
A src/mainboard/google/brox/variants/lotso/gpio.c
A src/mainboard/google/brox/variants/lotso/include/variant/ec.h
A src/mainboard/google/brox/variants/lotso/include/variant/gpio.h
A src/mainboard/google/brox/variants/lotso/memory/Makefile.mk
A src/mainboard/google/brox/variants/lotso/memory/dram_id.generated.txt
A src/mainboard/google/brox/variants/lotso/memory/mem_parts_used.txt
A src/mainboard/google/brox/variants/lotso/overridetree.cb
10 files changed, 83 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/81817/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/81817?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Gerrit-Change-Number: 81817
Gerrit-PatchSet: 4
Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com>
Gerrit-Attention: Shelley Chen <shchen(a)google.com>
Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>
Gerrit-MessageType: newpatchset
Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57503?usp=email )
Change subject: sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
......................................................................
sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
Program the AER capability header register in a single write because
it's write-once. In addition, only PCH-LP supports L1 sub-states, so
only report the L1 sub-state capability on PCH-LP. This follows what
Lynx Point PCH reference code version 1.9.1 does.
Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57503
Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/southbridge/intel/lynxpoint/pcie.c
1 file changed, 14 insertions(+), 12 deletions(-)
Approvals:
Lean Sheng Tan: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 30a34f7..766ed43 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -670,20 +670,22 @@
/* Set EOI forwarding disable. */
pci_or_config32(dev, 0xd4, 1 << 1);
- /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */
- if (CONFIG(PCIEXP_AER))
- pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29) | 0x10001);
- else
- pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
+ /* Set AER Extended Cap ID to 01h */
+ u32 aech = CONFIG(PCIEXP_AER) ? 0x10001 : 0;
- /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
- if (CONFIG(PCIEXP_L1_SUB_STATE))
- pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
- else
- pci_update_config32(dev, 0x200, ~0xfffff, 0);
-
+ /* For PCH-LP, set Next Cap Pointer to 200h. */
if (is_lp)
- pci_or_config32(dev, 0x100, 1 << 29);
+ aech |= 1 << 29;
+
+ pci_update_config32(dev, 0x100, ~0xfffff, aech);
+
+ if (is_lp) {
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
+ if (CONFIG(PCIEXP_L1_SUB_STATE))
+ pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
+ else
+ pci_update_config32(dev, 0x200, ~0xfffff, 0);
+ }
/* Read and write back write-once capability registers. */
pci_update_config32(dev, 0x34, ~0, 0);
--
To view, visit https://review.coreboot.org/c/coreboot/+/57503?usp=email
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035
Gerrit-Change-Number: 57503
Gerrit-PatchSet: 7
Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com>
Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Martin L Roth <gaumless(a)gmail.com>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-MessageType: merged