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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Completed test. Should we close open for this patch?
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Change subject: drivers/pc80/tpm: Support Xeon-SP
......................................................................
Patch Set 7:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/81276/comment/49c62053_41917cb4 :
PS5, Line 806: assert(domain);
: if (domain)
> Patrick, Nico, […]
Done
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Change subject: drivers/pc80/tpm: Support Xeon-SP
......................................................................
Patch Set 7:
(1 comment)
File src/drivers/pc80/tpm/tis.c:
https://review.coreboot.org/c/coreboot/+/81276/comment/8ab9848f_457dbf30 :
PS5, Line 806: assert(domain);
: if (domain)
> Why both?
Patrick, Nico,
This patch is needed in topic of 'Dyn-SSDT' for SPR and hence I made a rebase of it. I tentatively make a revise here and hope this is okay for both of you.
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Hello Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
......................................................................
soc/intel/xeon_sp/spr: Support dynamic domain SSDT generation
Domain SSDT is dynamically generated by soc_pci_domain_fill_ssdt.
SPR has 2 SKUs, XCC and MCC. Dynamic domain SSDT generation could
better fit both. One possible side-effect might be the extra
performance cost for generating these tables, which should not bring
big impact on high performance server CPUs.
TEST=Build and boot intel/archercity CRB
Linux ACPI host bridge parsing logs are kept the same before and
after, with below issue fixed.
[ 5.124087] ACPI BIOS Error (bug): Could not resolve symbol
[\_SB.PC16], AE_NOT_FOUND (20221020/dswload2-162)
[ 5.124087] ACPI Error: AE_NOT_FOUND, During name lookup/catalog
(20221020/psobject-220)
[ 5.124087] ACPI: Skipping parse of AML opcode: OpcodeName
unavailable (0x0010)
Change-Id: Icc5843feadc840d87c49b2aa4259716264520dba
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
D src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
D src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
D src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/uncore.asl
M src/soc/intel/xeon_sp/spr/ioat.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
11 files changed, 105 insertions(+), 327 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81377/20
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Change subject: device/device_util: Rename dev_get_pci_domain
......................................................................
device/device_util: Rename dev_get_pci_domain
In coreboot, domain indicates hardware units that provide/group
resource windows, For Xeon-SP, domains are PCIe compatible and
further function in many aspects, e.g. PCIe, CXL, IOAT, UBOX.
Rename dev_get_pci_domain to dev_get_domain to align with coreboot
concept and distinguish from Xeon-SP concept.
TEST=Build and boot on intel/archercity CRB
Change-Id: I51b18b30fb41038869ea1384b01091da31a895b9
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/device/device_util.c
M src/drivers/pc80/tpm/tis.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
6 files changed, 15 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/81554/8
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Change subject: drivers/pc80/tpm: Support Xeon-SP
......................................................................
drivers/pc80/tpm: Support Xeon-SP
On Xeon-SP the first PCI domain isn't named PCI0 and thus the TPM
ACPI code fails to evaluate. Instead of hardcoding an ACPI path
use the domain name set in the SoC chip_ops.
TEST=Build and boot on intel/archercity CRB
Below issue is fixed,
ACPI BIOS Error (bug): Could not resolve symbol [\_SB.PCI0],
AE_NOT_FOUND (20200925/dswload2-163)
ACPI Error: AE_NOT_FOUND, During name lookup/catalog
(20200925/psobject-221)
ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010)
Change-Id: I6130b937ec81bbde78d2619eb859ecf354fc3854
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/drivers/pc80/tpm/tis.c
1 file changed, 12 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81276/7
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Change subject: device/device_util: Use const qualifier
......................................................................
device/device_util: Use const qualifier
Allows to use the function in more places that expect the
struct device to be readonly.
TEST=Build and boot on intel/archercity CRB
Change-Id: Iac04fe6931a43070f6638b399adbff2ce64829c9
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---
M src/device/device_util.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/uncore_acpi.c
5 files changed, 22 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/81275/20
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Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
......................................................................
acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
Besides code movement, improvements are made,
1. Firmware granted features are passed as parameters.
2. Rename to acpigen_write_OSC_pci_domain_fixed_caps to reflect
that the runtime change of firmware setting is not supported.
3. Aligned to Linux 5.19.rc8 that CXL UUID _OSC call will handle
PCIe bits as well.
4. Add TODO for control bits suppression based on OS supports.
5. Update control flag definitions according to Linux 5.19.rc8.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/acpi/acpigen_pci.c
M src/include/acpi/acpigen_pci.h
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
4 files changed, 318 insertions(+), 316 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81652/4
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