April 2024 - coreboot-gerrit - mail.coreboot.org

[XS] Change in coreboot[main]: sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
by Matt DeVillier (Code Review) April 16, 2024

April 16, 2024

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57502?usp=email ) Change subject: sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask ...................................................................... sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask Lynx Point PCH reference code version 1.9.1 masks the upper 4 bits of the PCIe root port register at offset 0xf5. Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57502 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index fd41ce8..30a34f7 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -662,7 +662,7 @@ /* Set Invalid Receive Range Check Enable in MPC register. */ pci_or_config32(dev, 0xd8, 1 << 25); - pci_and_config8(dev, 0xf5, 0x3f); + pci_and_config8(dev, 0xf5, 0x0f); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) pci_and_config8(dev, 0xf7, ~0x0c); -- To view, visit https://review.coreboot.org/c/coreboot/+/57502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Gerrit-Change-Number: 57502 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: lynxpoint/broadwell: Correct L1 exit latency with ASPM
by Matt DeVillier (Code Review) April 16, 2024

April 16, 2024

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57501?usp=email ) Change subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM ...................................................................... lynxpoint/broadwell: Correct L1 exit latency with ASPM Lynx Point PCH reference code version 1.9.1 programs the larger L1 exit latency when ASPM is enabled. Document 535127 (BDW PCH-LP BS) also does the same. Correct the condition accordingly. On Lynx Point, also remove a now-redundant write to the LCAP register (offset 0x4c). Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57501 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/broadwell/pch/pcie.c M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 2 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 966a25d..4847da6 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -522,7 +522,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 0c17c9c..fd41ce8 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -570,9 +570,6 @@ /* Set unique clock exit latency in MPC register. */ pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); - /* Set L1 exit latency in LCAP register. */ - pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); - if (is_lp) { switch (rp) { case 1: @@ -650,7 +647,7 @@ pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ - if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) + if ((pci_read_config8(dev, 0xf5) & 0x1) || do_aspm) pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); -- To view, visit https://review.coreboot.org/c/coreboot/+/57501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Gerrit-Change-Number: 57501 Gerrit-PatchSet: 7 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Anil Kumar K (Code Review) April 16, 2024

April 16, 2024

Attention is currently required from: Anil Kumar K. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81920?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... drivers/soundwire: Support Realtek ALC722 codec This patch adds soundwire driver to support ALC722 audio codec. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc722 register "desc" = ""Headset Codec"" device generic 0.1 on end end TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 --- A src/drivers/soundwire/alc722/Kconfig A src/drivers/soundwire/alc722/Makefile.mk A src/drivers/soundwire/alc722/alc722.c A src/drivers/soundwire/alc722/chip.h M src/include/mipi/ids.h 5 files changed, 176 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81920/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 4 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-CC: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Anil Kumar K (Code Review) April 16, 2024

April 16, 2024

Attention is currently required from: Anil Kumar K. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81920?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... drivers/soundwire: Support Realtek ALC722 codec This patch adds soundwire driver to support ALC722 audio codec. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc722 register "desc" = ""Headset Codec"" device generic 0.1 on end end TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 --- A src/drivers/soundwire/alc722/Kconfig A src/drivers/soundwire/alc722/Makefile.mk A src/drivers/soundwire/alc722/alc722.c A src/drivers/soundwire/alc722/chip.h M src/include/mipi/ids.h 5 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81920/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-CC: Sathya Prakash M R <sathya.prakash.m.r(a)intel.com> Gerrit-CC: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-CC: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Anil Kumar K (Code Review) April 16, 2024

April 16, 2024

Anil Kumar K has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/81920?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... drivers/soundwire: Support Realtek ALC722 codec This patch adds soundwire driver to support ALC722 audio codec. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc722 register "desc" = ""Headset Codec"" device generic 0.1 on end end TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 --- A src/drivers/soundwire/alc722/Kconfig A src/drivers/soundwire/alc722/Makefile.mk A src/drivers/soundwire/alc722/alc722.c A src/drivers/soundwire/alc722/chip.h M src/include/mipi/ids.h 5 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81920/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 2 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC722 codec
by Anil Kumar K (Code Review) April 16, 2024

April 16, 2024

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81920?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC722 codec ...................................................................... drivers/soundwire: Support Realtek ALC722 codec This patch adds soundwire driver to support ALC722 audio codec. The ACPI address for the codec is calculated with the information in the codec driver combined with the devicetree.cb hierarchy where the link and unique IDs are extracted from the device path. For example this device is connected to master link ID 0 and has strap settings configuring it for unique ID 1: chip drivers/soundwire/alc722 register "desc" = ""Headset Codec"" device generic 0.1 on end end TEST=This driver was tested on Intel RVP with on board ALC722 codec by booting and disassembling the runtime SSDT to ensure that the devices have the expected address and properties. Test soundcard binding works and devices are detected and check for audio playback. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 --- A src/drivers/soundwire/alc722/Kconfig A src/drivers/soundwire/alc722/Makefile.mk A src/drivers/soundwire/alc722/alc722.c A src/drivers/soundwire/alc722/chip.h M src/include/mipi/ids.h 5 files changed, 174 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81920/1 diff --git a/src/drivers/soundwire/alc722/Kconfig b/src/drivers/soundwire/alc722/Kconfig new file mode 100644 index 0000000..8d7d6df --- /dev/null +++ b/src/drivers/soundwire/alc722/Kconfig @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config DRIVERS_SOUNDWIRE_ALC722 + bool diff --git a/src/drivers/soundwire/alc722/Makefile.mk b/src/drivers/soundwire/alc722/Makefile.mk new file mode 100644 index 0000000..ca59033 --- /dev/null +++ b/src/drivers/soundwire/alc722/Makefile.mk @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVERS_SOUNDWIRE_ALC722) += alc722.c diff --git a/src/drivers/soundwire/alc722/alc722.c b/src/drivers/soundwire/alc722/alc722.c new file mode 100644 index 0000000..5e15bd0 --- /dev/null +++ b/src/drivers/soundwire/alc722/alc722.c @@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <acpi/acpi_device.h> +#include <acpi/acpi_soundwire.h> +#include <device/device.h> +#include <device/soundwire.h> +#include <mipi/ids.h> +#include <stdio.h> + +#include "chip.h" + +static struct soundwire_address alc722_address = { + .version = SOUNDWIRE_VERSION_1_2, + .manufacturer_id = MIPI_MFG_ID_REALTEK, + .part_id = MIPI_DEV_ID_REALTEK_ALC722, + .class = MIPI_CLASS_SDCA +}; + +static struct soundwire_slave alc722_slave = { + .wake_up_unavailable = false, + .test_mode_supported = false, + .clock_stop_mode1_supported = true, + .simplified_clockstopprepare_sm_supported = true, + .clockstopprepare_hard_reset_behavior = false, + .highPHY_capable = false, + .paging_supported = false, + .bank_delay_supported = false, + .port15_read_behavior = false, + .source_port_list = SOUNDWIRE_PORT(2), + .sink_port_list = SOUNDWIRE_PORT(1), +}; + +static struct soundwire_audio_mode alc722_audio_mode = { + /* Bus frequency must be 1/2/4/8 divider of supported input frequencies. */ + .bus_frequency_configs_count = 12, + .bus_frequency_configs = { + 9600 * KHz, + 4800 * KHz, + 2400 * KHz, + 1200 * KHz, + 12000 * KHz, + 6000 * KHz, + 3000 * KHz, + 1500 * KHz, + 12288 * KHz, + 6144 * KHz, + 3072 * KHz, + 1536 * KHz + }, + /* Support 16 KHz to 192 KHz sampling frequency */ + .sampling_frequency_configs_count = 9, + .sampling_frequency_configs = { + 16 * KHz, + 22.05 * KHz, + 24 * KHz, + 32 * KHz, + 44.1 * KHz, + 48 * KHz, + 88.2 * KHz, + 96 * KHz, + 192 * KHz + }, + .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY +}; + +static struct soundwire_dpn alc722_dp = { + .port_wordlength_configs_count = 1, + .port_wordlength_configs = { 32 }, + .data_port_type = FULL_DATA_PORT, + .max_grouping_supported = BLOCK_GROUP_COUNT_1, + .simplified_channelprepare_sm = false, + .imp_def_dpn_interrupts_supported = 0, + .min_channel_number = 1, + .max_channel_number = 2, + .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | + MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, + .block_packing_mode = true, + .port_audio_mode_count = 1, + .port_audio_mode_list = { 0 } +}; + +static const struct soundwire_codec alc722_codec = { + .slave = &alc722_slave, + .audio_mode = { &alc722_audio_mode }, + .dpn = { + { + /* Data Input for Speaker Path */ + .port = 1, + .sink = &alc722_dp + }, + { + /* Data Output for DSP Path */ + .port = 2, + .source = &alc722_dp + } + } + +}; + +static void soundwire_alc722_fill_ssdt(const struct device *dev) +{ + struct drivers_soundwire_alc722_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_dp *dsd; + + if (!scope) + return; + + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + + /* Set codec address IDs. */ + alc722_address.link_id = dev->path.generic.id; + alc722_address.unique_id = dev->path.generic.subid; + + acpigen_write_ADR_soundwire_device(&alc722_address); + acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); + acpigen_write_STA(acpi_device_status(dev)); + + dsd = acpi_dp_new_table("_DSD"); + soundwire_gen_codec(dsd, &alc722_codec, NULL); + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *soundwire_alc722_acpi_name(const struct device *dev) +{ + struct drivers_soundwire_alc722_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return config->name; + snprintf(name, sizeof(name), "SW%1X%1X", dev->path.generic.id, dev->path.generic.subid); + return name; +} + +static struct device_operations soundwire_alc722_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = soundwire_alc722_acpi_name, + .acpi_fill_ssdt = soundwire_alc722_fill_ssdt, +}; + +static void soundwire_alc722_enable(struct device *dev) +{ + dev->ops = &soundwire_alc722_ops; +} + +struct chip_operations drivers_soundwire_alc722_ops = { + .name = "Realtek ALC722 SoundWire Codec", + .enable_dev = soundwire_alc722_enable +}; diff --git a/src/drivers/soundwire/alc722/chip.h b/src/drivers/soundwire/alc722/chip.h new file mode 100644 index 0000000..87d8b98 --- /dev/null +++ b/src/drivers/soundwire/alc722/chip.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_SOUNDWIRE_ALC722_CHIP_H__ +#define __DRIVERS_SOUNDWIRE_ALC722_CHIP_H__ + +struct drivers_soundwire_alc722_config { + const char *name; + const char *desc; +}; + +#endif /* __DRIVERS_SOUNDWIRE_ALC722_CHIP_H__ */ diff --git a/src/include/mipi/ids.h b/src/include/mipi/ids.h index 5aa5a67..4e54b62 100644 --- a/src/include/mipi/ids.h +++ b/src/include/mipi/ids.h @@ -21,6 +21,7 @@ #define MIPI_MFG_ID_REALTEK 0x025d #define MIPI_DEV_ID_REALTEK_ALC5682 0x5682 #define MIPI_DEV_ID_REALTEK_ALC711 0x0711 +#define MIPI_DEV_ID_REALTEK_ALC722 0x0722 #define MIPI_DEV_ID_REALTEK_ALC1308 0x1308 #define MIPI_MFG_ID_MAXIM 0x019f -- To view, visit https://review.coreboot.org/c/coreboot/+/81920?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieb16a1c6f3a79321fdc35987468daa8be33b6e49 Gerrit-Change-Number: 81920 Gerrit-PatchSet: 1 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/alderlake: Enable Early CrashLog support
by Benjamin Doron (Code Review) April 16, 2024

April 16, 2024

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81938?usp=email ) Change subject: soc/intel/alderlake: Enable Early CrashLog support ...................................................................... soc/intel/alderlake: Enable Early CrashLog support Perform the SoC-specific part of preparing CrashLog, by temporarily provisioning MMIO space for the CrashLog device, and calling into the early CrashLog feature. Change-Id: I1ce47531a74486bc5c996f7793af7087bc30d1f7 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/soc/intel/alderlake/bootblock/bootblock.c M src/soc/intel/alderlake/crashlog.c M src/soc/intel/alderlake/include/soc/iomap.h 3 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81938/1 diff --git a/src/soc/intel/alderlake/bootblock/bootblock.c b/src/soc/intel/alderlake/bootblock/bootblock.c index b8086a4..81de269 100644 --- a/src/soc/intel/alderlake/bootblock/bootblock.c +++ b/src/soc/intel/alderlake/bootblock/bootblock.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <intelblocks/crashlog.h> #include <intelblocks/fast_spi.h> #include <intelblocks/systemagent.h> #include <intelblocks/tco.h> @@ -26,6 +27,10 @@ void bootblock_soc_init(void) { report_platform_info(); + + if (CONFIG(SOC_INTEL_CRASHLOG)) + early_dump_pmc_and_cpu_crashlog_from_srams(); + bootblock_pch_init(); /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index ab2823b..8f5fbcb 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -23,6 +23,26 @@ static tel_crashlog_devsc_cap_t cpu_cl_devsc_cap; static cpu_crashlog_discovery_table_t cpu_cl_disc_tab; +void early_cl_enable_bars(void) +{ + /* Set CrashLog BARs (FIXME: Is there a second BAR here? Documentation doesn't say so) */ + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, (uint32_t)PCH_TEMPORARY_ADDRESS); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, 0); + + /* Enable CrashLog memory-access */ + pci_write_config16(SA_DEV_TMT, PCI_COMMAND, PCI_COMMAND_MEMORY); +} + +void early_cl_disable_bars(void) +{ + /* Clear CrashLog BARs */ + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0, 0); + pci_write_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_1, 0); + + /* Disable CrashLog memory-access */ + pci_write_config16(SA_DEV_TMT, PCI_COMMAND, 0); +} + u32 __weak cl_get_cpu_mb_int_addr(void) { return CRASHLOG_MAILBOX_INTF_ADDRESS; diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index b451a72..49d6665 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -100,6 +100,10 @@ #define EARLY_I2C_BASE_ADDRESS 0xfe020000 #define EARLY_I2C_BASE(x) (EARLY_I2C_BASE_ADDRESS + (0x2000 * (x))) +/* May be used for any purpose, but known to be used by the FSP. */ +#define PCH_TEMPORARY_ADDRESS 0xfe600000 +#define PCH_TEMPORARY_SIZE 0x200000 + #define IOM_BASE_ADDRESS 0xfbc10000 #define IOM_BASE_SIZE 0x1600 -- To view, visit https://review.coreboot.org/c/coreboot/+/81938?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ce47531a74486bc5c996f7793af7087bc30d1f7 Gerrit-Change-Number: 81938 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/common/block/crashlog: Add Early CrashLog feature
by Benjamin Doron (Code Review) April 16, 2024

April 16, 2024

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81937?usp=email ) Change subject: soc/intel/common/block/crashlog: Add Early CrashLog feature ...................................................................... soc/intel/common/block/crashlog: Add Early CrashLog feature CrashLog is a useful feature for debugging critical errors, but until now, it has only been used by ramstage code to generate an ACPI table. This doesn't help if system firmware itself contains bugs. To help with these sorts of early issues, dump any CrashLog data found to the console, where it can be retrieved as used for debugging. SoC code should call this as early as possible. While this code also does not perform the CrashLog enablement performed by some FSPs, it's assumed not necessary: it was already performed on a previous boot. Now, all that's necessary is to read the data. Change-Id: I7a02f29a3bb63ed210ab3a6812c8575569e43c07 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/soc/intel/common/block/crashlog/Makefile.mk A src/soc/intel/common/block/crashlog/early_crashlog.c M src/soc/intel/common/block/include/intelblocks/crashlog.h 3 files changed, 196 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81937/1 diff --git a/src/soc/intel/common/block/crashlog/Makefile.mk b/src/soc/intel/common/block/crashlog/Makefile.mk index 1f101c5..8868765 100644 --- a/src/soc/intel/common/block/crashlog/Makefile.mk +++ b/src/soc/intel/common/block/crashlog/Makefile.mk @@ -1,2 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CRASHLOG) += early_crashlog.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CRASHLOG) += crashlog.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CRASHLOG) += crashlog.c diff --git a/src/soc/intel/common/block/crashlog/early_crashlog.c b/src/soc/intel/common/block/crashlog/early_crashlog.c new file mode 100644 index 0000000..51c2689 --- /dev/null +++ b/src/soc/intel/common/block/crashlog/early_crashlog.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <intelblocks/crashlog.h> + +void __weak early_cl_enable_bars(void) +{ + printk(BIOS_WARNING, "%s: Operation unsupported!\n", __func__); +} + +void __weak early_cl_disable_bars(void) +{ + printk(BIOS_WARNING, "%s: Operation unsupported!\n", __func__); +} + +static bool early_cl_dump_data_from_sram(u32 src_bar, + u32 offset, + u32 size, + u32 buffer_index, + bool pmc_sram) +{ + if (src_bar == 0) { + printk(BIOS_ERR, "Invalid bar 0x%x and offset 0x%x for %s\n", + src_bar, offset, __func__); + return false; + } + + u32 src_addr = src_bar + offset; + + u32 data = read32((u32 *)src_addr); + + /* First 32bits of the record must not be 0xdeadbeef */ + if (data == INVALID_CRASHLOG_RECORD) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x\n", + data, offset, src_bar); + return false; + } + + /* PMC: copy if 1st DWORD in buffer is not zero and its 31st bit is not set */ + if (pmc_sram && !(data && !(data & BIT(31)))) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" + " of PMC SRAM.\n", data, offset, src_bar); + return false; + } + /*CPU: don't copy if 1st DWORD in first buffer is zero */ + if (!pmc_sram && !data && (buffer_index == 0)) { + printk(BIOS_DEBUG, "Invalid data 0x%x at offset 0x%x from addr 0x%x" + " of telemetry SRAM.\n", data, offset, src_bar); + return false; + } + + printk(BIOS_DEBUG, "%s (buffer %d):\n", pmc_sram ? "PMC SRAM" : "CPU SRAM", buffer_index); + + u32 copied = 0; + while (copied < size) { + /* DW by DW copy: byte access to PMC SRAM not allowed */ + data = read32((u32 *)src_addr); + printk(BIOS_DEBUG, "0x%x 0x%x 0x%x 0x%x ", + (data & 0xff000000) >> 24, + (data & 0x00ff0000) >> 16, + (data & 0x0000ff00) >> 8, + (data & 0x000000ff)); + + src_addr += 4; + copied++; + + if (copied % 4 == 0) + printk(BIOS_DEBUG, "\n"); + } + + printk(BIOS_DEBUG, "\n"); + return true; +} + +static void early_cl_dump_pmc_sram_data(void) +{ + u32 tmp_bar_addr = cl_get_cpu_tmp_bar(); + u32 pmc_crashLog_size = cl_get_pmc_record_size(); + + if (!cl_pmc_sram_has_mmio_access() || !tmp_bar_addr) { + printk(BIOS_DEBUG, "%s: unable to collect data.\n", __func__); + return; + } + + pmc_ipc_discovery_buf_t discovery_buf = cl_get_pmc_discovery_buf(); + + if (discovery_buf.bits.supported != 1) { + printk(BIOS_DEBUG, "PCH crashlog feature not supported.\n"); + return; + } + + /* Get the size of data to copy */ + if (discovery_buf.bits.discov_mechanism == 1) { + if (discovery_buf.bits.base_offset & BIT(31)) { + printk(BIOS_DEBUG, "PCH discovery to be used is disabled.\n"); + return; + } + printk(BIOS_DEBUG, "PMC crashLog size in discovery mode : 0x%X\n", + pmc_crashLog_size); + } else { + if (discovery_buf.bits.dis) { + printk(BIOS_DEBUG, "PCH crashlog is disabled in legacy mode.\n"); + return; + } + pmc_crashLog_size = (discovery_buf.bits.size != 0) ? + discovery_buf.bits.size : 0xC00; + printk(BIOS_DEBUG, "PMC crashLog size in legacy mode : 0x%X\n", + pmc_crashLog_size); + } + + bool pmc_sram = true; + pmc_crashlog_desc_table_t descriptor_table = cl_get_pmc_descriptor_table(); + + if (discovery_buf.bits.discov_mechanism == 1) { + for (int i = 0; i < descriptor_table.numb_regions; i++) { + early_cl_dump_data_from_sram(tmp_bar_addr, + descriptor_table.regions[i].bits.offset, + descriptor_table.regions[i].bits.size, + i, + pmc_sram); + } + } else { + early_cl_dump_data_from_sram(tmp_bar_addr, + discovery_buf.bits.base_offset, + discovery_buf.bits.size, + 0, + pmc_sram); + } +} + +static void early_cl_dump_cpu_sram_data(void) +{ + u32 cpu_bar_addr = cl_get_cpu_bar_addr(); + u32 cpu_crashLog_size = cl_get_cpu_record_size(); + + if (cpu_crashLog_size < 1) { + printk(BIOS_DEBUG, "%s: no data to collect.\n", __func__); + return; + } + + cpu_crashlog_discovery_table_t cpu_cl_disc_tab = cl_get_cpu_discovery_table(); + + printk(BIOS_DEBUG, "CPU crash data size: 0x%X bytes in 0x%X region(s).\n", + cpu_crashLog_size, cpu_cl_disc_tab.header.fields.count); + + bool pmc_sram = false; + for (int i = 0; i < cpu_cl_disc_tab.header.fields.count; i++) { + if (!cpu_cl_disc_tab.buffers[i].fields.size) { + continue; + } + + if (early_cl_dump_data_from_sram(cpu_bar_addr, + cpu_cl_disc_tab.buffers[i].fields.offset, + cpu_cl_disc_tab.buffers[i].fields.size, + i, + pmc_sram)) { + } else { + /* for CPU skip all buffers if the 1st one is not valid */ + if (i == 0) + break; + } + } +} + +void early_dump_pmc_and_cpu_crashlog_from_srams(void) +{ + early_cl_enable_bars(); + + if (!discover_crashlog()) { + printk(BIOS_DEBUG, "Early CrashLog: not found\n"); + goto end; + } + + if (pmc_crashlog_support() && cl_pmc_data_present() + && (cl_get_pmc_record_size() > 0)) { + early_cl_dump_pmc_sram_data(); + } else { + printk(BIOS_DEBUG, "Skipping PMC crashLog collection. Data not present.\n"); + } + + if (cpu_crashlog_support() && cl_cpu_data_present() + && (cl_get_cpu_record_size() > 0)) { + early_cl_dump_cpu_sram_data(); + } else { + printk(BIOS_DEBUG, "Skipping CPU crashLog collection. Data not present.\n"); + } + +end: + early_cl_disable_bars(); +} diff --git a/src/soc/intel/common/block/include/intelblocks/crashlog.h b/src/soc/intel/common/block/include/intelblocks/crashlog.h index ff80b1c..5659ec6 100644 --- a/src/soc/intel/common/block/include/intelblocks/crashlog.h +++ b/src/soc/intel/common/block/include/intelblocks/crashlog.h @@ -222,6 +222,9 @@ u32 buffer_index, bool pmc_sram); void collect_pmc_and_cpu_crashlog_from_srams(cl_node_t *head); +void early_cl_enable_bars(void); +void early_cl_disable_bars(void); +void early_dump_pmc_and_cpu_crashlog_from_srams(void); static const EFI_GUID FW_ERR_SECTION_GUID = { 0x81212a96, 0x09ed, 0x4996, { 0x94, 0x71, 0x8d, 0x72, 0x9c, 0x8e, 0x69, 0xed } -- To view, visit https://review.coreboot.org/c/coreboot/+/81937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a02f29a3bb63ed210ab3a6812c8575569e43c07 Gerrit-Change-Number: 81937 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[main]: soc/intel/alderlake: Refactor CrashLog BAR helpers
by Benjamin Doron (Code Review) April 16, 2024

April 16, 2024

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik. Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81936?usp=email ) Change subject: soc/intel/alderlake: Refactor CrashLog BAR helpers ...................................................................... soc/intel/alderlake: Refactor CrashLog BAR helpers To enable early CrashLog dumping in bootblock, we cannot use the resource allocator's helpers. These functions only get the BAR, so just read it directly from the PCI config space. Change-Id: Ic4d1d9d19b4b81e5e90f18ae0c03d1c34d3724eb Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/soc/intel/alderlake/Makefile.mk M src/soc/intel/alderlake/crashlog.c M src/soc/intel/common/block/pmc/Makefile.mk 3 files changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81936/1 diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea..7227e9c 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -16,6 +16,7 @@ bootblock-y += bootblock/report_platform.c bootblock-y += espi.c bootblock-y += p2sb.c +bootblock-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c diff --git a/src/soc/intel/alderlake/crashlog.c b/src/soc/intel/alderlake/crashlog.c index 5a08c25..ab2823b 100644 --- a/src/soc/intel/alderlake/crashlog.c +++ b/src/soc/intel/alderlake/crashlog.c @@ -33,7 +33,6 @@ { uintptr_t sram_bar; const struct device *dev; - struct resource *res; dev = pcidev_path_on_root(PCH_DEVFN_SRAM); if (!dev) { @@ -41,15 +40,13 @@ return 0; } - res = probe_resource(dev, PCI_BASE_ADDRESS_0); - if (!res) { + sram_bar = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + if (!sram_bar) { printk(BIOS_ERR, "PCH SRAM device not found!\n"); return 0; } - /* Get the base address of the resource */ - sram_bar = res->base; - return sram_bar; } @@ -226,6 +223,8 @@ bool cpu_cl_discovery(void) { + u32 base_addr = 0; + memset(&cpu_cl_devsc_cap, 0, sizeof(tel_crashlog_devsc_cap_t)); if (!cpu_cl_get_capability(&cpu_cl_devsc_cap)) { @@ -236,8 +235,12 @@ m_cpu_crashLog_support = true; - const struct resource *res = find_resource(SA_DEV_TMT, PCI_BASE_ADDRESS_0); - printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%llX\n", res->base); + /* Resource may be indicated by the SRAM device. Enable these together. */ + const struct device *dev = pcidev_path_on_root(PCH_DEVFN_SRAM); + if (dev) + base_addr = pci_read_config32(SA_DEV_TMT, PCI_BASE_ADDRESS_0) & + ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + printk(BIOS_DEBUG, "cpu crashlog bar addr: 0x%X\n", base_addr); if (!cpu_cl_gen_discovery_table()) { printk(BIOS_ERR, "CPU crashlog discovery table not valid.\n"); diff --git a/src/soc/intel/common/block/pmc/Makefile.mk b/src/soc/intel/common/block/pmc/Makefile.mk index ea9242b..b50af4f 100644 --- a/src/soc/intel/common/block/pmc/Makefile.mk +++ b/src/soc/intel/common/block/pmc/Makefile.mk @@ -7,6 +7,7 @@ smm-y += pmclib.c verstage-y += pmclib.c postcar-y += pmclib.c +bootblock-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc_acpi.c endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic4d1d9d19b4b81e5e90f18ae0c03d1c34d3724eb Gerrit-Change-Number: 81936 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: soc/intel/common/block/pmc: Move ACPI generation to a separate file
by Benjamin Doron (Code Review) April 16, 2024

April 16, 2024

Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81935?usp=email ) Change subject: soc/intel/common/block/pmc: Move ACPI generation to a separate file ...................................................................... soc/intel/common/block/pmc: Move ACPI generation to a separate file The PMC IPC interface may be used in stages other than ramstage. Therefore, move the ACPI specific parts, so that pmc_ipc.c can be compiled into all necessary stages. This change is needed for the follow-ups, which will dump any CrashLog data found to the console during bootblock. Change-Id: If4df90e33f6982d3eae2474db6d095a9dda7a624 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/soc/intel/common/block/pmc/Makefile.mk M src/soc/intel/common/block/pmc/pmc_ipc.c A src/soc/intel/common/block/pmc/pmc_ipc_acpi.c 3 files changed, 176 insertions(+), 149 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/81935/1 diff --git a/src/soc/intel/common/block/pmc/Makefile.mk b/src/soc/intel/common/block/pmc/Makefile.mk index e46d5ee..ea9242b 100644 --- a/src/soc/intel/common/block/pmc/Makefile.mk +++ b/src/soc/intel/common/block/pmc/Makefile.mk @@ -8,4 +8,5 @@ verstage-y += pmclib.c postcar-y += pmclib.c ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc.c +ramstage-$(CONFIG_PMC_IPC_ACPI_INTERFACE) += pmc_ipc_acpi.c endif diff --git a/src/soc/intel/common/block/pmc/pmc_ipc.c b/src/soc/intel/common/block/pmc/pmc_ipc.c index 7c811ae..3f0f27c 100644 --- a/src/soc/intel/common/block/pmc/pmc_ipc.c +++ b/src/soc/intel/common/block/pmc/pmc_ipc.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <acpi/acpigen.h> #include <device/mmio.h> #include <console/console.h> #include <delay.h> @@ -96,151 +95,3 @@ return CB_SUCCESS; } - -void pmc_ipc_acpi_fill_ssdt(void) -{ - const struct fieldlist ipcs_fields[] = { - FIELDLIST_OFFSET(PMC_IPC_CMD_OFFSET), /* Command */ - FIELDLIST_NAMESTR("ICMD", 32), /* Command Register */ - FIELDLIST_OFFSET(PMC_IPC_STS_OFFSET), /* Status */ - FIELDLIST_NAMESTR("IBSY", 1), /* Status Busy */ - FIELDLIST_NAMESTR("IERR", 1), /* Status Error */ - FIELDLIST_RESERVED(14), - FIELDLIST_NAMESTR("IERC", 8), /* Status Error Code */ - FIELDLIST_OFFSET(IPC_WBUF0), /* Write Buffer */ - FIELDLIST_NAMESTR("IWB0", 32), /* Write Buffer 0 */ - FIELDLIST_NAMESTR("IWB1", 32), /* Write Buffer 1 */ - FIELDLIST_NAMESTR("IWB2", 32), /* Write Buffer 2 */ - FIELDLIST_NAMESTR("IWB3", 32), /* Write Buffer 3 */ - FIELDLIST_OFFSET(IPC_RBUF0), /* Read Buffer */ - FIELDLIST_NAMESTR("IRB0", 32), /* Read Buffer 0 */ - FIELDLIST_NAMESTR("IRB1", 32), /* Read Buffer 1 */ - FIELDLIST_NAMESTR("IRB2", 32), /* Read Buffer 2 */ - FIELDLIST_NAMESTR("IRB3", 32), /* Read Buffer 3 */ - }; - const struct opregion ipcs_opregion = OPREGION("IPCM", SYSTEMMEMORY, - soc_read_pmc_base(), 0xff); - int i; - - /* Package with return value and read buffer. */ - acpigen_write_name("RVAL"); - acpigen_write_package(5); - for (i = 0; i < 5; ++i) - acpigen_write_integer(0); - acpigen_pop_len(); - - acpigen_write_method_serialized("IPCS", 7); - - acpigen_write_opregion(&ipcs_opregion); - acpigen_write_field("IPCM", ipcs_fields, ARRAY_SIZE(ipcs_fields), - FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); - - /* Fill write buffer data registers. */ - acpigen_write_store_op_to_namestr(ARG3_OP, "IWB0"); - acpigen_write_store_op_to_namestr(ARG4_OP, "IWB1"); - acpigen_write_store_op_to_namestr(ARG5_OP, "IWB2"); - acpigen_write_store_op_to_namestr(ARG6_OP, "IWB3"); - - /* Program the command register with command and size of write data. */ - acpigen_write_store_int_to_op(0, LOCAL0_OP); - - /* Local0 += (Arg0 << PMC_IPC_CMD_COMMAND_SHIFT) */ - acpigen_emit_byte(ADD_OP); - acpigen_emit_byte(LOCAL0_OP); - acpigen_write_shiftleft_op_int(ARG0_OP, PMC_IPC_CMD_COMMAND_SHIFT); - acpigen_emit_byte(LOCAL0_OP); - - /* Local0 += (Arg1 << PMC_IPC_CMD_SUB_COMMAND_SHIFT) */ - acpigen_emit_byte(ADD_OP); - acpigen_emit_byte(LOCAL0_OP); - acpigen_write_shiftleft_op_int(ARG1_OP, PMC_IPC_CMD_SUB_COMMAND_SHIFT); - acpigen_emit_byte(LOCAL0_OP); - - /* Local1 = PMC_IPC_CMD_NO_MSI */ - acpigen_write_store_int_to_op(PMC_IPC_CMD_NO_MSI, LOCAL1_OP); - /* Local0 += (Local1 << PMC_IPC_CMD_MSI_SHIFT) */ - acpigen_emit_byte(ADD_OP); - acpigen_emit_byte(LOCAL0_OP); - acpigen_write_shiftleft_op_int(LOCAL1_OP, PMC_IPC_CMD_MSI_SHIFT); - acpigen_emit_byte(LOCAL0_OP); - - /* Local0 += (Arg1 << PMC_IPC_CMD_SIZE_SHIFT) */ - acpigen_emit_byte(ADD_OP); - acpigen_emit_byte(LOCAL0_OP); - acpigen_write_shiftleft_op_int(ARG2_OP, PMC_IPC_CMD_SIZE_SHIFT); - acpigen_emit_byte(LOCAL0_OP); - - /* Start mailbox command with one 32bit write. */ - acpigen_write_store_op_to_namestr(LOCAL0_OP, "ICMD"); - - /* Read status register to get busy/error status. */ - acpigen_write_store_int_to_op(PMC_IPC_XFER_TIMEOUT_MS, LOCAL1_OP); - - /* While (Local1 > 0) */ - acpigen_emit_byte(WHILE_OP); - acpigen_write_len_f(); - acpigen_emit_byte(LGREATER_OP); - acpigen_emit_byte(LOCAL1_OP); - acpigen_emit_byte(ZERO_OP); - - /* If (IBSY == 0) { Return (SUCCESS) } */ - acpigen_write_if_lequal_namestr_int("IBSY", 0); - acpigen_set_package_element_int("RVAL", 0, PMC_IPC_SUCCESS); - acpigen_set_package_element_namestr("RVAL", 1, "IRB0"); - acpigen_set_package_element_namestr("RVAL", 2, "IRB1"); - acpigen_set_package_element_namestr("RVAL", 3, "IRB2"); - acpigen_set_package_element_namestr("RVAL", 4, "IRB3"); - acpigen_write_return_namestr("RVAL"); - acpigen_pop_len(); - - /* If (IERR == 1) { Return (ERROR) } */ - acpigen_write_if_lequal_namestr_int("IERR", 1); - acpigen_write_debug_string("IPCS ERROR"); - acpigen_write_debug_namestr("IERC"); - acpigen_set_package_element_int("RVAL", 0, PMC_IPC_ERROR); - acpigen_write_return_namestr("RVAL"); - acpigen_pop_len(); - - /* Sleep (1) */ - acpigen_write_sleep(1); - /* Decrement (Local1) */ - acpigen_emit_byte(DECREMENT_OP); - acpigen_emit_byte(LOCAL1_OP); - acpigen_pop_len(); /* While */ - - /* Return (TIMEOUT) */ - acpigen_write_debug_string("IPCS TIMEOUT"); - acpigen_set_package_element_int("RVAL", 0, PMC_IPC_TIMEOUT); - acpigen_write_return_namestr("RVAL"); - - acpigen_pop_len(); /* Method */ -} - -void pmc_ipc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable) -{ - const uint32_t data[] = { - 1 << clock_pin, /* Clock pin to be modified */ - (enable ? 1 : 0) << clock_pin, /* Clock pin to set */ - 1 << pcie_rp, /* PCIe root port to be modified */ - (enable ? 1 : 0) << pcie_rp, /* PCIe root port to set */ - }; - const char *method = acpi_device_path_join(pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS"); - - if (!method) { - printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__); - return; - } - - /* - * The PMC IPC mailbox method takes 7 arguments: - * IPCS (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) - */ - acpigen_emit_namestring(method); - acpigen_write_integer(PMC_IPC_CMD_ID_SET_PCIE_CLOCK); - acpigen_write_integer(0); - acpigen_write_integer(sizeof(data)); - acpigen_write_dword(data[0]); - acpigen_write_dword(data[1]); - acpigen_write_dword(data[2]); - acpigen_write_dword(data[3]); -} diff --git a/src/soc/intel/common/block/pmc/pmc_ipc_acpi.c b/src/soc/intel/common/block/pmc/pmc_ipc_acpi.c new file mode 100644 index 0000000..500e4fb --- /dev/null +++ b/src/soc/intel/common/block/pmc/pmc_ipc_acpi.c @@ -0,0 +1,175 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpigen.h> +#include <intelblocks/pmc_ipc.h> +#include <intelblocks/pmclib.h> +#include <soc/pci_devs.h> +#include <timer.h> + +/* + * WBUF register block offset 0x80..0x8f there are 4 consecutive + * 32 bit registers + */ +#define IPC_WBUF0 0x80 + +/* + * RBUF registers block offset 0x90..0x9f there are 4 consecutive + * 32 bit registers + */ +#define IPC_RBUF0 0x90 + +/* + * From Intel 500 Series PCH EDS vol2 s4.4 + */ +#define PMC_IPC_CMD_OFFSET 0x0 +#define PMC_IPC_STS_OFFSET 0x4 + +#define PMC_IPC_XFER_TIMEOUT_MS (1 * MSECS_PER_SEC) /* max 1s */ + +void pmc_ipc_acpi_fill_ssdt(void) +{ + const struct fieldlist ipcs_fields[] = { + FIELDLIST_OFFSET(PMC_IPC_CMD_OFFSET), /* Command */ + FIELDLIST_NAMESTR("ICMD", 32), /* Command Register */ + FIELDLIST_OFFSET(PMC_IPC_STS_OFFSET), /* Status */ + FIELDLIST_NAMESTR("IBSY", 1), /* Status Busy */ + FIELDLIST_NAMESTR("IERR", 1), /* Status Error */ + FIELDLIST_RESERVED(14), + FIELDLIST_NAMESTR("IERC", 8), /* Status Error Code */ + FIELDLIST_OFFSET(IPC_WBUF0), /* Write Buffer */ + FIELDLIST_NAMESTR("IWB0", 32), /* Write Buffer 0 */ + FIELDLIST_NAMESTR("IWB1", 32), /* Write Buffer 1 */ + FIELDLIST_NAMESTR("IWB2", 32), /* Write Buffer 2 */ + FIELDLIST_NAMESTR("IWB3", 32), /* Write Buffer 3 */ + FIELDLIST_OFFSET(IPC_RBUF0), /* Read Buffer */ + FIELDLIST_NAMESTR("IRB0", 32), /* Read Buffer 0 */ + FIELDLIST_NAMESTR("IRB1", 32), /* Read Buffer 1 */ + FIELDLIST_NAMESTR("IRB2", 32), /* Read Buffer 2 */ + FIELDLIST_NAMESTR("IRB3", 32), /* Read Buffer 3 */ + }; + const struct opregion ipcs_opregion = OPREGION("IPCM", SYSTEMMEMORY, + soc_read_pmc_base(), 0xff); + int i; + + /* Package with return value and read buffer. */ + acpigen_write_name("RVAL"); + acpigen_write_package(5); + for (i = 0; i < 5; ++i) + acpigen_write_integer(0); + acpigen_pop_len(); + + acpigen_write_method_serialized("IPCS", 7); + + acpigen_write_opregion(&ipcs_opregion); + acpigen_write_field("IPCM", ipcs_fields, ARRAY_SIZE(ipcs_fields), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Fill write buffer data registers. */ + acpigen_write_store_op_to_namestr(ARG3_OP, "IWB0"); + acpigen_write_store_op_to_namestr(ARG4_OP, "IWB1"); + acpigen_write_store_op_to_namestr(ARG5_OP, "IWB2"); + acpigen_write_store_op_to_namestr(ARG6_OP, "IWB3"); + + /* Program the command register with command and size of write data. */ + acpigen_write_store_int_to_op(0, LOCAL0_OP); + + /* Local0 += (Arg0 << PMC_IPC_CMD_COMMAND_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG0_OP, PMC_IPC_CMD_COMMAND_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_SUB_COMMAND_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG1_OP, PMC_IPC_CMD_SUB_COMMAND_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local1 = PMC_IPC_CMD_NO_MSI */ + acpigen_write_store_int_to_op(PMC_IPC_CMD_NO_MSI, LOCAL1_OP); + /* Local0 += (Local1 << PMC_IPC_CMD_MSI_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(LOCAL1_OP, PMC_IPC_CMD_MSI_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_SIZE_SHIFT) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG2_OP, PMC_IPC_CMD_SIZE_SHIFT); + acpigen_emit_byte(LOCAL0_OP); + + /* Start mailbox command with one 32bit write. */ + acpigen_write_store_op_to_namestr(LOCAL0_OP, "ICMD"); + + /* Read status register to get busy/error status. */ + acpigen_write_store_int_to_op(PMC_IPC_XFER_TIMEOUT_MS, LOCAL1_OP); + + /* While (Local1 > 0) */ + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_emit_byte(ZERO_OP); + + /* If (IBSY == 0) { Return (SUCCESS) } */ + acpigen_write_if_lequal_namestr_int("IBSY", 0); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_SUCCESS); + acpigen_set_package_element_namestr("RVAL", 1, "IRB0"); + acpigen_set_package_element_namestr("RVAL", 2, "IRB1"); + acpigen_set_package_element_namestr("RVAL", 3, "IRB2"); + acpigen_set_package_element_namestr("RVAL", 4, "IRB3"); + acpigen_write_return_namestr("RVAL"); + acpigen_pop_len(); + + /* If (IERR == 1) { Return (ERROR) } */ + acpigen_write_if_lequal_namestr_int("IERR", 1); + acpigen_write_debug_string("IPCS ERROR"); + acpigen_write_debug_namestr("IERC"); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_ERROR); + acpigen_write_return_namestr("RVAL"); + acpigen_pop_len(); + + /* Sleep (1) */ + acpigen_write_sleep(1); + /* Decrement (Local1) */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_pop_len(); /* While */ + + /* Return (TIMEOUT) */ + acpigen_write_debug_string("IPCS TIMEOUT"); + acpigen_set_package_element_int("RVAL", 0, PMC_IPC_TIMEOUT); + acpigen_write_return_namestr("RVAL"); + + acpigen_pop_len(); /* Method */ +} + +void pmc_ipc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable) +{ + const uint32_t data[] = { + 1 << clock_pin, /* Clock pin to be modified */ + (enable ? 1 : 0) << clock_pin, /* Clock pin to set */ + 1 << pcie_rp, /* PCIe root port to be modified */ + (enable ? 1 : 0) << pcie_rp, /* PCIe root port to set */ + }; + const char *method = acpi_device_path_join(pcidev_path_on_root(PCH_DEVFN_PMC), "IPCS"); + + if (!method) { + printk(BIOS_ERR, "%s: Unable to find PMC device IPCS method\n", __func__); + return; + } + + /* + * The PMC IPC mailbox method takes 7 arguments: + * IPCS (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + */ + acpigen_emit_namestring(method); + acpigen_write_integer(PMC_IPC_CMD_ID_SET_PCIE_CLOCK); + acpigen_write_integer(0); + acpigen_write_integer(sizeof(data)); + acpigen_write_dword(data[0]); + acpigen_write_dword(data[1]); + acpigen_write_dword(data[2]); + acpigen_write_dword(data[3]); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/81935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4df90e33f6982d3eae2474db6d095a9dda7a624 Gerrit-Change-Number: 81935 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newchange

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