August 2019 - coreboot-gerrit - mail.coreboot.org

Change in ...coreboot[master]: drivers/apple: Add hybrid graphics driver
by Evgeny Zinoviev (Code Review) Sept. 2, 2026

Sept. 2, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32719 Change subject: drivers/apple: Add hybrid graphics driver ...................................................................... drivers/apple: Add hybrid graphics driver Hybrid graphics driver for Apple MacBook Pro. Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/drivers/apple/hybrid_graphics/Kconfig A src/drivers/apple/hybrid_graphics/Makefile.inc A src/drivers/apple/hybrid_graphics/chip.h A src/drivers/apple/hybrid_graphics/gmux.c A src/drivers/apple/hybrid_graphics/gmux.h A src/drivers/apple/hybrid_graphics/hybrid_graphics.c A src/drivers/apple/hybrid_graphics/hybrid_graphics.h A src/drivers/apple/hybrid_graphics/romstage.c 8 files changed, 417 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32719/1 diff --git a/src/drivers/apple/hybrid_graphics/Kconfig b/src/drivers/apple/hybrid_graphics/Kconfig new file mode 100644 index 0000000..252373f --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_APPLE_HYBRID_GRAPHICS + bool + default n diff --git a/src/drivers/apple/hybrid_graphics/Makefile.inc b/src/drivers/apple/hybrid_graphics/Makefile.inc new file mode 100644 index 0000000..ea45b45 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/Makefile.inc @@ -0,0 +1,15 @@ +# +# This file is part of the coreboot project. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c romstage.c +ramstage-$(CONFIG_DRIVERS_APPLE_HYBRID_GRAPHICS) += gmux.c hybrid_graphics.c diff --git a/src/drivers/apple/hybrid_graphics/chip.h b/src/drivers/apple/hybrid_graphics/chip.h new file mode 100644 index 0000000..39434f8 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _APPLE_HYBRID_GRAPHICS_CHIP_H_ +#define _APPLE_HYBRID_GRAPHICS_CHIP_H_ + +enum hybrid_graphics_req { + HYBRID_GRAPHICS_INTEGRATED = 0, + HYBRID_GRAPHICS_DISCRETE = 1 +}; + +#define HYBRID_GRAPHICS_DEFAULT_GPU HYBRID_GRAPHICS_INTEGRATED + +struct drivers_apple_hybrid_graphics_config { + unsigned int gmux_indexed; +}; + +#endif /* _APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/gmux.c b/src/drivers/apple/hybrid_graphics/gmux.c new file mode 100644 index 0000000..e1f763a --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.c @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com> + * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de> + * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <arch/io.h> +#include <device/device.h> +#include "gmux.h" +#include "chip.h" + +static int gmux_index_wait_ready(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && (gwr & 0x01)) { + inb(GMUX_IOSTART + GMUX_PORT_READ); + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + return !!i; +} + +static int gmux_index_wait_complete(void) +{ + int i = 200; + u8 gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + + while (i && !(gwr & 0x01)) { + gwr = inb(GMUX_IOSTART + GMUX_PORT_WRITE); + udelay(100); + i--; + } + + if (gwr & 0x01) + inb(GMUX_IOSTART + GMUX_PORT_READ); + + return !!i; +} + +u8 gmux_pio_read8(int port) +{ + return inb(GMUX_IOSTART + port); +} + +u8 gmux_index_read8(int port) +{ + u8 val; + + gmux_index_wait_ready(); + outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inb(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +void gmux_pio_write8(int port, u8 val) +{ + outb(val, GMUX_IOSTART + port); +} + + +void gmux_index_write8(int port, u8 val) +{ + outb(val, GMUX_IOSTART + GMUX_PORT_VALUE); + gmux_index_wait_ready(); + outb(port & 0xff, GMUX_IOSTART + GMUX_PORT_WRITE); + gmux_index_wait_complete(); +} + +u32 gmux_pio_read32(int port) +{ + return inl(GMUX_IOSTART + port); +} + +u32 gmux_index_read32(int port) +{ + u32 val; + + gmux_index_wait_ready(); + outb((port & 0xff), GMUX_IOSTART + GMUX_PORT_READ); + gmux_index_wait_complete(); + val = inl(GMUX_IOSTART + GMUX_PORT_VALUE); + + return val; +} + +u8 gmux_read8(const struct device *dev, int port) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + return gmux_index_read8(port); + } else { + return gmux_pio_read8(port); + } +} + +void gmux_write8(const struct device *dev, int port, u8 val) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + gmux_index_write8(port, val); + } else { + gmux_pio_write8(port, val); + } +} + +u32 gmux_read32(const struct device *dev, int port) +{ + const struct drivers_apple_hybrid_graphics_config *config = dev->chip_info; + if (config->gmux_indexed) { + return gmux_index_read32(port); + } else { + return gmux_pio_read32(port); + } +} + +void gmux_dgpu_power_enable(const struct device *dev, bool enable) +{ + if (enable) { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 3); + } else { + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 1); + gmux_write8(dev, GMUX_PORT_DISCRETE_POWER, 0); + } +} + +void gmux_switch(const struct device *dev, bool dgpu) +{ + if (dgpu) { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 2); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 3); + } else { + gmux_write8(dev, GMUX_PORT_SWITCH_DDC, 1); + gmux_write8(dev, GMUX_PORT_SWITCH_DISPLAY, 2); + } +} + + diff --git a/src/drivers/apple/hybrid_graphics/gmux.h b/src/drivers/apple/hybrid_graphics/gmux.h new file mode 100644 index 0000000..18f6722 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/gmux.h @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) Canonical Ltd. <seth.forshee(a)canonical.com> + * Copyright (C) 2010-2012 Andreas Heider <andreas(a)meetr.de> + * Copyright (C) 2015 Lukas Wunner <lukas(a)wunner.de> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EC_APPLE_GMUX_H +#define EC_APPLE_GMUX_H + +#define GMUX_PORT_VERSION_MAJOR 0x04 +#define GMUX_PORT_VERSION_MINOR 0x05 +#define GMUX_PORT_VERSION_RELEASE 0x06 + +#define GMUX_PORT_SWITCH_DISPLAY 0x10 +#define GMUX_PORT_SWITCH_DDC 0x28 +#define GMUX_PORT_DISCRETE_POWER 0x50 +#define GMUX_PORT_MAX_BRIGHTNESS 0x70 +#define GMUX_PORT_BRIGHTNESS 0x74 +#define GMUX_PORT_VALUE 0xc2 +#define GMUX_PORT_READ 0xd0 +#define GMUX_PORT_WRITE 0xd4 + +#define GMUX_PORT_INTERRUPT_ENABLE 0x14 +#define GMUX_INTERRUPT_ENABLE 0xff +#define GMUX_INTERRUPT_DISABLE 0x00 + +#define GMUX_BRIGHTNESS_MASK 0x00ffffff +#define GMUX_MAX_BRIGHTNESS GMUX_BRIGHTNESS_MASK + +#define GMUX_IOSTART 0x700 + +u8 gmux_index_read8(int port); +u8 gmux_pio_read8(int port); +u8 gmux_read8(const struct device *dev, int port); + +void gmux_index_write8(int port, u8 val); +void gmux_pio_write8(int port, u8 val); +void gmux_write8(const struct device *dev, int port, u8 val); + +u32 gmux_index_read32(int port); +u32 gmux_pio_read32(int port); +u32 gmux_read32(const struct device *dev, int port); + +void gmux_switch(const struct device *dev, bool dgpu); +void gmux_dgpu_power_enable(const struct device *dev, bool enable); + +#endif /* EC_APPLE_GMUX_H */ diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.c b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c new file mode 100644 index 0000000..804eb76 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> + +#include <southbridge/intel/common/gpio.h> +#include <console/console.h> +#include "chip.h" +#include "gmux.h" + +static void enable_dev(struct device *dev) +{ + printk(BIOS_INFO, "Hybrid graphics enable_dev\n"); + + const struct drivers_lenovo_hybrid_graphics_config *config; + enum hybrid_graphics_req mode; + u8 ver_major, ver_minor, ver_release; + u32 version, max_brightness, brightness; + + /* Don't confuse anyone else and disable the fake device */ + dev->enabled = 0; + + config = dev->chip_info; + if (!config) { + printk(BIOS_INFO, "Hybrid graphics: Not installed\n"); + return; + } + + version = gmux_index_read32(GMUX_PORT_VERSION_MAJOR); + ver_major = (version >> 24) & 0xff; + ver_minor = (version >> 16) & 0xff; + ver_release = (version >> 8) & 0xff; + max_brightness = gmux_index_read32(GMUX_PORT_MAX_BRIGHTNESS); + brightness = gmux_index_read32(GMUX_PORT_BRIGHTNESS) & GMUX_BRIGHTNESS_MASK; + + printk(BIOS_INFO, "gmux version: %d.%d.%d\n", + ver_major, ver_minor, ver_release); + printk(BIOS_INFO, "gmux max brightness: %d\n", max_brightness); + printk(BIOS_INFO, "gmux brightness: %d\n", brightness); + + mode = HYBRID_GRAPHICS_DEFAULT_GPU; + get_option(&mode, "hybrid_graphics_mode"); + + gmux_switch(dev, mode == HYBRID_GRAPHICS_DISCRETE); +} + +struct chip_operations drivers_apple_hybrid_graphics_ops = { + CHIP_NAME("Apple hybrid graphics driver") + .enable_dev = enable_dev +}; diff --git a/src/drivers/apple/hybrid_graphics/hybrid_graphics.h b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h new file mode 100644 index 0000000..782be44 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/hybrid_graphics.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ +#define _DRIVERS_APPLE_HYBRID_GRAPHICS_H_ + +#define HYBRID_GRAPHICS_PORT 0xff +#define HYBRID_GRAPHICS_DEVICE 0xf + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg); + +#endif /* _DRIVERS_APPLE_HYBRID_GRAPHICS_CHIP_H_ */ diff --git a/src/drivers/apple/hybrid_graphics/romstage.c b/src/drivers/apple/hybrid_graphics/romstage.c new file mode 100644 index 0000000..9cd5098 --- /dev/null +++ b/src/drivers/apple/hybrid_graphics/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <option.h> +#include <device/device.h> +#include <console/console.h> +#include "hybrid_graphics.h" +#include "chip.h" +#include "gmux.h" + +void early_hybrid_graphics(bool *enable_igd, bool *enable_peg) +{ + const struct drivers_apple_hybrid_graphics_config *config; + const struct device *dev; + + enum hybrid_graphics_req mode = HYBRID_GRAPHICS_DEFAULT_GPU; + + printk(BIOS_INFO, "Hybrid graphics early_hybrid_graphics\n"); + + /* TODO: Use generic device instead of dummy PNP device */ + dev = dev_find_slot_pnp(HYBRID_GRAPHICS_PORT, HYBRID_GRAPHICS_DEVICE); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "Hybrid graphics: ERROR\n"); + *enable_igd = true; + *enable_peg = false; + return; + } + + config = dev->chip_info; + + get_option(&mode, "hybrid_graphics_mode"); + + if (mode == HYBRID_GRAPHICS_DISCRETE) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling integrated GPU.\n"); + + *enable_igd = false; + *enable_peg = true; + } else if (mode == HYBRID_GRAPHICS_INTEGRATED) { + printk(BIOS_DEBUG, "Hybrid graphics:" + " Disabling discrete GPU.\n"); + + *enable_igd = true; + *enable_peg = false; + } + + gmux_dgpu_power_enable(dev, *enable_peg); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32719 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22b66622cd2da0e9951ee726d650d204fbb8a5bc Gerrit-Change-Number: 32719 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

9 34

Change in ...coreboot[master]: mb/apple: Add MacBook Pro 10,1 (A1398) support
by Evgeny Zinoviev (Code Review) Sept. 1, 2026

Sept. 1, 2026

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32673 Change subject: mb/apple: Add MacBook Pro 10,1 (A1398) support ...................................................................... mb/apple: Add MacBook Pro 10,1 (A1398) support MacBook Pro Retina 15 (Mid 2012) with Ivy Bridge CPU. This is WIP. Not for merging. Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- M 3rdparty/vboot A src/mainboard/apple/macbookpro10_1/Kconfig A src/mainboard/apple/macbookpro10_1/Kconfig.name A src/mainboard/apple/macbookpro10_1/Makefile.inc A src/mainboard/apple/macbookpro10_1/acpi/ec.asl A src/mainboard/apple/macbookpro10_1/acpi/platform.asl A src/mainboard/apple/macbookpro10_1/acpi/superio.asl A src/mainboard/apple/macbookpro10_1/acpi_tables.c A src/mainboard/apple/macbookpro10_1/board_info.txt A src/mainboard/apple/macbookpro10_1/devicetree.cb A src/mainboard/apple/macbookpro10_1/dsdt.asl A src/mainboard/apple/macbookpro10_1/gma-mainboard.ads A src/mainboard/apple/macbookpro10_1/gpio.c A src/mainboard/apple/macbookpro10_1/hda_verb.c A src/mainboard/apple/macbookpro10_1/mainboard.c A src/mainboard/apple/macbookpro10_1/romstage.c 16 files changed, 758 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32673/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..304aa42 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit 304aa429c1a04cda3ab2ce37b9e31af84405bfca diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig b/src/mainboard/apple/macbookpro10_1/Kconfig new file mode 100644 index 0000000..603f3ee --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig @@ -0,0 +1,46 @@ +if BOARD_APPLE_MACBOOKPRO10_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_EDP + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default apple/macbookpro10_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro10,1" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/apple/macbookpro10_1/Kconfig.name b/src/mainboard/apple/macbookpro10_1/Kconfig.name new file mode 100644 index 0000000..c257f7a --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO10_1 + bool "MacBookPro10,1" diff --git a/src/mainboard/apple/macbookpro10_1/Makefile.inc b/src/mainboard/apple/macbookpro10_1/Makefile.inc new file mode 100644 index 0000000..fd60338 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/Makefile.inc @@ -0,0 +1,7 @@ +romstage-y += gpio.c + +cbfs-files-y += spd.bin +spd.bin-file := spd.bin +spd.bin-type := spd + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro10_1/acpi/ec.asl b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl new file mode 100644 index 0000000..f70cb3d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/ec.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/platform.asl b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl new file mode 100644 index 0000000..a17c6ea --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/apple/macbookpro10_1/acpi/superio.asl b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro10_1/acpi_tables.c b/src/mainboard/apple/macbookpro10_1/acpi_tables.c new file mode 100644 index 0000000..c48f0bd --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/acpi_tables.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro10_1/board_info.txt b/src/mainboard/apple/macbookpro10_1/board_info.txt new file mode 100644 index 0000000..81a5134 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2012 diff --git a/src/mainboard/apple/macbookpro10_1/devicetree.cb b/src/mainboard/apple/macbookpro10_1/devicetree.cb new file mode 100644 index 0000000..f9e7eb4 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/devicetree.cb @@ -0,0 +1,124 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + #register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.did" = "{ 0x80000410, 0x80000320, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0xffffffff" + register "gpu_dp_b_hotplug" = "7" + register "gpu_dp_c_hotplug" = "7" + register "gpu_dp_d_hotplug" = "7" + register "gpu_panel_port_select" = "3" + register "gpu_panel_power_backlight_off_delay" = "8191" + register "gpu_panel_power_backlight_on_delay" = "8191" + register "gpu_panel_power_cycle_delay" = "255" + register "gpu_panel_power_down_delay" = "8191" + register "gpu_panel_power_up_delay" = "8191" + register "gpu_pch_backlight" = "0xffffffff" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x8086 0x7270 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00f7 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00f7 + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00f7 + end + device pci 01.2 on + subsystemid 0x106b 0x00f7 + end + device pci 01.1 on + subsystemid 0x106b 0x00f7 + end + end +end diff --git a/src/mainboard/apple/macbookpro10_1/dsdt.asl b/src/mainboard/apple/macbookpro10_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads new file mode 100644 index 0000000..d4a5d7d --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gma-mainboard.ads @@ -0,0 +1,34 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/apple/macbookpro10_1/gpio.c b/src/mainboard/apple/macbookpro10_1/gpio.c new file mode 100644 index 0000000..a445687 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/gpio.c @@ -0,0 +1,243 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_OUTPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_LOW, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_LOW, + .gpio19 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio11 = GPIO_RESET_RSMRST, + .gpio15 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio36 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_LOW, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_GPIO, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_LOW, + .gpio65 = GPIO_LEVEL_LOW, + .gpio66 = GPIO_LEVEL_LOW, + .gpio67 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro10_1/hda_verb.c b/src/mainboard/apple/macbookpro10_1/hda_verb.c new file mode 100644 index 0000000..b8e4855 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/hda_verb.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b2800, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b2800), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x002b4020), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100112), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100110), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x400000f0), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x90a60100), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be030), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro10_1/mainboard.c b/src/mainboard/apple/macbookpro10_1/mainboard.c new file mode 100644 index 0000000..3910541 --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro10_1/romstage.c b/src/mainboard/apple/macbookpro10_1/romstage.c new file mode 100644 index 0000000..c35604b --- /dev/null +++ b/src/mainboard/apple/macbookpro10_1/romstage.c @@ -0,0 +1,82 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <cbfs.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCH_LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(PCH_LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(PCH_LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(PCH_LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(PCH_LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(PCH_LPC_DEV, 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +// FIXME +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + void *spd_file; + size_t spd_file_len = 0; + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (spd_file && spd_file_len >= 128) { + memcpy(&spd[0], spd_file, 128); + memcpy(&spd[2], spd_file, 128); + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica03aba442493c0d369a3d360ad569ddc16954df Gerrit-Change-Number: 32673 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

12 81

Change in ...coreboot[master]: Documentation: Update CBFS
by Patrick Rudolph (Code Review) Aug. 6, 2026

Aug. 6, 2026

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33664 Change subject: Documentation: Update CBFS ...................................................................... Documentation: Update CBFS Update some parts to match current implementation. Change-Id: I84d07ae1c5c1ded2b9ab5934e2babbbabb749440 --- M Documentation/lib/cbfs.md M Documentation/lib/payloads/selfboot.md 2 files changed, 46 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/33664/1 diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md index 83d8b44..ce87b78 100644 --- a/Documentation/lib/cbfs.md +++ b/Documentation/lib/cbfs.md @@ -7,7 +7,7 @@ ## Introduction -This document describes the coreboot CBFS specification (from here +This document describes the coreboot filesystem specification (from here referred to as CBFS). CBFS is a scheme for managing independent chunks of data in a system ROM. Though not a true filesystem, the style and concepts are similar. @@ -15,7 +15,7 @@ ## Architecture -The CBFS architecture looks like the following: +The CBFS on x86 architecture looks like the following: ``` /---------------\ <-- Start of ROM @@ -49,11 +49,11 @@ The CBFS architecture consists of a binary associated with a physical ROM disk referred hereafter as the ROM. A number of independent of -components, each with a header prepended on to data are located within -the ROM. The components are nominally arranged sequentially, though they +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they are aligned along a pre-defined boundary. -The bootblock occupies the last 20k of the ROM. Within +On x86 legacy the bootblock occupies the last 20k of the ROM. Within the bootblock is a master header containing information about the ROM including the size, alignment of the components, and the offset of the start of the first CBFS component within the ROM. @@ -62,14 +62,13 @@ The master header contains essential information about the ROM that is used by both the CBFS implementation within coreboot at runtime as well -as host based utilities to create and manage the ROM. The master header -will be located somewhere within the bootblock (last 20k of the ROM). A -pointer to the location of the header will be located at offset --4 from the end of the ROM. This translates to address 0xFFFFFFFC on a -normal x86 system. The pointer will be to physical memory somewhere -between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot -to locate the header at run time. Build time utilities will -need to read the pointer and do the appropriate math to locate the header. +as host based utilities to create and manage the ROM. The master header +will be located at the start of CBFS. A pointer to the location of the +header will be located at offset -4 from the end of the ROM. +This translates to address 0xFFFFFFFC on a normal x86 system. +This makes it easier for coreboot to locate the header at run time. +Build time utilities will need to read the pointer and do the appropriate +math to locate the header. The following is the structure of the master header: @@ -114,16 +113,16 @@ for. ## Bootblock -The bootblock is a mandatory component in the ROM. It is located in the -last 20k of the ROM space, and contains, among other things, the location of the -master header and the entry point for the loader firmware. The bootblock -does not have a component header attached to it. +The bootblock is a mandatory component in the ROM. On x86 legacy it is located +at the end of the CBFS, and contains, among other things, the location of the +master header and the entry point for the loader firmware. On other +architectures the bootblock might not be part of the CBFS. ## Components CBFS components are placed in the ROM starting at 'offset' specified in -the master header and ending at the bootblock. Thus the total size -available for components in the ROM is (ROM size - 20k - 'offset'). +the master header and ending at the end of the CBFS. Thus the total size +available for components in the ROM is (ROM size - 'offset'). Each CBFS component is to be aligned according to the 'align' value in the header. Thus, if a component of size 1052 is located at offset 0 with an 'align' @@ -208,10 +207,10 @@ #### Stages -Stages are code loaded by coreboot during the boot process. They are -essential to a successful boot. Stages are comprised of a single blob +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob of binary data that is to be loaded into a particular location in memory -and executed. The uncompressed header contains information about how +and executed. The uncompressed header contains information about how large the data is, and where it should be placed, and what additional memory needs to be cleared. @@ -244,8 +243,8 @@ `compression` is an integer defining how the data is compressed. There are three compression types defined by this version of the standard: -none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional -types may be added assuming that coreboot understands how to handle the scheme. +none (0x0), lzma (0x1), and lz4 (0x02), though additional types may be +added assuming that coreboot understands how to handle the scheme. `entry` is a 64 bit value indicating the location where the program counter should jump following the loading of the stage. This should be @@ -271,13 +270,13 @@ #### Payloads Payloads are loaded by coreboot following the boot process. +The default payloads supported by coreboot are [SELF] payloads. -Stages are assigned a component value of 0x20. When coreboot sees this +[SELF] stages are assigned a component value of 0x20. When coreboot sees this component type, it knows that it should pass the data to a sub-function -that will process the payload. Furthermore, other run time applications such -as 'bayou' may easily index all available payloads -on the system by searching for the payload type. - +that will process the payload. Furthermore, other run time applications such +as 'bayou' may easily index all available payloads on the system by searching +for the payload type. The following is the format of a stage component: @@ -338,9 +337,9 @@ `compression` is the compression scheme for the segment. Each segment can be independently compressed. There are three compression types defined by -this version of the standard: none (0x0), lzma (0x1), and nrv2b -(0x02, deprecated), though additional types may be added assuming that -coreboot understands how to handle the scheme. +this version of the standard: none (0x0), lzma (0x1), and lz4 (0x02), though +additional types may be added assuming that coreboot understands how to handle +the scheme. `offset` is the address of the data within the component, starting from the component header. @@ -355,6 +354,13 @@ The data will located immediately following the last segment. +#### FIT payload + +A payload of type [FIT] is supported on some architectures. + +[FIT] stages are assigned a component value of 0x21 and do not support +compressions at all. + #### Option ROMS The third specified component type will be Option ROMs. Option ROMS will @@ -364,8 +370,11 @@ #### NULL -There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is -the "don't care" component type. This can be used when the component +There is a 4th component type, defined as NULL (0xFFFFFFFF, 0x00000000). +This is the "don't care" component type. This can be used when the component type is not necessary (such as when the name of the component is unique. i.e. option_table). It is recommended that all components be assigned a unique type, but NULL can be used when the type does not matter. + +[FIT]: payloads/fit.md +[SELF]: payloads/selfboot.md diff --git a/Documentation/lib/payloads/selfboot.md b/Documentation/lib/payloads/selfboot.md index 62a4393..791d6c0 100644 --- a/Documentation/lib/payloads/selfboot.md +++ b/Documentation/lib/payloads/selfboot.md @@ -18,6 +18,8 @@ address they specify. If it's not possible to load the payload at the specified address, the system won't boot. +Implementations details can be found in the [CBFS] documentation. + ### Calling conventions The SELF payload is called with a pointer to the coreboot tables as first argument. @@ -26,3 +28,4 @@ and a pointer to the *FDT* as arguments. [RISC-V]: ../../arch/riscv/index.md +[CBFS]: ../cbfs.md -- To view, visit https://review.coreboot.org/c/coreboot/+/33664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84d07ae1c5c1ded2b9ab5934e2babbbabb749440 Gerrit-Change-Number: 33664 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: Documentation: Convert cbfs.txt to markdown
by Patrick Rudolph (Code Review) Aug. 6, 2026

Aug. 6, 2026

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33663 Change subject: Documentation: Convert cbfs.txt to markdown ...................................................................... Documentation: Convert cbfs.txt to markdown Convert the document to markdown. Needs to be fixed in a separate commit as it doesn't reflect coreboot v4. Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/lib/cbfs.md M Documentation/lib/index.md 2 files changed, 372 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33663/1 diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md new file mode 100644 index 0000000..83d8b44 --- /dev/null +++ b/Documentation/lib/cbfs.md @@ -0,0 +1,371 @@ +# coreboot CBFS Specification +by Jordan Crouse <jordan(a)cosmicpenguin.net> + +**WARNING: This documentation is written against coreboot v1.** + +**TODO: Update this document ASAP** + +## Introduction + +This document describes the coreboot CBFS specification (from here +referred to as CBFS). CBFS is a scheme for managing independent chunks +of data in a system ROM. Though not a true filesystem, the style and +concepts are similar. + + +## Architecture + +The CBFS architecture looks like the following: + +``` +/---------------\ <-- Start of ROM +| /-----------\ | --| +| | Header | | | +| |-----------| | | +| | Name | | |-- Component +| |-----------| | | +| |Data | | | +| |.. | | | +| \-----------/ | --| +| | +| /-----------\ | +| | Header | | +| |-----------| | +| | Name | | +| |-----------| | +| |Data | | +| |.. | | +| \-----------/ | +| | +| ... | +| /-----------\ | +| | | | +| | Bootblock | | +| | --------- | | +| | Reset | | <- 0xFFFFFFF0 +| \-----------/ | +\---------------/ +``` + +The CBFS architecture consists of a binary associated with a physical +ROM disk referred hereafter as the ROM. A number of independent of +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they +are aligned along a pre-defined boundary. + +The bootblock occupies the last 20k of the ROM. Within +the bootblock is a master header containing information about the ROM +including the size, alignment of the components, and the offset of the +start of the first CBFS component within the ROM. + +## Master Header + +The master header contains essential information about the ROM that is +used by both the CBFS implementation within coreboot at runtime as well +as host based utilities to create and manage the ROM. The master header +will be located somewhere within the bootblock (last 20k of the ROM). A +pointer to the location of the header will be located at offset +-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a +normal x86 system. The pointer will be to physical memory somewhere +between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot +to locate the header at run time. Build time utilities will +need to read the pointer and do the appropriate math to locate the header. + +The following is the structure of the master header: + +```c +struct cbfs_header { + u32 magic; + u32 version; + u32 romsize; + u32 bootblocksize; + u32 align; + u32 offset; + u32 architecture; + u32 pad[1]; +} __packed; +``` + +The meaning of each member is as follows: + +`magic` is a 32 bit number that identifies the ROM as a CBFS type. The +magic +number is 0x4F524243, which is 'ORBC' in ASCII. + +`version` is a version number for CBFS header. cbfs_header structure may be +different if version is not matched. + +`romsize` is the size of the ROM in bytes. coreboot will subtract 'size' from +0xFFFFFFFF to locate the beginning of the ROM in memory. + +`bootblocksize` is the size of bootblock reserved in firmware image. + +`align` is the number of bytes that each component is aligned to within the +ROM. This is used to make sure that each component is aligned correctly +with +regards to the erase block sizes on the ROM - allowing one to replace a +component at runtime without disturbing the others. + +`offset` is the offset of the first CBFS component (from the start of +the ROM). This is to allow for arbitrary space to be left at the beginning +of the ROM for things like embedded controller firmware. + +`architecture` describes which architecture (x86, arm, ...) this CBFS is created +for. + +## Bootblock +The bootblock is a mandatory component in the ROM. It is located in the +last 20k of the ROM space, and contains, among other things, the location of the +master header and the entry point for the loader firmware. The bootblock +does not have a component header attached to it. + +## Components + +CBFS components are placed in the ROM starting at 'offset' specified in +the master header and ending at the bootblock. Thus the total size +available for components in the ROM is (ROM size - 20k - 'offset'). +Each CBFS component is to be aligned according to the 'align' value in the +header. +Thus, if a component of size 1052 is located at offset 0 with an 'align' +value of 1024, the next component will be located at offset 2048. + +Each CBFS component will be indexed with a unique ASCII string name of +unlimited size. + +Each CBFS component starts with a header: + +```c +struct cbfs_file { + char magic[8]; + unsigned int len; + unsigned int type; + unsigned int checksum; + unsigned int offset; +}; +``` + +`magic` is a magic value used to identify the header. During runtime, +coreboot will scan the ROM looking for this value. The default magic is +the string 'LARCHIVE'. + +`len` is the length of the data, not including the size of the header and +the size of the name. + +`type` is a 32 bit number indicating the type of data that is attached. +The data type is used in a number of ways, as detailed in the section +below. + +`checksum` is a 32bit checksum of the entire component, including the +header and name. + +`offset` is the start of the component data, based off the start of the +header. +The difference between the size of the header and offset is the size of the +component name. + +Immediately following the header will be the name of the component, +which will null terminated and 16 byte aligned. The following picture shows the +structure of the header: + +``` +/--------\ <- start +| Header | +|--------| <- sizeof(struct cbfs_file) +| Name | +|--------| <- 'offset' +| Data | +| ... | +\--------/ <- start + 'offset' + 'len' +``` + +### Searching Algorithm + +To locate a specific component in the ROM, one starts at the 'offset' +specified in the CBFS master header. For this example, the offset will +be 0. + +From that offset, the code should search for the magic string on the +component, jumping 'align' bytes each time. So, assuming that 'align' is +16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. +If the offset ever exceeds the allowable range for CBFS components, then no +component was found. + +Upon recognizing a component, the software then has to search for the +specific name of the component. This is accomplished by comparing the +desired name with the string on the component located at +`offset + sizeof(struct cbfs_file)`. If the string matches, then the +component has been located, otherwise the software should add +`'offset' + 'len'` to the offset and resume the search for the magic value. + +### Data Types + +The 'type' member of struct cbfs_file is used to identify the content +of the component data, and is used by coreboot and other +run-time entities to make decisions about how to handle the data. + +There are three component types that are essential to coreboot, and so +are defined here. + +#### Stages + +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob +of binary data that is to be loaded into a particular location in memory +and executed. The uncompressed header contains information about how +large the data is, and where it should be placed, and what additional memory +needs to be cleared. + +Stages are assigned a component value of 0x10. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the stage. + +The following is the format of a stage component: + +``` +/--------\ +| Header | +|--------| +| Binary | +| .. | +\--------/ +``` + +The header is defined as: + +```c +struct cbfs_stage { + unsigned int compression; + unsigned long long entry; + unsigned long long load; + unsigned int len; + unsigned int memlen; +}; +``` + +`compression` is an integer defining how the data is compressed. There +are three compression types defined by this version of the standard: +none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional +types may be added assuming that coreboot understands how to handle the scheme. + +`entry` is a 64 bit value indicating the location where the program +counter should jump following the loading of the stage. This should be +an absolute physical memory address. + +`load` is a 64 bit value indicating where the subsequent data should be +loaded. This should be an absolute physical memory address. + +`len` is the length of the compressed data in the component. + +`memlen` is the amount of memory that will be used by the component when +it is loaded. + +The component data will start immediately following the header. + +When coreboot loads a stage, it will first zero the memory from 'load' to +'memlen'. It will then decompress the component data according to the +specified scheme and place it in memory starting at 'load'. Following that, +it will jump execution to the address specified by 'entry'. +Some components are designed to execute directly from the ROM - coreboot +knows which components must do that and will act accordingly. + +#### Payloads + +Payloads are loaded by coreboot following the boot process. + +Stages are assigned a component value of 0x20. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the payload. Furthermore, other run time applications such +as 'bayou' may easily index all available payloads +on the system by searching for the payload type. + + +The following is the format of a stage component: + +``` +/-----------\ +| Header | +| Segment 1 | +| Segment 2 | +| ... | +|-----------| +| Binary | +| .. | +\-----------/ +``` + +The header is as follows: + +```c +struct cbfs_payload { + struct cbfs_payload_segment segments; +} +``` + +The header contains a number of segments corresponding to the segments +that need to be loaded for the payload. + +The following is the structure of each segment header: + +```c +struct cbfs_payload_segment { + unsigned int type; + unsigned int compression; + unsigned int offset; + unsigned long long load_addr; + unsigned int len; + unsigned int mem_len; +}; +``` + +`type` is the type of segment, one of the following: + +```eval_rst ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_CODE | 0x45444F43 | The segment contains executable code | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_DATA | 0x41544144 | The segment contains data | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_BSS | 0x20535342 | The memory specified by the segment | +| | | should be zeroed | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_PARAMS| 0x41524150 | The segment contains information for | +| | | the payload | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_ENTRY | 0x52544E45 | The segment contains the entry point | +| | | for the payload | ++----------------------+-------------+---------------------------------------+ +``` + +`compression` is the compression scheme for the segment. Each segment can +be independently compressed. There are three compression types defined by +this version of the standard: none (0x0), lzma (0x1), and nrv2b +(0x02, deprecated), though additional types may be added assuming that +coreboot understands how to handle the scheme. + +`offset` is the address of the data within the component, starting from +the component header. + +`load_addr` is a 64 bit value indicating where the segment should be placed +in memory. + +`len` is a 32 bit value indicating the size of the segment within the +component. + +`mem_len` is the size of the data when it is placed into memory. + +The data will located immediately following the last segment. + +#### Option ROMS + +The third specified component type will be Option ROMs. Option ROMS will +have component type '0x30'. They will have no additional header, the +uncompressed binary data will be located in the data portion of the +component. + +#### NULL + +There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is +the "don't care" component type. This can be used when the component +type is not necessary (such as when the name of the component is unique. +i.e. option_table). It is recommended that all components be assigned a +unique type, but NULL can be used when the type does not matter. diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index 99b8061..808bac8 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -6,4 +6,5 @@ ## Structure and layout - [Flashmap and Flashmap Descriptor](flashmap.md) - [ABI data consumption](abi-data-consumption.md) +- [CBFS](cbfs.md) - [Timestamps](timestamp.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/33663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Gerrit-Change-Number: 33663 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: Documentation: Explain SimpleELF
by Patrick Rudolph (Code Review) Aug. 6, 2026

Aug. 6, 2026

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33447 Change subject: Documentation: Explain SimpleELF ...................................................................... Documentation: Explain SimpleELF Explain coreboot's SELF format. Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/lib/payloads/index.md A Documentation/lib/payloads/selfboot.md M Documentation/payloads.md 3 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/33447/1 diff --git a/Documentation/lib/payloads/index.md b/Documentation/lib/payloads/index.md index 44daef1..b8eca8c 100644 --- a/Documentation/lib/payloads/index.md +++ b/Documentation/lib/payloads/index.md @@ -6,6 +6,10 @@ coreboot supports multiple payloads, depending on the architecture of the selected mainboard. +## SimpleELF + +- [SimpleELF format](selfboot.md) + ## FIT - [uImage.FIT support](fit.md) diff --git a/Documentation/lib/payloads/selfboot.md b/Documentation/lib/payloads/selfboot.md new file mode 100644 index 0000000..62a4393 --- /dev/null +++ b/Documentation/lib/payloads/selfboot.md @@ -0,0 +1,28 @@ +# Simple ELF standard + +coreboot is able to use static linked ELF binaries as payload. +To reduce complexity the ELF binaries are converted to coreboot's SimpleELF +(SELF) format. +The payload is therefore split into multiple sections by `cbfstool` at +build time, each having a unique loading address and possible compression. + +## SELF loader +The SELF loader implementation can be found in `src/lib/selfboot.c`. +It decompresses the SELF sections and places them in memory. + +If the payload overlaps with the loading stage (*RAMSTAGE*) and +`CONFIG_RELOCATABLE_RAMSTAGE` is selected, the loading stage is moved to another +location in RAM. + +SELF payloads are **never** relocatable and will always be placed at the +address they specify. If it's not possible to load the payload at the specified +address, the system won't boot. + +### Calling conventions +The SELF payload is called with a pointer to the coreboot tables as first +argument. + +**Note:** The only exception is made on [RISC-V] which does use the *HARTID* +and a pointer to the *FDT* as arguments. + +[RISC-V]: ../../arch/riscv/index.md diff --git a/Documentation/payloads.md b/Documentation/payloads.md index b1eae61..650818e 100644 --- a/Documentation/payloads.md +++ b/Documentation/payloads.md @@ -7,6 +7,12 @@ There is various software in that space that is either explicitly written as payload or can be made to work as one. +## ELF + +Executable and linking format (ELF) compatible static linked binaries can be +loaded as payload. +ELF binaries are loaded through the [SELF] boot mechanism. + ## SeaBIOS [SeaBIOS](https://www.seabios.org) is an open source implementation of @@ -14,6 +20,7 @@ since. While originally written for emulators such as QEMU, it can be made to work as a coreboot payload and all the necessary code is in SeaBIOS' mainline code. +SeaBIOS is loaded through the [SELF] boot mechanism. ## Tianocore @@ -40,3 +47,8 @@ firmware project drivers that often reinvent the wheel) and the ability to define boot policy with familiar tools, no matter if those are shell scripts or compiled userland programs written in C, Go or other programming languages. + +On x86 platforms Linux is loaded through the [SELF] boot mechanism, by adding a +*tampoline code* at the start of the kernel. + +[SELF]: lib/payloads/selfboot.md -- To view, visit https://review.coreboot.org/c/coreboot/+/33447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia217af7d39505393ed9324fbe53b4ca7f3069e2e Gerrit-Change-Number: 33447 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 13

Change in ...coreboot[master]: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies
by mikeb mikeb (Code Review) June 12, 2025

June 12, 2025

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32351 to review the following change. Change subject: SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies ...................................................................... SeaBIOS - unofficial patches: advanced_bootmenu and multiple_floppies If you'd like to add the useful floppies to your coreboot (read about them at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking#Useful_floppies ), or to use your USB numpad for choosing a SeaBIOS boot entry, then this change is for you! It contains two valuable patches together with a Makefile mod needed to automatically apply these patches to a cloned SeaBIOS before its' compilation. advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) https://mail.coreboot.org/hyperkitty/list/seabios@seabios.org/thread/CKWLNT… [PATCH v2] ramdisk: search for all available floppy images instead of one https://mail.coreboot.org/pipermail/seabios/2018-December/012670.html Patch descriptions are available at these links, and just in case here's a copy: advanced_bootmenu: up to 35 entries (2 pages if >18), numpad support (console) Add support for up to 35 boot menu entries (2 pages if >18). To solve the ">10" problem currently experienced by SeaBIOS users (there are no 11, 12, etc. keys on a keyboard - so impossible to choose the last menu entries if you got >10 entries because of multiple hard drives / secondary payloads / floppies) - the boot menu has been extended to the letter keys. NOTE: TPM menu has been moved from T to M letter: it is at the end of keyboard's 3rd row of letters and "Trusted" is adjective while "Module" is a noun; alternatively could press '-'. Also, add support for a numpad. Small USB numpad could be really convenient for choosing the boot entries at coreboot boards used as (maybe headless) servers. '/' char on numpad could be used to open the boot menu or to exit it. If there are >10 boot menu entries - the numpad console interface will be enabled: press one or two digit keys and then ENTER to confirm your choice, or remove a digit by pressing the '.Del' key. Also you could call TPM with '-' key at any moment, or boot with a single key press of your fullsize keyboard. [PATCH v2] ramdisk: search for all available floppy images instead of one All the floppy images available at CBFS will be found and listed in a boot menu, instead of the first found. Could be highly valuable if you are participating in a hobby OS development - would like to test multiple versions of your floppy at the same coreboot image, to reduce the amount of re-flashes and accelerate the development at bare metal - or simply you would like to access multiple floppies as a coreboot user. For example: KolibriOS (nice assembly OS with GUI and apps), FreeDOS, MichalOS, Snowdrop and memtest (coreboot's memtest version is buggy, e.g. external USB keyboard isn't working at some laptops; floppy is much better) Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d --- M payloads/external/SeaBIOS/Makefile A payloads/external/SeaBIOS/advanced_bootmenu.patch A payloads/external/SeaBIOS/multiple_floppies.patch 3 files changed, 551 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32351/1 diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index e505c8c..ae58c8c 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -76,7 +76,18 @@ # echo "# CONFIG_SMBIOS is not set" >> seabios/.config $(MAKE) -C seabios olddefconfig OUT=out/ -build: config +patch: + if [ -d seabios ]; then \ + cd seabios; \ + if [ ! -f .patched ]; then \ + echo " PATCH SeaBIOS $(TAG-y)"; \ + patch -p1 < ./../advanced_bootmenu.patch; \ + patch -p1 < ./../multiple_floppies.patch; \ + touch .patched; \ + fi; \ + fi + +build: config patch echo " MAKE SeaBIOS $(TAG-y)" $(MAKE) -C seabios OUT=out/ diff --git a/payloads/external/SeaBIOS/advanced_bootmenu.patch b/payloads/external/SeaBIOS/advanced_bootmenu.patch new file mode 100644 index 0000000..c914588 --- /dev/null +++ b/payloads/external/SeaBIOS/advanced_bootmenu.patch @@ -0,0 +1,332 @@ +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..f94dd27 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -463,6 +463,7 @@ get_keystroke(int msec) + * Boot menu and BCV execution + ****************************************************************/ + ++#define BOOTMENU_PAGE_SIZE 18 + #define DEFAULT_BOOTMENU_WAIT 2500 + + // Show IPL option menu. +@@ -478,59 +479,282 @@ interactive_bootmenu(void) + ; + + char *bootmsg = romfile_loadfile("etc/boot-menu-message", NULL); +- int menukey = romfile_loadint("etc/boot-menu-key", 1); +- printf("%s", bootmsg ?: "\nPress ESC for boot menu.\n\n"); ++ int menukey = romfile_loadint("etc/boot-menu-key", 1); // custom menukey ++ printf("%s", bootmsg ?: "\nPress ESC or \\ / slash for boot menu.\n\n"); + free(bootmsg); + + u32 menutime = romfile_loadint("etc/boot-menu-wait", DEFAULT_BOOTMENU_WAIT); + enable_bootsplash(); + int scan_code = get_keystroke(menutime); + disable_bootsplash(); +- if (scan_code != menukey) ++ if (scan_code != menukey && // custom menukey ++ scan_code != 1 && // ESC ++ scan_code != 43 && // '\' char on keyboard ++ scan_code != 53 && // '/' char on keyboard ++ scan_code != 98) { // '/' char on numpad ++ if (scan_code == -1) ++ printf("No key pressed.\n"); ++ else ++ printf("Not a menukey pressed.\n"); + return; ++ } + + while (get_keystroke(0) >= 0) + ; + +- printf("Select boot device:\n\n"); + wait_threads(); + +- // Show menu items ++ char keyboard_keys[35] = {'1','2','3','4','5','6','7','8','9','0', ++ 'q','w','e','r','t','y','u','i','o','p', ++ 'a','s','d','f','g','h','j','k','l', ++ 'z','x','c','v','b','n'}; /* m = TPM */ ++ int numpad_scancodes[10] = { 82, 79, 80, 81, 75, 76, 77, 71, 72, 73 }; ++ int numpi = 0; // Key index: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. ++ int digits = 0; // Numerical length of a current choice number. ++ int decode = 0; // Decode the current choice number into a letter? ++ int entry_id = 0; ++ char desc[77]; ++ ++ printf("Select boot device"); ++ ++ // Show menu items after counting them and determining a number of pages. ++ // Only 35 boot menu items (36 if to count a TPM) are supported currently. ++ + int maxmenu = 0; + struct bootentry_s *pos; +- hlist_for_each_entry(pos, &BootList, node) { +- char desc[77]; ++ hlist_for_each_entry(pos, &BootList, node) + maxmenu++; +- printf("%d. %s\n", maxmenu ++ ++ if (maxmenu > 10) { ++ if (maxmenu > 35) ++ maxmenu = 35; ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - page 1 :"); ++ else ++ printf(": "); ++ printf(" // press ENTER after your numpad input"); ++ if (maxmenu > BOOTMENU_PAGE_SIZE) ++ printf(" - if any -\n " ++ " // - or to switch between the pages...\n"); ++ else ++ printf(" (if any)\n\n"); ++ } else { ++ printf(":\n\n"); ++ } ++ ++ hlist_for_each_entry(pos, &BootList, node) { ++ if (entry_id == BOOTMENU_PAGE_SIZE) // Show only the first page. ++ break; ++ printf("%c. %s\n", keyboard_keys[entry_id] + , strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; + } ++ int tpm_cshm = 0; + if (tpm_can_show_menu()) { +- printf("\nt. TPM Configuration\n"); ++ tpm_cshm = 1; ++ printf("\nm-. TPM Configuration"); + } +- +- // Get key press. If the menu key is ESC, do not restart boot unless +- // 1.5 seconds have passed. Otherwise users (trained by years of +- // repeatedly hitting keys to enter the BIOS) will end up hitting ESC +- // multiple times and immediately booting the primary boot device. +- int esc_accepted_time = irqtimer_calc(menukey == 1 ? 1500 : 0); ++ printf("\n> "); ++ ++ // Do not restart boot on menukey press, unless DEFAULT_BOOTMENU_WAIT msecs ++ // have passed. Otherwise users (trained by years of repeatedly hitting keys ++ // to enter the BIOS) will end up hitting menukey multiple times and ++ // immediately booting the primary boot device. ++ int esc_accepted_time = irqtimer_calc(DEFAULT_BOOTMENU_WAIT); ++ int choice = 0, kb_choice = 0; ++ int page_num = 1; ++ int enter = 0; ++ int backspace = 0; ++ int tpm_show_menu = 0; + for (;;) { + scan_code = get_keystroke(1000); +- if (scan_code == 1 && !irqtimer_check(esc_accepted_time)) +- continue; +- if (tpm_can_show_menu() && scan_code == 20 /* t */) { ++ if (scan_code == menukey || // custom menukey ++ scan_code == 1 || // ESC ++ scan_code == 43 || // '\' char on keyboard ++ scan_code == 53 || // '/' char on keyboard ++ scan_code == 98) { // '/' char on numpad ++ if (!irqtimer_check(esc_accepted_time)) ++ continue; ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a message. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ printf("Menukey pressed.\n"); ++ return; ++ } ++ kb_choice = 0; ++ /* 4 rows of keyboard_keys: 1 row with numbers, 3 rows with letters. ++ Use any of them to select a boot device (except the TPM 'm-' keys) */ ++ // 1st range: 1-9 and 0 (10) keys <==> 2-11 scan codes <==> 1-10 choice ++ if (scan_code >= 2 && scan_code <= 11) kb_choice = scan_code - 1; ++ // 2nd range: Q-P row of letters <==> 16-25 scan codes <==> 11-20 choice ++ if (scan_code >= 16 && scan_code <= 25) kb_choice = scan_code - 5; ++ // 3rd range: A-L row of letters <==> 30-38 scan codes <==> 21-29 choice ++ if (scan_code >= 30 && scan_code <= 38) kb_choice = scan_code - 9; ++ // 4th range: Z-N row of letters <==> 44-49 scan codes <==> 30-35 choice ++ if (scan_code >= 44 && scan_code <= 49) kb_choice = scan_code - 14; ++ // ENTER: (28) on keyboard, (96) on numpad. ++ if (scan_code == 28 || scan_code == 96) ++ enter = 1; ++ // BCKSPC: '<-'(14) and 'Delete'(111) on keyboard, '.Del'(83) on numpad. ++ if (scan_code == 14 || scan_code == 111 || scan_code == 83) ++ backspace = 1; ++ // TPM keys: 'm'(50) and '-'(12) chars on keyboard, '-'(74) on numpad. ++ if ((scan_code == 50 || scan_code == 12 || scan_code == 74) && tpm_cshm) ++ tpm_show_menu = 1; ++ ++ if (kb_choice != 0 || tpm_show_menu) { ++ if (kb_choice > maxmenu) { ++ if (!tpm_show_menu) ++ continue; ++ } else { ++ choice = kb_choice; ++ } ++ if (digits == 2) // Remove the decoded "(*)" ++ printf(" \b\b\b"); ++ /* Remove the existing input before printing a choice. */ ++ for (; digits > 0; digits--) ++ printf("\b \b"); ++ if (!tpm_show_menu) { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } else { ++ // Internal/USB Numpad console interface. ++ if (digits < 9) { ++ for (numpi = 0; numpi < 10; numpi++) { ++ if (scan_code == numpad_scancodes[numpi]) { ++ if (maxmenu <= 10) { // Console interface is not needed. ++ if ((numpi != 0 && numpi <= maxmenu) || ++ (numpi == 0 && 10 <= maxmenu)) { // 10(0) ++ choice = numpi; ++ enter = 1; // Fake ENTER to boot this entry now. ++ } else { // If no such an entry, don't try to boot. ++ break; ++ } ++ } else { ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ if (choice == 0) { ++ printf("\b\b \b\b"); // Remove "10". ++ digits = 0; ++ } ++ } ++ choice = 10 * choice + numpi; ++ } ++ if (choice > 0) { ++ printf("%d", numpi); // Print the entered digit. ++ digits++; ++ } else { ++ if (10 <= maxmenu) ++ printf("10(0)\b\b\b"); ++ else ++ printf("10(?)\b\b\b"); ++ digits = 2; ++ } ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ break; ++ } ++ } ++ } ++ if (backspace && digits > 0) { ++ backspace = 0; ++ choice = choice / 10; ++ if (digits == 2) { ++ printf(" \b\b\b"); // Remove the decoded "(*)" ++ // 0 turned into 10: one more Backspace is needed to remove. ++ if (choice == 0) { ++ printf("\b \b"); ++ digits--; ++ } ++ } ++ printf("\b \b"); // Remove the last entered digit. ++ digits--; ++ if (choice > 9 && digits == 2) // Decode into a letter. ++ decode = 1; ++ } ++ if (decode) { // Decode the current choice number into a letter. ++ decode = 0; ++ if (choice <= maxmenu) { ++ printf("(%c)", keyboard_keys[choice-1]); ++ } else { ++ if (tpm_cshm && choice == 36) ++ printf("(m)"); // For TPM. ++ else ++ printf("(?)"); // No matching letter found. ++ } ++ printf("\b\b\b"); // Move a cursor before the "(*)" ++ } ++ } ++ ++ if (enter) { ++ enter = 0; ++ if (choice == 0) { ++ if (digits == 2) { // for 0 that turned into 10 ++ if (10 <= maxmenu) ++ break; ++ else ++ continue; ++ } ++ // If there are two pages - switch between them. ++ if (maxmenu > BOOTMENU_PAGE_SIZE) { ++ entry_id = 0; ++ page_num = 3 - page_num; // 3 - 1 = 2; 3 - 2 = 1. ++ printf("\n\nSelect boot device - page %d :" ++ " // press ENTER after your numpad input" ++ " - if any -\n " ++ " // - or to switch between the pages...\n", ++ page_num); ++ hlist_for_each_entry(pos, &BootList, node) { ++ if ((page_num == 1 && entry_id == BOOTMENU_PAGE_SIZE) || ++ (page_num == 2 && entry_id == 35)) ++ break; ++ if (page_num == 1 || entry_id >= BOOTMENU_PAGE_SIZE) ++ printf("%c. %s\n", keyboard_keys[entry_id], ++ strtcpy(desc, pos->description, ARRAY_SIZE(desc))); ++ entry_id++; ++ } ++ if (tpm_cshm) ++ printf("\nm-. TPM Configuration"); ++ printf("\n> "); ++ } ++ } else { ++ if (choice > maxmenu) { ++ if (tpm_cshm && choice == 36) ++ tpm_show_menu = 1; ++ } else { ++ // Choice is any of the detected boot devices ==> lets boot! ++ break; ++ } ++ } ++ } ++ ++ if (tpm_show_menu) { ++ tpm_show_menu = 0; ++ choice = 0; ++ if (digits == 0) ++ printf("TPM key pressed."); ++ else ++ digits = 0; + printf("\n"); + tpm_menu(); ++ printf("> "); + } +- if (scan_code >= 1 && scan_code <= maxmenu+1) +- break; ++ } ++ ++ if (choice == 0) // 10(0) ++ choice = 10; ++ ++ if (digits == 0 && choice < 36) { ++ printf("%c", keyboard_keys[choice-1]); ++ if (choice > 9) // Decode into a number. ++ printf("(%d)", choice); + } + printf("\n"); +- if (scan_code == 0x01) +- // ESC +- return; + + // Find entry and make top priority. +- int choice = scan_code - 1; + hlist_for_each_entry(pos, &BootList, node) { + if (! --choice) + break; +diff --git a/src/config.h b/src/config.h +index 93c8dbc..f85cc14 100644 +--- a/src/config.h ++++ b/src/config.h +@@ -19,7 +19,7 @@ + // Space to reserve in high-memory for tables + #define BUILD_MAX_HIGHTABLE (256*1024) + // Largest supported externaly facing drive id +-#define BUILD_MAX_EXTDRIVE 16 ++#define BUILD_MAX_EXTDRIVE 36 + // Number of bytes the smbios may be and still live in the f-segment + #define BUILD_MAX_SMBIOS_FSEG 600 + // Maximum number of bytes the mptable may be and still be copied to f-segment diff --git a/payloads/external/SeaBIOS/multiple_floppies.patch b/payloads/external/SeaBIOS/multiple_floppies.patch new file mode 100644 index 0000000..5249394 --- /dev/null +++ b/payloads/external/SeaBIOS/multiple_floppies.patch @@ -0,0 +1,207 @@ +diff --git a/src/block.h b/src/block.h +index f64e880..aaa236f 100644 +--- a/src/block.h ++++ b/src/block.h +@@ -2,7 +2,7 @@ + #define __BLOCK_H + + #include "types.h" // u32 +- ++#include "romfile.h" // struct romfile_s + + /**************************************************************** + * Disk command request +@@ -48,6 +48,7 @@ struct drive_s { + struct drive_s { + u8 type; // Driver type (DTYPE_*) + u8 floppy_type; // Type of floppy (only for floppy drives). ++ struct romfile_s *floppy_file; // Floppy file (only for virtual floppies). + struct chs_s lchs; // Logical CHS + u64 sectors; // Total sectors count + u32 cntl_id; // Unique id for a given driver type. +diff --git a/src/boot.c b/src/boot.c +index 9f82f3c..79f1e7d 100644 +--- a/src/boot.c ++++ b/src/boot.c +@@ -584,7 +584,7 @@ bcv_prepboot(void) + break; + case IPL_TYPE_FLOPPY: + map_floppy_drive(pos->drive); +- add_bev(IPL_TYPE_FLOPPY, 0); ++ add_bev(IPL_TYPE_FLOPPY, (u32)pos->drive); + break; + case IPL_TYPE_HARDDISK: + map_hd_drive(pos->drive); +@@ -733,6 +733,12 @@ do_boot(int seq_nr) + static void + do_boot(int seq_nr) + { ++ ++ int ret; ++ void *pos; ++ struct romfile_s *file; ++ struct drive_s *drive; ++ + if (! CONFIG_BOOT) + panic("Boot support not compiled in.\n"); + +@@ -744,6 +750,16 @@ do_boot(int seq_nr) + switch (ie->type) { + case IPL_TYPE_FLOPPY: + printf("Booting from Floppy...\n"); ++ drive = (struct drive_s *)ie->vector; ++ file = drive->floppy_file; ++ // File is NULL if a floppy is physical. ++ if (file) { ++ // Copy virtual floppy image into ram. ++ pos = (void *)drive->cntl_id; ++ ret = file->copy(file, pos, file->size); ++ if (ret < 0) ++ break; ++ } + boot_disk(0x00, CheckFloppySig); + break; + case IPL_TYPE_HARDDISK: +diff --git a/src/hw/floppy.c b/src/hw/floppy.c +index 9e6647d..5b37c6c 100644 +--- a/src/hw/floppy.c ++++ b/src/hw/floppy.c +@@ -107,7 +107,7 @@ struct floppyinfo_s FloppyInfo[] VARFSEG = { + }; + + struct drive_s * +-init_floppy(int floppyid, int ftype) ++init_floppy(int floppyid, int ftype, struct romfile_s *ffile) + { + if (ftype <= 0 || ftype >= ARRAY_SIZE(FloppyInfo)) { + dprintf(1, "Bad floppy type %d\n", ftype); +@@ -124,6 +124,7 @@ init_floppy(int floppyid, int ftype) + drive->type = DTYPE_FLOPPY; + drive->blksize = DISK_SECTOR_SIZE; + drive->floppy_type = ftype; ++ drive->floppy_file = ffile; + drive->sectors = (u64)-1; + + memcpy(&drive->lchs, &FloppyInfo[ftype].chs +@@ -134,7 +135,7 @@ addFloppy(int floppyid, int ftype) + static void + addFloppy(int floppyid, int ftype) + { +- struct drive_s *drive = init_floppy(floppyid, ftype); ++ struct drive_s *drive = init_floppy(floppyid, ftype, 0); + if (!drive) + return; + char *desc = znprintf(MAXDESCSIZE, "Floppy [drive %c]", 'A' + floppyid); +diff --git a/src/hw/ramdisk.c b/src/hw/ramdisk.c +index b9e9baa..a679385 100644 +--- a/src/hw/ramdisk.c ++++ b/src/hw/ramdisk.c +@@ -23,40 +23,69 @@ ramdisk_setup(void) + if (!CONFIG_FLASH_FLOPPY) + return; + +- // Find image. +- struct romfile_s *file = romfile_findprefix("floppyimg/", NULL); +- if (!file) +- return; +- const char *filename = file->name; +- u32 size = file->size; +- dprintf(3, "Found floppy file %s of size %d\n", filename, size); +- int ftype = find_floppy_type(size); +- if (ftype < 0) { +- dprintf(3, "No floppy type found for ramdisk size\n"); ++ struct romfile_s *file = NULL; ++ char *filename, *desc; ++ u32 size, max_size = 0; ++ int ftype; ++ void *pos; ++ struct drive_s *drive; ++ ++ // Find the max floppy size ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ break; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ // Check if this size is valid. ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ if (size > max_size) ++ max_size = size; ++ } ++ } ++ if (max_size == 0) { ++ dprintf(3, "No floppies found\n"); + return; + } + + // Allocate ram for image. +- void *pos = memalign_tmphigh(PAGE_SIZE, size); ++ pos = memalign_tmphigh(PAGE_SIZE, max_size); + if (!pos) { + warn_noalloc(); + return; + } +- e820_add((u32)pos, size, E820_RESERVED); ++ e820_add((u32)pos, max_size, E820_RESERVED); ++ dprintf(3, "Allocate %u bytes for a floppy\n", max_size); + +- // Copy image into ram. +- int ret = file->copy(file, pos, size); +- if (ret < 0) +- return; +- +- // Setup driver. +- struct drive_s *drive = init_floppy((u32)pos, ftype); +- if (!drive) +- return; +- drive->type = DTYPE_RAMDISK; +- dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); +- char *desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); +- boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ // Setup the floppy drivers. ++ file = NULL; ++ for (;;) { ++ // Find the next image. ++ file = romfile_findprefix("floppyimg/", file); ++ if (!file) ++ return; ++ filename = file->name; ++ size = file->size; ++ dprintf(3, "Found floppy file %s of size %d\n", filename, size); ++ ftype = find_floppy_type(size); ++ if (ftype < 0) { ++ dprintf(3, "No floppy type found for ramdisk size\n"); ++ } else { ++ // Setup driver. ++ drive = init_floppy((u32)pos, ftype, file); ++ if (!drive) ++ return; ++ drive->type = DTYPE_RAMDISK; ++ dprintf(1, "Mapping floppy %s to addr %p\n", filename, pos); ++ desc = znprintf(MAXDESCSIZE, "Ramdisk [%s]", &filename[10]); ++ boot_add_floppy(drive, desc, bootprio_find_named_rom(filename, 0)); ++ } ++ } + } + + static int +diff --git a/src/util.h b/src/util.h +index 9c06850..ce3a26d 100644 +--- a/src/util.h ++++ b/src/util.h +@@ -147,7 +147,8 @@ void dma_setup(void); + // hw/floppy.c + extern struct floppy_ext_dbt_s diskette_param_table2; + void floppy_setup(void); +-struct drive_s *init_floppy(int floppyid, int ftype); ++extern struct romfile_s *ffile; ++struct drive_s *init_floppy(int floppyid, int ftype, struct romfile_s *ffile); + int find_floppy_type(u32 size); + int floppy_process_op(struct disk_op_s *op); + void floppy_tick(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4efba31091a8678b51c2f6541d440c5cc6d37d Gerrit-Change-Number: 32351 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 32

Change in coreboot[master]: pci: Add support for assigning resources to SR-IOV VF BARs
by Name of user not set (Code Review) May 28, 2025

May 28, 2025

stephend(a)silicom-usa.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34620 ) Change subject: pci: Add support for assigning resources to SR-IOV VF BARs ...................................................................... pci: Add support for assigning resources to SR-IOV VF BARs This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages like: pci 0000:03:00.0: BAR 7: no space for [mem size 0x00100000 64bit] pci 0000:03:00.0: BAR 7: failed to assign [mem size 0x00100000 64bit] Tested on Camelback Mountain, and Harcuvar. Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend(a)silicom-usa.com> --- M src/device/pci_device.c M src/device/pciexp_device.c M src/include/device/pci_def.h M src/include/device/pciexp.h 4 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34620/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 7786043..c96fc8d 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -439,6 +439,11 @@ { pci_read_bases(dev, 6); pci_get_rom_resource(dev, PCI_ROM_ADDRESS); + +#if CONFIG(PCIEXP_PLUGIN_SUPPORT) + /* Check for SR-IOV BARs if we have PCIe support */ + pciexp_dev_read_resources(dev); +#endif } void pci_bus_read_resources(struct device *dev) diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index c209816..8d660b1 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -442,6 +442,82 @@ pciexp_enable_aspm(root, root_cap, dev, cap); } +/* + * Check if this is an SR-IOV capable device and add resources for all VF bars + * + * @param dev Pointer to the dev structure. + */ +void pciexp_dev_read_resources(struct device *dev) +{ + unsigned long sriovpos; + u16 numvfs, i; + + sriovpos = pci_find_capability(dev, PCI_CAP_ID_PCIE); + if (!sriovpos) { + return; + } + + sriovpos = pciexp_find_extended_cap(dev, PCI_EXT_CAP_ID_SRIOV); + if (!sriovpos) { + return; + } + + numvfs = pci_read_config16(dev, sriovpos + PCI_SRIOV_TOT_VFS); + printk(BIOS_DEBUG, "%s: supports %d SR-IOV VFs\n", dev_path(dev), numvfs); + + /* The spec allows this to be 0 for some reason. Nothing to do. */ + if (numvfs == 0) { + return; + } + + for (int off = 0; off < 6; off++) { + unsigned long res_ix = sriovpos + PCI_SRIOV_VFBAR0 + off * 4; + struct resource *resource; + + resource = pci_get_resource(dev, res_ix); + + /* VF BARs aren't necessarily contiguous, skip the unused ones */ + if (resource->size == 0) { + continue; + } + + printk(BIOS_DEBUG, "%s: found %dbit SR-IOV BAR, size 0x%llx @ index %lx\n", + dev_path(dev), (resource->flags & IORESOURCE_PCI64) ? 64 : 32, + resource->size, resource->index); + + if (resource->flags & IORESOURCE_PCI64) { + off++; + } + + /* + * SR-IOV BARs break the resource allocator assumption for PCI + * dev resources that size = gran = alignment. + * + * alignment = gran = pci_get_resource() result, but... + * size is pci_get_resource()->size * numvfs, and there's no + * power of two guarantee on size either since numvfs is just + * an integer. + * + * Rather than add code to handle this as a special case in the + * resource allocator, just round up the size. In practice + * MaxVfs tends to be 2^n or 2^n - 1, so the holes produced + * should only be the size of a single VF BAR + */ + for (i = 1; i < numvfs; i <<= 1) { + resource->size <<= 1; + resource->align += 1; + resource->gran += 1; + } + + if (i != numvfs) { + printk(BIOS_DEBUG, "%s: VFs != 2^n, wasting MMIO space...\n", + dev_path(dev)); + } + } + + compact_resources(dev); +} + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn) { diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index bc5bc79..39a6137 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -453,6 +453,7 @@ #define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_PWR 4 +#define PCI_EXT_CAP_ID_SRIOV 0x0010 /* Extended Capability lists*/ #define PCIE_EXT_CAP_OFFSET 0x100 @@ -518,6 +519,34 @@ #define PCI_PWR_CAP 12 /* Capability */ #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */ +/* SR-IOV */ +#define PCI_SRIOV_CAPS 0x04 /* SR-IOV capabilities */ +#define PCI_SRIOV_VF_MIG (1 << 0) /* VF Migration capable */ +#define PCI_SRIOV_ARI_CAP (1 << 1) /* ARI Capable Hierarchy Preserved */ +#define PCI_SRIOV_MIG_INT(x) (((x) >> 21) & 0x7ff) +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_VF_EN (1 << 0) +#define PCI_SRIOV_MIG_EN (1 << 1) +#define PCI_SRIOV_MIG_INT_EN (1 << 2) +#define PCI_SRIOV_MSE (1 << 3) +#define PCI_SRIOV_ARI_CAP_EN (1 << 4) +#define PCI_SRIOV_STATUS 0x0A /* SR-IOV Status */ +#define PCI_SRIOV_INIT_VFS 0x0C +#define PCI_SRIOV_TOT_VFS 0x0E +#define PCI_SRIOV_NUM_VFS 0x10 +#define PCI_SRIOV_FN_DEP_LINK 0x12 +#define PCI_SRIOV_VF_OFF 0x14 +#define PCI_SRIOV_VF_STRIDE 0x16 +#define PCI_SRIOV_VF_DEVID 0x1A +#define PCI_SRIOV_SUP_PAGE_SIZE 0x1C +#define PCI_SRIOV_PAGE_SIZE 0x20 +#define PCI_SRIOV_VFBAR0 0x24 +#define PCI_SRIOV_VFBAR1 0x28 +#define PCI_SRIOV_VFBAR2 0x2C +#define PCI_SRIOV_VFBAR3 0x30 +#define PCI_SRIOV_VFBAR4 0x34 +#define PCI_SRIOV_VFBAR5 0x38 +#define PCI_SRIOV_MIG_ARRAY 0x3C /* * The PCI interface treats multi-function devices as independent diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d..94a80bf 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -19,6 +19,8 @@ /* Latency tolerance reporting, max snoop latency value 3.14ms */ #define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003 +void pciexp_dev_read_resources(struct device *dev); + void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn, unsigned int max_devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/34620 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Gerrit-Change-Number: 34620 Gerrit-PatchSet: 1 Gerrit-Owner: stephend(a)silicom-usa.com Gerrit-MessageType: newchange

8 14

Change in ...coreboot[master]: autoport: Add support for Haswell-LynxPoint platform
by Iru Cai (vimacs) (Code Review) July 14, 2024

July 14, 2024

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/30890 to review the following change. Change subject: autoport: Add support for Haswell-LynxPoint platform ...................................................................... autoport: Add support for Haswell-LynxPoint platform It can now generate a buildable source for Clevo W650SZ. TODO: - Support Lynx Point LP (GPIO registers differ from non-LP) - Use PCH HD-Audio in azilia instead of the CPU/Northbridge HD-Audio Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M util/autoport/azalia.go A util/autoport/haswell.go A util/autoport/lynxpoint.go M util/autoport/main.go 4 files changed, 625 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/30890/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index c525189..3090dd0 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -62,4 +62,9 @@ RegisterPCI(0x8086, 0x1c20, azalia{}) /* C216/ivybridge */ RegisterPCI(0x8086, 0x1e20, azalia{}) + /* Haswell */ + RegisterPCI(0x8086, 0x0c0c, azalia{}) + /* Lynx Point */ + RegisterPCI(0x8086, 0x8c20, azalia{}) + RegisterPCI(0x8086, 0x9c20, azalia{}) } diff --git a/util/autoport/haswell.go b/util/autoport/haswell.go new file mode 100644 index 0000000..d3c9d9f --- /dev/null +++ b/util/autoport/haswell.go @@ -0,0 +1,119 @@ +package main + +type haswellmc struct { + variant string +} + +func (i haswellmc) Scan(ctx Context, addr PCIDevData) { + inteltool := ctx.InfoSource.GetInteltool() + + /* FIXME:XX Move this somewhere else. */ + MainboardIncludes = append(MainboardIncludes, "drivers/intel/gma/int15.h") + MainboardEnable += (` /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +`) + + DevTree = DevTreeNode{ + Chip: "northbridge/intel/haswell", + MissingParent: "northbridge", + Comment: "FIXME: check gfx.ndid and gfx.did", + Registers: map[string]string{ + "gpu_dp_b_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 2) & 7), + "gpu_dp_c_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 10) & 7), + "gpu_dp_d_hotplug": FormatInt32((inteltool.IGD[0xc4030] >> 18) & 7), + "gpu_panel_port_select": FormatInt32((inteltool.IGD[0xc7208] >> 30) & 3), + "gpu_panel_power_up_delay": FormatInt32((inteltool.IGD[0xc7208] >> 16) & 0x1fff), + "gpu_panel_power_backlight_on_delay": FormatInt32(inteltool.IGD[0xc7208] & 0x1fff), + "gpu_panel_power_down_delay": FormatInt32((inteltool.IGD[0xc720c] >> 16) & 0x1fff), + "gpu_panel_power_backlight_off_delay": FormatInt32(inteltool.IGD[0xc720c] & 0x1fff), + "gpu_panel_power_cycle_delay": FormatInt32(inteltool.IGD[0xc7210] & 0xff), + "gpu_cpu_backlight": FormatHex32(inteltool.IGD[0x48254]), + "gpu_pch_backlight": FormatHex32((inteltool.IGD[0xc8254] >> 16) * 0x10001), + "gpu_ddi_e_connected": FormatBool(((inteltool.IGD[0x64000] >> 4) & 1) == 0), + /* FIXME:XX hardcoded. */ + "gfx.ndid": "3", + "gfx.did": "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }", + }, + Children: []DevTreeNode{ + { + Chip: "cpu_cluster", + Dev: 0, + Children: []DevTreeNode{ + { + Chip: "cpu/intel/haswell", + Children: []DevTreeNode{ + { + Chip: "lapic", + Dev: 0, + }, + { + Chip: "lapic", + Dev: 0xacac, + Disabled: true, + }, + }, + Registers: map[string]string{ + /* FIXME:XX hardcoded. */ + "c1_acpower": "1", + "c2_acpower": "3", + "c3_acpower": "5", + "c1_battery": "1", + "c2_battery": "3", + "c3_battery": "5", + }, + }, + }, + }, + + { + Chip: "domain", + Dev: 0, + PCIController: true, + ChildPCIBus: 0, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PCIe Bridge for discrete graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "Internal graphics"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x3, Func: 0}, writeEmpty: true, additionalComment: "Mini-HD audio"}, + }, + }, + }, + } + + PutPCIDev(addr, "Host bridge") + + /* FIXME:XX some configs are unsupported. */ + + KconfigBool["CPU_INTEL_HASWELL"] = true + KconfigBool["NORTHBRIDGE_INTEL_HASWELL"] = true + KconfigBool["INTEL_INT15"] = true + KconfigBool["HAVE_ACPI_TABLES"] = true + KconfigBool["HAVE_ACPI_RESUME"] = true + + KconfigInt["MAX_CPUS"] = 8 + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "cpu/intel/common/acpi/cpu.asl", + }) + + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "northbridge/intel/haswell/acpi/haswell.asl", + }, DSDTInclude{ + File: "drivers/intel/gma/acpi/default_brightness_levels.asl", + }) +} + +func init() { + RegisterPCI(0x8086, 0x0c00, haswellmc{variant: "Desktop"}) + RegisterPCI(0x8086, 0x0c04, haswellmc{variant: "Mobile"}) + RegisterPCI(0x8086, 0x0a04, haswellmc{variant: "ULT"}) + RegisterPCI(0x8086, 0x0c08, haswellmc{variant: "Server"}) + for _, id := range []uint16{ + 0x0402, 0x0412, 0x0422, + 0x0406, 0x0416, 0x0426, + 0x0d16, 0x0d26, 0x0d36, + 0x0a06, 0x0a16, 0x0a26, + } { + RegisterPCI(0x8086, id, GenericVGA{GenericPCI{Comment: "VGA controller"}}) + } +} diff --git a/util/autoport/lynxpoint.go b/util/autoport/lynxpoint.go new file mode 100644 index 0000000..df20c3f --- /dev/null +++ b/util/autoport/lynxpoint.go @@ -0,0 +1,495 @@ +package main + +import ( + "fmt" + "os" +) + +type lynxpoint struct { + variant string + node *DevTreeNode +} + +func (b lynxpoint) writeGPIOSet(ctx Context, sb *os.File, + val uint32, set uint, partno int, constraint uint32) { + + max := uint(32) + if set == 3 { + max = 12 + } + + bits := [6][2]string{ + {"GPIO_MODE_NATIVE", "GPIO_MODE_GPIO"}, + {"GPIO_DIR_OUTPUT", "GPIO_DIR_INPUT"}, + {"GPIO_LEVEL_LOW", "GPIO_LEVEL_HIGH"}, + {"GPIO_RESET_PWROK", "GPIO_RESET_RSMRST"}, + {"GPIO_NO_INVERT", "GPIO_INVERT"}, + {"GPIO_NO_BLINK", "GPIO_BLINK"}, + } + + for i := uint(0); i < max; i++ { + if ((constraint>>i)&1 == 1) { + fmt.Fprintf(sb, " .gpio%d = %s,\n", + (set-1)*32+i, + bits[partno][(val>>i)&1]) + } + } +} + +func (b lynxpoint) GPIO(ctx Context, inteltool InteltoolData) { + var constraint uint32 + gpio := Create(ctx, "gpio.c") + defer gpio.Close() + + AddROMStageFile("gpio.c", "") + + Add_gpl(gpio) + gpio.WriteString("#include <southbridge/intel/common/gpio.h>\n\n") + + /* TODO: different in LP PCH */ + addresses := [3][6]int{ + {0x00, 0x04, 0x0c, 0x60, 0x2c, 0x18}, + {0x30, 0x34, 0x38, 0x64, -1, -1}, + {0x40, 0x44, 0x48, 0x68, -1, -1}, + } + + for set := 1; set <= 3; set++ { + for partno, part := range []string{"mode", "direction", "level", "reset", "invert", "blink"} { + addr := addresses[set-1][partno] + if addr < 0 { + continue + } + fmt.Fprintf(gpio, "static const struct pch_gpio_set%d pch_gpio_set%d_%s = {\n", + set, set, part) + + constraint = 0xffffffff + switch part { + case "direction": + /* Ignored on native mode */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + case "level": + /* Level doesn't matter for input */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + case "reset": + /* Only show reset */ + constraint = inteltool.GPIO[uint16(addresses[set-1][3])] + case "invert": + /* Only on input and only show inverted GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][4])] + case "blink": + /* Only on output and only show blinking GPIO */ + constraint = inteltool.GPIO[uint16(addresses[set-1][0])] + constraint &^= inteltool.GPIO[uint16(addresses[set-1][1])] + constraint &= inteltool.GPIO[uint16(addresses[set-1][5])] + } + b.writeGPIOSet(ctx, gpio, inteltool.GPIO[uint16(addr)], uint(set), partno, constraint) + gpio.WriteString("};\n\n") + } + } + + gpio.WriteString(`const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; +`) +} + +func (b lynxpoint) IsPCIeHotplug(ctx Context, port int) bool { + portDev, ok := PCIMap[PCIAddr{Bus: 0, Dev: 0x1c, Func: port}] + if !ok { + return false + } + return (portDev.ConfigDump[0xdb] & (1 << 6)) != 0 +} + +func (b lynxpoint) GetGPIOHeader() string { + return "southbridge/intel/lynxpoint/pch.h" +} + +func (b lynxpoint) EnableGPE(in int) { + b.node.Registers[fmt.Sprintf("gpi%d_routing", in)] = "2" +} + +func (b lynxpoint) EncodeGPE(in int) int { + return in + 0x10 +} + +func (b lynxpoint) DecodeGPE(in int) int { + return in - 0x10 +} + +func (b lynxpoint) NeedRouteGPIOManually() { + b.node.Comment += ", FIXME: set gpiX_routing for EC support" +} + +func (b lynxpoint) Scan(ctx Context, addr PCIDevData) { + + SouthBridge = &b + + inteltool := ctx.InfoSource.GetInteltool() + b.GPIO(ctx, inteltool) + + KconfigBool["SOUTHBRIDGE_INTEL_LYNXPOINT"] = true + if b.variant == "Lynx Point LP" { + KconfigBool["INTEL_LYNXPOINT_LP"] = true + } + KconfigBool["SERIRQ_CONTINUOUS_MODE"] = true + KconfigInt["USBDEBUG_HCD_INDEX"] = 2 + KconfigComment["USBDEBUG_HCD_INDEX"] = "FIXME: check this" + dmi := ctx.InfoSource.GetDMI() + if dmi.Vendor == "LENOVO" { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 10 + } else { + KconfigInt["DRAM_RESET_GATE_GPIO"] = 60 + } + KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" + + /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. + But most systems don't have any of those. But the config needs to be set + nevertheless. So set it to southbridge subsys/subvendor. */ + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) + KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) + + ich9GetFlashSize(ctx) + + DSDTDefines = append(DSDTDefines, + DSDTDefine{ + Key: "BRIGHTNESS_UP", + Value: "\\_SB.PCI0.GFX0.INCB", + }, + DSDTDefine{ + Key: "BRIGHTNESS_DOWN", + Value: "\\_SB.PCI0.GFX0.DECB", + }, + DSDTDefine{ + Key: "ACPI_VIDEO_DEVICE", + Value: "\\_SB.PCI0.GFX0", + }) + + /* SPI init */ + MainboardIncludes = append(MainboardIncludes, "southbridge/intel/lynxpoint/pch.h") + + cur := DevTreeNode{ + Chip: "southbridge/intel/lynxpoint", + Comment: "Intel Series 8 Lynx Point PCH", + + Registers: map[string]string{ + "pirqa_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x60]), + "pirqb_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x61]), + "pirqc_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x62]), + "pirqd_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x63]), + "pirqe_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x68]), + "pirqf_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x69]), + "pirqg_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6a]), + "pirqh_routing": FormatHex8(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x6b]), + "sata_ahci": "1", + "gen1_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x84:0x88]), + "gen2_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x88:0x8c]), + "gen3_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x8c:0x90]), + "gen4_dec": FormatHexLE32(PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 0}].ConfigDump[0x90:0x94]), + "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), + }, + PCISlots: []PCISlot{ + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + }, + } + + b.node = &cur + + PutPCIChip(addr, cur) + PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/platform.asl", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/globalnvs.asl", + Comment: "global NVS and variables", + }) + DSDTIncludes = append(DSDTIncludes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/sleepstates.asl", + }) + DSDTPCI0Includes = append(DSDTPCI0Includes, DSDTInclude{ + File: "southbridge/intel/lynxpoint/acpi/pch.asl", + }) + + sb := Create(ctx, "romstage.c") + defer sb.Close() + Add_gpl(sb) + sb.WriteString(`#include <stdint.h> +#include <cpu/intel/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { +`) + RestoreDIRRoute(sb, "D31IR", uint16(inteltool.RCBA[0x3140])) + RestoreDIRRoute(sb, "D29IR", uint16(inteltool.RCBA[0x3144])) + RestoreDIRRoute(sb, "D28IR", uint16(inteltool.RCBA[0x3146])) + RestoreDIRRoute(sb, "D27IR", uint16(inteltool.RCBA[0x3148])) + RestoreDIRRoute(sb, "D26IR", uint16(inteltool.RCBA[0x314c])) + RestoreDIRRoute(sb, "D25IR", uint16(inteltool.RCBA[0x3150])) + RestoreDIRRoute(sb, "D22IR", uint16(inteltool.RCBA[0x315c])) + RestoreDIRRoute(sb, "D20IR", uint16(inteltool.RCBA[0x3160])) + + sb.WriteString(` + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +};`) + + sb.WriteString(` + +void mainboard_config_superio(void) +{ +} + +void mainboard_romstage_entry(unsigned long bist) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server, FIXME: check this */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, /* FIXME: check this */ + .ec_present = 0, + .dimm_channel0_disabled = 0, /* FIXME: leave channel 0 enabled */ + .dimm_channel1_disabled = 0, /* FIXME: leave channel 1 enabled */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ +`) + + pdo1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x64] + ocmap1 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1d, Func: 0}].ConfigDump[0x74:0x78] + pdo2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x64] + ocmap2 := PCIMap[PCIAddr{Bus: 0, Dev: 0x1a, Func: 0}].ConfigDump[0x74:0x78] + + for port := uint(0); port < 14; port++ { + var port_oc int = -1 + var port_pos string + var port_disable uint8 + + if port < 8 { + port_disable = (pdo1 >> port) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap1[oc] & (1 << port)) != 0) { + port_oc = oc + break + } + } + } else { + port_disable = (pdo2 >> (port - 8)) & 1 + for oc := 0; oc < 4; oc++ { + if ((ocmap2[oc] & (1 << (port - 8))) != 0) { + port_oc = oc + 4 + break + } + } + } + if port_disable == 1 { + port_pos = "USB_PORT_SKIP" + } else { + port_pos = "USB_PORT_BACK_PANEL" + } + if port_oc == -1 { + fmt.Fprintf(sb, " { 0x0040, %d, USB_OC_PIN_SKIP, %s },\n", + (port_disable ^ 1), port_pos) + } else { + fmt.Fprintf(sb, " { 0x0040, %d, %d, %s },\n", + (port_disable ^ 1), port_oc, port_pos) + } + } + + sb.WriteString(` }, + .usb3_ports = { +`) + + xpdo := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xe8] + u3ocm := PCIMap[PCIAddr{Bus: 0, Dev: 0x14, Func: 0}].ConfigDump[0xc8:0xd0] + + for port := uint(0); port < 6; port++ { + var port_oc int = -1 + port_disable := (xpdo >> port) & 1 + for oc := 0; oc < 8; oc++ { + if (u3ocm[oc] & (1 << port)) != 0 { + port_oc = oc + break + } + } + if port_oc == -1 { + fmt.Fprintf(sb, " { %d, USB_OC_PIN_SKIP },\n", + (port_disable ^ 1)) + } else { + fmt.Fprintf(sb, " { %d, %d },\n", + (port_disable ^ 1), port_oc) + } + } + + sb.WriteString(` }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + .bist = bist, + }; + + romstage_common(&romstage_params); +}`) + + gnvs := Create(ctx, "acpi_tables.c") + defer gnvs.Close() + + Add_gpl(gnvs) + gnvs.WriteString(`#include <southbridge/intel/lynxpoint/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} +`) + +} + +func init() { + for _, id := range []uint16 { + 0x8c41, 0x8c49, 0x8c4b, 0x8c4f, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Mobile"}) + } + + for _, id := range []uint16 { + 0x8c42, 0x8c44, 0x8c46, 0x8c4a, + 0x8c4c, 0x8c4e, 0x8c50, 0x8c5c, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Desktop"}) + } + + for _, id := range []uint16 { + 0x8c52, 0x8c54, 0x8c56, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point Server"}) + } + + for _, id := range []uint16 { + 0x9c41, 0x9c43, 0x9c45, + } { + RegisterPCI(0x8086, uint16(id), lynxpoint{variant: "Lynx Point LP"}) + } + + /* PCIe bridge */ + for _, id := range []uint16{ + 0x8c10, 0x8c12, 0x8c14, 0x8c16, 0x8c18, 0x8c1a, 0x8c1c, 0x8c1e, + 0x9c10, 0x9c12, 0x9c14, 0x9c16, 0x9c18, 0x9c1a, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* SMBus controller */ + RegisterPCI(0x8086, 0x1c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x1e22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x8c22, GenericPCI{MissingParent: "smbus"}) + RegisterPCI(0x8086, 0x9c22, GenericPCI{MissingParent: "smbus"}) + + /* SATA */ + for _, id := range []uint16{ + 0x8c00, 0x8c02, 0x8c04, 0x8c06, 0x8c08, 0x8c0e, + 0x8c01, 0x8c03, 0x8c05, 0x8c07, 0x8c09, 0x8c0f, + 0x9c03, 0x9c05, 0x9c07, 0x9c0f, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* EHCI */ + for _, id := range []uint16{ + 0x9c26, 0x8c26, 0x8c2d, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* XHCI */ + RegisterPCI(0x8086, 0x8c31, GenericPCI{}) + RegisterPCI(0x8086, 0x9c31, GenericPCI{}) + + /* ME and children */ + for _, id := range []uint16{ + 0x8c3a, 0x8c3b, + } { + RegisterPCI(0x8086, id, GenericPCI{}) + } + + /* Ethernet */ + RegisterPCI(0x8086, 0x8c33, GenericPCI{}) +} diff --git a/util/autoport/main.go b/util/autoport/main.go index 05a829b..c1920a7 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -236,6 +236,12 @@ pcidev.ConfigDump[addr]) } +func RestoreDIRRoute(f *os.File, regname string, val uint16) { + fmt.Fprintf(f, " RCBA_SET_REG_16(%s, DIR_ROUTE(PIRQ%c, PIRQ%c, PIRQ%c, PIRQ%c)),\n", + regname, 'A' + (val & 7), 'A' + ((val >> 4) & 7), + 'A' + ((val >> 8) & 7), 'A' + ((val >> 12) & 7)) +} + func RestorePCI32Simple(f *os.File, pcidev PCIDevData, addr uint16) { fmt.Fprintf(f, " pci_write_config32(PCI_DEV(%d, 0x%02x, %d), 0x%02x, 0x%02x%02x%02x%02x);\n", pcidev.Bus, pcidev.Dev, pcidev.Func, addr, -- To view, visit https://review.coreboot.org/c/coreboot/+/30890 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f6e8c97b5122101de2f36bba8ba9f8ddd5b813a Gerrit-Change-Number: 30890 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

15 92

Change in coreboot[master]: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/...
by Matt Parnell (Code Review) June 8, 2024

June 8, 2024

Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34946 ) Change subject: WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port ...................................................................... WIP: add WIP it8987e src/ec/hp/it8987e port and WIP src/mainboard/hp/spectre_x360_13t_ae000 port Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 --- A src/ec/hp/it8987e/Kconfig A src/ec/hp/it8987e/Makefile.inc A src/ec/hp/it8987e/acpi/ac.asl A src/ec/hp/it8987e/acpi/battery.asl A src/ec/hp/it8987e/acpi/ec.asl A src/ec/hp/it8987e/acpi/kb.asl A src/ec/hp/it8987e/acpi/superio.asl A src/ec/hp/it8987e/acpi/tpm.asl A src/ec/hp/it8987e/chip.h A src/ec/hp/it8987e/ec.c A src/ec/hp/it8987e/ec.h A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig A src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name A src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl A src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c A src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt A src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb A src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl A src/mainboard/hp/spectre_x360_13t_ae000/gpio.h A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c A src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h A src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c A src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c A src/mainboard/hp/spectre_x360_13t_ae000/romstage.c 31 files changed, 5,065 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/34946/1 diff --git a/src/ec/hp/it8987e/Kconfig b/src/ec/hp/it8987e/Kconfig new file mode 100644 index 0000000..54f7896 --- /dev/null +++ b/src/ec/hp/it8987e/Kconfig @@ -0,0 +1,4 @@ +config EC_HP_IT8987E + bool + help + Interface to QUANTA/HP IT8987E Embedded Controller. diff --git a/src/ec/hp/it8987e/Makefile.inc b/src/ec/hp/it8987e/Makefile.inc new file mode 100644 index 0000000..db11205 --- /dev/null +++ b/src/ec/hp/it8987e/Makefile.inc @@ -0,0 +1,8 @@ +ifeq ($(CONFIG_EC_HP_IT8987E),y) + +romstage-y += ec.c +ramstage-y += ec.c +smm-y += ec.c +smm-y += ../../../lib/delay.c + +endif diff --git a/src/ec/hp/it8987e/acpi/ac.asl b/src/ec/hp/it8987e/acpi/ac.asl new file mode 100644 index 0000000..bb4b4fe --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ac.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (AC) +{ + Name (_HID, "ACPI0003") + Name (_PCL, Package () { \_SB }) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + Local0 = ^^PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = One + } + + Return (Local0) + } + + Method (_STA) + { + Return (0x0F) + } +} diff --git a/src/ec/hp/it8987e/acpi/battery.asl b/src/ec/hp/it8987e/acpi/battery.asl new file mode 100644 index 0000000..75efd92 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, One) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, Zero) + Name (B1ST, 0x0F) + Name (B1WT, Zero) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((^^PCI0.LPCB.EC0.ECOK == One)) + { + If (^^PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = ^^PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [One] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += One + If ((^^PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == One)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = ^^PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = ^^PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [Zero] = One + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == One)) + { + Local0 = ^^PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [One] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [One] = Local3 + } + } + Else + { + PBST [One] = Local0 + } + } + Else + { + PBST [One] = 0xFFFFFFFF + } + + Local5 = ^^PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!^^PCI0.LPCB.EC0.SW2S && (^^PCI0.LPCB.EC0.BACR == One))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = ^^PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [Zero] = ^^PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/ec/hp/it8987e/acpi/ec.asl b/src/ec/hp/it8987e/acpi/ec.asl new file mode 100644 index 0000000..0692ced --- /dev/null +++ b/src/ec/hp/it8987e/acpi/ec.asl @@ -0,0 +1,1201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * The mainboard must define a PNOT method to handle power + * state notifications and Notify CPU device objects to + * re-evaluate their _PPC and _CST tables. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (PHOT, One) + Name (ECAV, Zero) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (BFFR, ResourceTemplate () + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + Return (BFFR) /* \_SB_.PCI0.LPCB.EC0_._CRS.BFFR */ + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + ^^^GFX0.CLID = 0x03 + Return (0x0F) + } + + OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, Zero) + Name (BATO, Zero) + Name (BATN, Zero) + Name (BATF, 0xC0) + Name (TMEE, Zero) + Name (TMDE, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If (((Arg0 == 0x03) && (Arg1 == One))) + { + ECOK = One + GBAS () + ECMI () + } + } + + Method (_GPE, 0, NotSerialized) // _GPE: General Purpose Events + { + Local0 = GGPE (0x02020017) + Return (Local0) + } + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = One + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = Zero + EBPL = Zero + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == One)) + { + BATF = Zero + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= One + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = Zero + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + ^^^GFX0.GHDS (Zero) + Sleep (0xC8) + } + + Method (_Q10, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x87) // Device-Specific + } + + Method (_Q11, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (^^^GFX0.DD1F, 0x86) // Device-Specific + } + + Method (_Q15, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "!!! Wireless Button pressed !!!" + If ((OSYS >= 0x07DC)) + { + Notify (WLBT, 0x80) // Status Change + } + Else + { + If (BNLS) + { + BNLS = Zero + Local0 = One + } + Else + { + BNLS = One + Local0 = Zero + } + + If ((^^^^WMID.WMIF == One)) + { + If (((WWLS == One) & (WLDS == One))) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If (((WBTS == One) & (BTDS == One))) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + Else + { + If ((WLDS == One)) + { + If (One) + { + SGOV (0x02070002, Local0) + } + Else + { + SGOV (0x01090008, Local0) + } + } + + If ((BTDS == One)) + { + If (One) + { + SGOV (0x0203000C, Local0) + } + Else + { + SGOV (0x0103000C, Local0) + } + } + } + } + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + If (SW2S) + { + ^^^^WMID.GWEV (0x03, Zero) + } + } + + PNOT () + } + } + + Method (_Q21, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((BCTF || BMNF)) + { + ^^^^WMID.GWEV (0x12, One) + } + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + BACR = Zero + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == One)) + { + PSIN = 0xFF + Sleep (One) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (One) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((ENWD == One)) + { + TMPR = One + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((CVTS == One)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == Zero)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + ^^^^WFTE.WMDE (Zero, One, Local0) + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + Method (_Q49, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If ((PVSS == One)) + { + If ((PVSE == One)) + { + ^^^^WMID.GWEV (0x14, 0xFE) + } + Else + { + ^^^^WMID.GWEV (0x14, 0xFF) + } + } + } + } + + Method (_Q4D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x00020001, Zero) + } + + Method (_Q6F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x04, Zero) + } + + Method (_Q70, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, Zero) + } + + Method (_Q71, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + SGOV (0x0204000A, One) + } + + Method (_Q80, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q82, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q82 : Temperature reachs for Turbo Mode OFF" + TMDE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q83, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Sleep (0x14) + Debug = "_Q83 : Temperature reachs for Turbo Mode ON" + TMEE = One + Notify (\_TZ.TZ01, 0x80) // Thermal Status Change + } + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == One)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == One)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = Zero + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + + Method (_Q8E, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q8F, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + If (Local0) + { + Local0-- + CPUS (Local0) + } + + CLOW = Local0 + } + + Method (_Q99, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA0, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QA1, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + } + + Method (_QE4, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local1 = Zero + Local0 = PKPS /* \PKPS */ + If ((Local0 > 0x80)) + { + Local0 -= 0x80 + While ((Local0 > 0x06)) + { + Local0 -= 0x10 + Local1 += 0x06 + } + + Local1 += Local0 + If (((Local1 >= 0x07) & (Local1 <= 0x0C))) + { + Local1 += 0x12 + } + ElseIf (((Local1 >= 0x0D) & (Local1 <= 0x12))) + { + Local1 += 0x06 + } + ElseIf (((Local1 >= 0x13) & (Local1 <= 0x18))) + { + Local1 -= 0x0C + } + ElseIf (((Local1 >= 0x19) & (Local1 <= 0x1E))) + { + Local1 -= 0x0C + } + + Stall (0x05) + Local0 = Zero + Local3 = OFDA /* \OFDA */ + While ((Local1 > One)) + { + Local2 = DerefOf (Local3 [Local0]) + Local0 += Local2 + Local1 -= One + } + + Stall (0x0F) + Local1 = DerefOf (Local3 [Local0]) + Local2 = Zero + Stall (0x0F) + Name (KPFT, Buffer (0xA0){}) + While ((Local2 < 0xA0)) + { + If ((Local1 > Zero)) + { + KPFT [Local2] = DerefOf (Local3 [Local0]) + Local0++ + Local1 -= One + } + Else + { + KPFT [Local2] = Zero + } + + Local2++ + Stall (0x05) + } + + PKMC = KPFT /* \_SB_.PCI0.LPCB.EC0_._QE4.KPFT */ + PKWD = One + } + } + + Method (_QE5, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + ^^^^WMID.GWEV (0x12, PKPS) + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMW0, 16 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + SMB0, 8 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD0, 64 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD1, 128 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD2, 192 + } + + Field (ERAM, ByteAcc, NoLock, Preserve) + { + Offset (0x04), + FLD3, 256 + } + + Mutex (MUT0, 0x00) + Mutex (MUT1, 0x00) + Mutex (MUT2, 0x00) + Method (SMRD, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x07)) + { + If ((Arg0 != 0x09)) + { + If ((Arg0 != 0x0B)) + { + If ((Arg0 != 0x47)) + { + If ((Arg0 != 0xC7)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + Else + { + If ((Arg0 == 0x07)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x47)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0xC7)) + { + Arg3 = SMB0 /* \_SB_.PCI0.LPCB.EC0_.SMB0 */ + } + + If ((Arg0 == 0x09)) + { + Arg3 = SMW0 /* \_SB_.PCI0.LPCB.EC0_.SMW0 */ + } + + If ((Arg0 == 0x0B)) + { + Local3 = BCNT /* \_SB_.PCI0.LPCB.EC0_.BCNT */ + Local2 = 0x20 + If ((Local3 > Local2)) + { + Local3 = Local2 + } + + If ((Local3 < 0x11)) + { + Local2 = FLD1 /* \_SB_.PCI0.LPCB.EC0_.FLD1 */ + } + ElseIf ((Local3 < 0x19)) + { + Local2 = FLD2 /* \_SB_.PCI0.LPCB.EC0_.FLD2 */ + } + Else + { + Local2 = FLD3 /* \_SB_.PCI0.LPCB.EC0_.FLD3 */ + } + + Local3++ + Local4 = Buffer (Local3){} + Local3-- + Local5 = Zero + Name (OEMS, Buffer (0x46){}) + ToBuffer (Local2, OEMS) /* \_SB_.PCI0.LPCB.EC0_.SMRD.OEMS */ + While ((Local3 > Local5)) + { + GBFE (OEMS, Local5, RefOf (Local6)) + PBFE (Local4, Local5, Local6) + Local5++ + } + + PBFE (Local4, Local5, Zero) + Arg3 = Local4 + } + } + + Release (MUT0) + Return (Local0) + } + + Method (SMWR, 4, NotSerialized) + { + If (!ECOK) + { + Return (0xFF) + } + + If ((Arg0 != 0x06)) + { + If ((Arg0 != 0x08)) + { + If ((Arg0 != 0x0A)) + { + If ((Arg0 != 0x46)) + { + If ((Arg0 != 0xC6)) + { + Return (0x19) + } + } + } + } + } + + Acquire (MUT0, 0xFFFF) + Local0 = 0x04 + While ((Local0 > One)) + { + If ((Arg0 == 0x06)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x46)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0xC6)) + { + SMB0 = Arg3 + } + + If ((Arg0 == 0x08)) + { + SMW0 = Arg3 + } + + If ((Arg0 == 0x0A)) + { + SMD0 = Arg3 + } + + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + While (!Local1 = (SMST & 0xBF)) + { + Sleep (0x02) + Local3++ + If ((Local3 == 0x32)) + { + SMST &= 0x40 + SMCM = Arg2 + SMAD = Arg1 + SMPR = Arg0 + Local3 = Zero + } + } + + If ((Local1 == 0x80)) + { + Local0 = Zero + } + Else + { + Local0-- + } + } + + If (Local0) + { + Local0 = (Local1 & 0x1F) + } + + Release (MUT0) + Return (Local0) + } + + Method (GSHK, 0, Serialized) + { + If ((ECOK == One)) + { + Local0 = SFHK /* \_SB_.PCI0.LPCB.EC0_.SFHK */ + } + + Return (Local0) + } + + Method (SSHK, 1, Serialized) + { + If ((ECOK == One)) + { + SFHK = Arg0 + } + } + + Method (CPUS, 1, NotSerialized) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + \_PR.CPPC = Arg0 + } + + If ((TCNT == 0x08)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + Notify (\_PR.PR04, 0x80) // Performance Capability Change + Notify (\_PR.PR05, 0x80) // Performance Capability Change + Notify (\_PR.PR06, 0x80) // Performance Capability Change + Notify (\_PR.PR07, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x04)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + Notify (\_PR.PR02, 0x80) // Performance Capability Change + Notify (\_PR.PR03, 0x80) // Performance Capability Change + } + + If ((TCNT == 0x02)) + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + Notify (\_PR.PR01, 0x80) // Performance Capability Change + } + Else + { + Notify (\_PR.PR00, 0x80) // Performance Capability Change + } + } + + Method (ECMI, 0, NotSerialized) + { + If ((ECOK == One)) + { + OSTD () + CLOW = Zero + CMAX = (MPPP - One) + ACKY = FNKY /* \FNKY */ + SASU () + If ((SMA4 == One)) + { + SMSZ = Zero + } + Else + { + SMSZ = One + } + + ULID (Zero) + } + } + + Method (SASU, 0, NotSerialized) + { + If ((ECOK == One)) + { + If (CondRefOf (\_PR.PR00._PPC)) + { + Local0 = \_PR.PR00._PPC () + } + + Local1 = (MPPP - One) + If (((SW2S == Zero) || ((SADP >= One) & ( + SADP <= 0x02)))) + { + Local0 = Zero + CPUS (Local0) + CLOW = Local0 + } + + If ((SADP == 0x03)) + { + If ((Local0 < Local1)) + { + Local0++ + CPUS (Local0) + CLOW = Local0 + } + } + } + } + + Method (RPIO, 2, NotSerialized) + { + Local0 = Zero + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + Local0 = EI03 /* \EI03 */ + } + + Return (Local0) + } + + Method (WPIO, 3, NotSerialized) + { + If ((ECOK == One)) + { + EI01 = Arg0 + EI02 = Arg1 + EI03 = Arg2 + } + } + + Method (ECMD, 3, NotSerialized) + { + If ((ECOK == One)) + { + WPIO (Arg0, Arg1, Arg2) + While (EI03) + { + Stall (0xFF) + } + + Local0 = RPIO (0xFB, Zero) + Return (Local0) + } + } + + Method (CBCD, 0, NotSerialized) + { + If ((ECOK == One)) + { + Local0 = MBDC /* \_SB_.PCI0.LPCB.EC0_.MBDC */ + Local0 &= 0xE4 + MBDC = Local0 + } + } + + Method (ULID, 1, NotSerialized) + { + If ((ECOK == One)) + { + If ((ECLS == One)) + { + Local0 = Zero + } + Else + { + Local0 = One + } + + If (IGDS) + { + If ((Arg0 == One)) + { + If ((Local0 != LIDS)) + { + If (^^^GFX0.GLID (Local0)) + { + If ((LIDS == Zero)) + { + ^^^GFX0.CLID |= 0x80000000 /* External reference */ + } + + If ((LIDS == One)) + { + ^^^GFX0.CLID |= 0x80000001 /* External reference */ + } + } + } + } + } + + LIDS = Local0 + } + } + + Method (OSTD, 0, NotSerialized) + { + If ((ECOK == One)) + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + If ((OSYS >= 0x07D0)) + { + If ((OSYS >= 0x07D9)) + { + W7OS = One + If ((OSKU == Zero)) + { + W7OS = Zero + } + } + } + Else + { + If ((OSYS == 0x03E8)) + { + RFLG = One + } + + If ((OSYS == 0x03E9)) + { + SUSE = One + } + } + } + Else + { + W7OS = Zero + SUSE = Zero + RFLG = Zero + } + } + + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "tpm.asl" +} diff --git a/src/ec/hp/it8987e/acpi/kb.asl b/src/ec/hp/it8987e/acpi/kb.asl new file mode 100644 index 0000000..bc42897 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/kb.asl @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((CHID == 0x25)) + { + Return ("*SYN326A") + } + Else + { + Return ("*SYN326A") + } + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/ec/hp/it8987e/acpi/superio.asl b/src/ec/hp/it8987e/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/ec/hp/it8987e/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/ec/hp/it8987e/acpi/tpm.asl b/src/ec/hp/it8987e/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/ec/hp/it8987e/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/ec/hp/it8987e/chip.h b/src/ec/hp/it8987e/chip.h new file mode 100644 index 0000000..1bc9949 --- /dev/null +++ b/src/ec/hp/it8987e/chip.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _EC_HP_IT8987E_CHIP_H +#define _EC_HP_IT8987E_CHIP_H + +#include <device/device.h> + +struct chip_operations; +extern struct chip_operations ec_quanta_it8987e_ops; + +struct ec_quanta_it8987e_config { +}; + +#endif /* _EC_HP_IT8987E_CHIP_H */ diff --git a/src/ec/hp/it8987e/ec.c b/src/ec/hp/it8987e/ec.c new file mode 100644 index 0000000..db6fe3c --- /dev/null +++ b/src/ec/hp/it8987e/ec.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> + +#include "ec.h" +#include "chip.h" + +/* helper functions from drivers/pc80/keyboard.c */ +static int input_buffer_empty(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF); + timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_WARNING, "EC-IT8987E Unexpected input buffer full\n"); + printk(BIOS_WARNING, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + +static int output_buffer_full(u16 status_reg) +{ + u32 timeout; + for (timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg) + & KBD_OBF) == 0); timeout--) { + udelay(1000); + } + + if (!timeout) { + printk(BIOS_INFO, "EC-IT8987E output buffer result timeout\n"); + printk(BIOS_INFO, " Status (0x%x): 0x%x\n", status_reg, inb(status_reg)); + } + return !!timeout; +} + + + +/* The IT8987E 60/64 EC registers are the same command/status IB/OB KBC pair. + * Check status from 64 port before each command. + * + * Ex. Get panel ID command C43/D77 + * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port + * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port + * Check OBF set. Then Get Data(0x03:panel ID) from 0x60 + * Different commands return may or may not respond and may have multiple + * bytes. Keep it simple for nor + */ + +u8 ec_kbc_read_ob(void) +{ + if (!output_buffer_full(KBD_STATUS)) return 0; + return inb(KBD_DATA); +} + +void ec_kbc_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(cmd, KBD_COMMAND); +} + +void ec_kbc_write_ib(u8 data) +{ + if (!input_buffer_empty(KBD_STATUS)) return; + outb(data, KBD_DATA); +} + + +/* + * These functions are for accessing the IT8987E device RAM space via 0x66/0x68 + */ + +u8 ec_read_ob(void) +{ + if (!output_buffer_full(EC_SC)) return 0; + return inb(EC_DATA); +} + +void ec_write_cmd(u8 cmd) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(cmd, EC_SC); +} + +void ec_write_ib(u8 data) +{ + if (!input_buffer_empty(EC_SC)) return; + outb(data, EC_DATA); +} + +u8 ec_read(u16 addr) +{ + ec_write_cmd(RD_EC); + ec_write_ib(addr); + return ec_read_ob(); +} + +void ec_write(u16 addr, u8 data) +{ + ec_write_cmd(WR_EC); + ec_write_ib(addr); + ec_write_ib(data); +} + +#ifndef __PRE_RAM__ + +u8 ec_it8987e_get_event(void) +{ + u8 cmd = 0; + u8 status = inb(EC_SC); + if (status & SCI_EVT) { + ec_write_cmd(QR_EC); + cmd = ec_read_ob(); + } else if (status & SMI_EVT) { + ec_kbc_write_cmd(EC_KBD_SMI_EVENT); + cmd = ec_kbc_read_ob(); + } + return cmd; +} + +void ec_it8987e_enable_wake_events(void) +{ + /* + * Set the bit in ECRAM that will enable the Lid switch as a wake source + */ + u8 reg8 = ec_read(EC_WAKE_SRC_ENABLE); + ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); +} + +#ifndef __SMM__ +static void it8987e_init(struct device *dev) +{ + if (!dev->enabled) + return; + + printk(BIOS_DEBUG, "Quanta IT8987E: Initializing keyboard.\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static struct device_operations ops = { + .init = it8987e_init, + .read_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +}; + +static struct pnp_info pnp_dev_info[] = { + { NULL, 0, 0, 0, } +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations ec_quanta_it8987e_ops = { + CHIP_NAME("QUANTA IT8987E EC") + .enable_dev = enable_dev +}; +#endif /* ! __SMM__ */ +#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/hp/it8987e/ec.h b/src/ec/hp/it8987e/ec.h new file mode 100644 index 0000000..f87b2c0 --- /dev/null +++ b/src/ec/hp/it8987e/ec.h @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Modified by Matt Parnell <mparnell(a)gmail.com> to support ITL 8987E + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * EC communication interface for QUANTA IT8987E Embedded Controller. + */ + +#ifndef _EC_HP_IT8987E_EC_H +#define _EC_HP_IT8987E_EC_H + +#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */ +#define EC_IO_HIGH EC_IO + 1 +#define EC_IO_LOW EC_IO + 2 +#define EC_IO_DATA EC_IO + 3 + +/* Wait 400ms for keyboard controller ansswers */ +#define KBC_TIMEOUT_IN_MS 400 + +// 60h/64h Command Interface +#define KBD_DATA 0x60 +#define KBD_COMMAND 0x64 +#define KBD_STATUS 0x64 +#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec) +#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host) + +#define EC_KBD_SMI_EVENT 0xCD +#define EC_KBD_CMD_UNMUTE 0xE8 +#define EC_KBD_CMD_MUTE 0xE9 + +u8 ec_kbc_read_ob(void); +void ec_kbc_write_cmd(u8 cmd); +void ec_kbc_write_ib(u8 data); + +// 62h/66h Command Interface +#define EC_DATA 0x62 +#define EC_SC 0x66 // Status & Control Register +#define SMI_EVT (1 << 6) // 1: SMI event was triggered +#define SCI_EVT (1 << 5) // 1: SCI event was triggered + +// EC Commands (defined in ec_function_spec v3.12) +#define RD_EC 0x80 +#define WR_EC 0x81 +#define QR_EC 0x84 + +#define EC_CMD_EXIT_BOOT_BLOCK 0x85 +#define EC_CMD_NOTIFY_ACPI_ENTER 0x86 +#define EC_CMD_NOTIFY_ACPI_EXIT 0x87 +#define EC_CMD_WARM_RESET 0x8C + +// ECRAM Offsets +#define EC_PERIPH_CNTL_3 0x0D +#define EC_USB_S3_EN 0x26 +#define EC_PERIPH_STAT_3 0x35 +#define EC_THERM_0 0x78 +#define EC_WAKE_SRC_ENABLE 0xBF +#define EC_FW_VER 0xE8 // 2 Bytes +#define EC_IF_MIN_VER 0xEB +#define EC_STATUS_REG 0xEC +#define EC_IF_MAJ_VER 0xEF +#define EC_MBAT_STATUS 0x0138 + + +// EC 0.83b added status bits: +// BIT0=EC in RO mode +// BIT1=Recovery Key Sequence Detected +#define EC_IN_RO_MODE 0x1 +#define EC_IN_RECOVERY_MODE 0x3 + +// EC 0.86a added enable bit: +#define EC_LID_WAKE_ENABLE 0x4 + +u8 ec_read_ob(void); +void ec_write_cmd(u8 cmd); +void ec_write_ib(u8 data); + +u8 ec_read(u16 addr); +void ec_write(u16 addr, u8 data); +u8 ec_it8987e_get_event(void); +void ec_it8987e_enable_wake_events(void); + +#endif /* _EC_HP_IT8987E_EC_H */ diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig new file mode 100644 index 0000000..00542d7 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig @@ -0,0 +1,59 @@ +config BOARD_HP_SPECTRE_AE000 + select SYSTEM_TYPE_LAPTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select SOC_INTEL_KABYLAKE + select MAINBOARD_USES_FSP2_0 + select SPD_READ_BY_WORD + select MAINBOARD_HAS_LPC_TPM + select NO_POST # This platform does not have any way to see POST codes + +if BOARD_HP_SPECTRE_AE000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_VENDOR + string + default "HP" + +config MAINBOARD_FAMILY + string + default "HP Spectre x360" + +config MAINBOARD_PART_NUMBER + string + default "13t-ae000" + +config MAINBOARD_DIR + string + default "hp/hp_spectre_x360_13_convertible" + +config DEVICETREE + string + default "devicetree.cb" + +config FMDFILE + string + default "" + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_ID + string + default "8086,0406" + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name new file mode 100644 index 0000000..9f089a5 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_HP_SPECTRE_AE000 + bool "Spectre x360 13t-ae000" diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc new file mode 100644 index 0000000..35f0f6c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl new file mode 100644 index 0000000..489bdcd --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ac.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (ADP1) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.SW2S + } + Else + { + Local0 = 1 + } + + Return (Local0) + } + + Method (_PCL, 0, NotSerialized) // _PCL: Power Consumer List + { + Return (_SB) /* \_SB_ */ + } +} + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D") /* Lid Device */) // _HID: Hardware ID + Method (_LID, 0, NotSerialized) // _LID: Lid Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.ECLS == 1)) + { + Local0 = 0 + } + Else + { + Local0 = 1 + } + } + Else + { + Local0 = 1 + } + + /* \_SB_.PCI0.LPCB.EC0.ULID (1) */ + Return (Local0) + } +} + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C") /* Power Button Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl new file mode 100644 index 0000000..94ce92c --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/battery.asl @@ -0,0 +1,252 @@ +/* +* This file is part of the coreboot project. +* +* Copyright (C) 2013 Google Inc. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; version 2 of +* the License. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +Device (BAT0) +{ + Name (FRST, 1) + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (PBIF, Package (0x0D) + { + 1, + 0xFFFFFFFF, + 0xFFFFFFFF, + 1, + 0xFFFFFFFF, + 0xFA, + 0x96, + 0x0A, + 0x19, + "BAT0", + " ", + " ", + " " + }) + Name (PBST, Package (0x04) + { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x2710 + }) + Name (BAST, 0) + Name (B1ST, 0x0F) + Name (B1WT, 0) + Name (FABL, 0xFFFFFFFF) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + B1ST = 0x1F + } + Else + { + B1ST = 0x0F + } + } + Else + { + B1ST = 0x0F + } + + Return (B1ST) /* \_SB_.BAT0.B1ST */ + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBI () + } + Else + { + IVBI () + } + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If (\_SB_.PCI0.LPCB.EC0.MBTS) + { + UPBS () + } + Else + { + IVBS () + } + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } + + Method (UPBI, 0, NotSerialized) + { + Local5 = \_SB_.PCI0.LPCB.EC0.BFCC /* \_SB_.PCI0.LPCB.EC0_.BFCC */ + If ((Local5 && !(Local5 & 0x8000))) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + PBIF [1] = Local5 + PBIF [0x02] = Local5 + Local2 = (Local5 / 0x64) + Local2 += 1 + If ((\_SB_.PCI0.LPCB.EC0.BADC < 0x0C80)) + { + Local4 = (Local2 * 0x0E) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x09) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0B) + } + ElseIf ((SMA4 == 1)) + { + Local4 = (Local2 * 0x0A) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x05) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x08) + } + Else + { + Local4 = (Local2 * 0x0C) + PBIF [0x05] = (Local4 + 0x02) + Local4 = (Local2 * 0x07) + PBIF [0x06] = (Local4 + 0x02) + Local4 = (Local2 * 0x0A) + } + + FABL = (Local4 + 0x02) + } + + Local0 = \_SB_.PCI0.LPCB.EC0.BVLB /* \_SB_.PCI0.LPCB.EC0_.BVLB */ + Local1 = \_SB_.PCI0.LPCB.EC0.BVHB /* \_SB_.PCI0.LPCB.EC0_.BVHB */ + Local1 <<= 0x08 + Local0 |= Local1 + PBIF [0x04] = Local0 + Sleep (0x32) + PBIF [0x0B] = "LION" + PBIF [0x09] = "Primary" + UPUM () + PBIF [0] = 1 + } + + Method (UPUM, 0, NotSerialized) + { + Local0 = Buffer (0x0A) + { + /* 0000 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00 // .. + } + Local6 = Buffer (0x05) + { + 0x36, 0x35, 0x35, 0x33, 0x35 // 65535 + } + Local7 = Buffer (0x05) + { + 0x31, 0x32, 0x33, 0x32, 0x31 // 12321 + } + PBIF [0x0C] = "HP" + } + + Method (UPBS, 0, NotSerialized) + { + If ((BRTM == 1)) + { + Local0 = \_SB_.PCI0.LPCB.EC0.MCUR /* \_SB_.PCI0.LPCB.EC0_.MCUR */ + If ((Local0 & 0x8000)) + { + If ((Local0 == 0xFFFF)) + { + PBST [1] = 0xFFFFFFFF + } + Else + { + Local1 = ~Local0 + Local1++ + Local3 = (Local1 & 0xFFFF) + PBST [1] = Local3 + } + } + Else + { + PBST [1] = Local0 + } + } + Else + { + PBST [1] = 0xFFFFFFFF + } + + Local5 = \_SB_.PCI0.LPCB.EC0.MBRM /* \_SB_.PCI0.LPCB.EC0_.MBRM */ + If (!(Local5 & 0x8000)) + { + Local5 >>= 0x05 + Local5 <<= 0x05 + If ((Local5 != DerefOf (PBST [0x02]))) + { + PBST [0x02] = Local5 + } + } + + If ((!\_SB_.PCI0.LPCB.EC0.SW2S && (\_SB_.PCI0.LPCB.EC0.BACR == 1))) + { + PBST [0x02] = FABL /* \_SB_.BAT0.FABL */ + } + + PBST [0x03] = \_SB_.PCI0.LPCB.EC0.MBCV /* \_SB_.PCI0.LPCB.EC0_.MBCV */ + PBST [0] = \_SB_.PCI0.LPCB.EC0.MBST /* \_SB_.PCI0.LPCB.EC0_.MBST */ + } + + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = "Bad" + PBIF [0x0A] = "Bad" + PBIF [0x0B] = "Bad" + PBIF [0x0C] = "Bad" + } + + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl new file mode 100644 index 0000000..a417560 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/ec.asl @@ -0,0 +1,393 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_UID, 1) // _UID: Unique ID + Name (_GPE, 0x17) + Name (PHOT, 1) + + Name (_CRS, ResourceTemplate () { + IO (Decode16, 0x62, 0x62, 0, 1) + IO (Decode16, 0x66, 0x66, 0, 1) + }) + + OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) + Field (ERAM, ByteAcc, NoLock, Preserve) + { + SMPR, 8, + SMST, 8, + SMAD, 8, + SMCM, 8, + SMD0, 256, + BCNT, 8, + SMAA, 8, + Offset (0x40), + SW2S, 1, + , 2, + ACCC, 1, + TRPM, 1, + Offset (0x41), + W7OS, 1, + QWOS, 1, + , 1, + SUSE, 1, + RFLG, 1, + Offset (0x43), + , 1, + , 1, + ACPS, 1, + ACKY, 1, + GFXT, 1, + Offset (0x44), + , 7, + DSMB, 1, + Offset (0x47), + TNT2, 8, + TNT3, 8, + Offset (0x4C), + STRM, 8, + Offset (0x4E), + LIDE, 1, + Offset (0x4F), + ACID, 8, + , 2, + PTHM, 1, + , 1, + BSEV, 1, + DPTL, 1, + Offset (0x52), + ECLS, 1, + Offset (0x55), + EC45, 8, + Offset (0x58), + RTMP, 8, + TNT1, 8, + Offset (0x5F), + , 1, + Offset (0x61), + SHPM, 8, + Offset (0x67), + , 1, + , 1, + GC6R, 1, + IGC6, 1, + , 2, + PVSE, 1, + PVSS, 1, + , 3, + PLGS, 1, + , 3, + TPDF, 1, + , 4, + BCTF, 1, + BMNF, 1, + BTVD, 1, + BF10, 1, + Offset (0x6C), + GWKR, 8, + Offset (0x70), + BADC, 16, + BFCC, 16, + BVLB, 8, + BVHB, 8, + BDVO, 8, + Offset (0x7F), + ECTB, 1, + Offset (0x82), + MBST, 8, + MCUR, 16, + MBRM, 16, + MBCV, 16, + Offset (0x8B), + LEDM, 3, + Offset (0x8D), + , 5, + MBFC, 1, + Offset (0x92), + SPSV, 8, + Offset (0x94), + GSSU, 1, + GSMS, 1, + Offset (0x95), + MMST, 4, + DMST, 4, + Offset (0xA0), + QBHK, 8, + Offset (0xA2), + QBBB, 8, + Offset (0xA4), + MBTS, 1, + , 6, + BACR, 1, + Offset (0xA6), + MBDC, 8, + Offset (0xA8), + ENWD, 1, + TMPR, 1, + Offset (0xAA), + , 1, + SMSZ, 1, + , 5, + RCDS, 1, + Offset (0xAD), + SADP, 8, + Offset (0xB2), + RPM1, 8, + RPM2, 8, + Offset (0xBA), + CLOW, 8, + CMAX, 8, + Offset (0xC1), + DPPC, 8, + Offset (0xC6), + , 1, + CVTS, 1, + Offset (0xCE), + NVDX, 8, + ECDX, 8, + EBPL, 1, + Offset (0xD2), + , 7, + DLYE, 1, + Offset (0xD4), + PSHD, 8, + PSLD, 8, + DBPL, 8, + STSP, 8, + Offset (0xDA), + PSIN, 8, + PSKB, 1, + PSTP, 1, + , 1, + PWOL, 1, + RTCE, 1, + Offset (0xE0), + DLYT, 8, + DLY2, 8, + Offset (0xE6), + SFHK, 8, + Offset (0xE9), + DTMT, 8, + PL12, 8, + ETMT, 8, + Offset (0xF2), + ZPDD, 1, + , 6, + ENPA, 1, + Offset (0xF4), + SFAN, 8, + Offset (0xF9), + , 7, + FTHM, 1 + } + + Name (ECOK, 0) + Name (BATO, 0) + Name (BATN, 0) + Name (BATF, 0xC0) + Name (TMEE, 0) + Name (TMDE, 0) + + Method (BPOL, 1, NotSerialized) + { + DBPL = Arg0 + EBPL = 1 + } + + Method (BPOM, 0, NotSerialized) + { + DBPL = 0 + EBPL = 0 + } + + Method (GBAS, 0, NotSerialized) + { + If ((ECOK == 1)) + { + BATF = 0 + Local0 = MBTS /* \_SB_.PCI0.LPCB.EC0_.MBTS */ + Local1 = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + Local0 <<= 0x06 + Local1 <<= 1 + If (((BATO & 0x40) != Local0)) + { + BATF |= 0x40 + } + + If (((BATO & 0x02) != Local1)) + { + BATF |= 0x02 + } + + BATO = 0 + BATO = (Local0 | Local1) + } + } + + Method (_Q09, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + BPOM () + GBAS () + Notify (BAT0, 0x80) // Status Change + Notify (BAT0, 0x81) // Information Change + Notify (ADP1, 0x80) // Status Change + } + + Method (_Q0D, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Debug = "_Q0D : Switch Display (Fn+F4)" + /*\_SB_.PCI0.GFX0.GHDS (0)*/ /*Todo: fixme? where is this guy defined? */ + Sleep (0xC8) + } + + Method (_Q20, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + GBAS () + If ((0x40 & BATF)) + { + Notify (BAT0, 0x81) // Information Change + } + + Notify (BAT0, 0x80) // Status Change + If ((0x02 & BATF)) + { + Notify (ADP1, 0x80) // Status Change + PWRS = SW2S /* \_SB_.PCI0.LPCB.EC0_.SW2S */ + } + + PNOT () + } + } + + Method (_Q22, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + BACR = 0 + Notify (BAT0, 0x80) // Status Change + } + } + + Method (_Q2A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (BAT0, 0x81) // Information Change + Notify (BAT0, 0x80) // Status Change + } + + Method (_Q33, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Local0 = ^^RTC.RTMN /* \_SB_.PCI0.LPCB.RTC_.RTMN */ + FromBCD (Local0, Local0) + Local1 = ^^RTC.RTHR /* \_SB_.PCI0.LPCB.RTC_.RTHR */ + FromBCD (Local1, Local1) + Local2 = ^^RTC.RTDY /* \_SB_.PCI0.LPCB.RTC_.RTDY */ + Local3 = ^^RTC.RTSE /* \_SB_.PCI0.LPCB.RTC_.RTSE */ + FromBCD (Local3, Local3) + If ((ECOK == 1)) + { + PSIN = 0xFF + Sleep (1) + PSLD = Local0 + PSHD = Local1 + PSIN = 0x1C + Sleep (1) + PSLD = Local2 + PSHD = Local3 + PSIN = 0x1D + } + } + + Method (_Q34, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((ENWD == 1)) + { + TMPR = 1 + } + } + } + + Method (_Q46, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If ((CVTS == 1)) + { + Local0 = 0x03 + Local0 <<= 0x10 + Local0 |= 0x03 + Notify (VBPA, 0xCC) // Hardware-Specific + } + + If ((CVTS == 0)) + { + Local0 = 0x02 + Local0 <<= 0x10 + Local0 |= 0x02 + Notify (VBPA, 0xCD) // Hardware-Specific + } + } + } + + /* _Q80 _Q82 _Q83 thermal zone methods removed */ + + Method (_Q84, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x02 + } + } + + Method (_Q85, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + Notify (B0D4, 0x90) // Device-Specific + } + + Method (_Q86, 0, Serialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((PHOT == 1)) + { + PHOT = 0x03 + } + } + + Method (_Q8A, 0, NotSerialized) // _Qxx: EC Query, xx=0x00-0xFF + { + If ((ECOK == 1)) + { + If (LIDE) + { + Debug = "_Q8A : LID Switch Event" + LIDE = 0 + Sleep (0x14) + Notify (LID0, 0x80) // Status Change + } + } + } + +/* TODO: revisit _Q8E _Q8F and wtf is _QE4 for? ? */ + +#include "ac.asl" +#include "battery.asl" +#include "kb.asl" +#include "mainboard.asl" +/*#include "tpm.asl"*/ +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl new file mode 100644 index 0000000..296cdba --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/kb.asl @@ -0,0 +1,159 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (PS2K) +{ + Name (_CID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _CID: Compatible ID + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If ((OSYS >= 0x07DC)) + { + Return ("HPQ8001") + } + Else + { + Return ("PNP0303") + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQ (Edge, ActiveHigh, Exclusive, ) + {1} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + FixedIO ( + 0x0060, // Address + 0x01, // Length + ) + FixedIO ( + 0x0064, // Address + 0x01, // Length + ) + IRQNoFlags () + {1} + } + EndDependentFn () + }) + + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + KBWK = Arg0 + } +} + +Device (PS2M) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + Return ("*SYN326A") + } + + Method (_CID, 0, NotSerialized) // _CID: Compatible ID + { + Return (Package (0x03) + { + 0x001E2E4F, + 0x02002E4F, + 0x130FD041 + }) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQ (Edge, ActiveHigh, Exclusive, ) + {12} + }) + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + StartDependentFn (0x00, 0x00) + { + IRQNoFlags () + {12} + } + EndDependentFn () + }) + Method (_PRW, 0, NotSerialized) // _PRW: Power Resources for Wake + { + If (One) + { + Return (Package (0x02) + { + 0x3D, + 0x03 + }) + } + Else + { + Return (Package (0x02) + { + 0x1F, + 0x03 + }) + } + } + + Method (_PSW, 1, NotSerialized) // _PSW: Power State Wake + { + TPWK = Arg0 + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl new file mode 100644 index 0000000..3c7189b --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/mainboard.asl @@ -0,0 +1,282 @@ + /* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope (EC0) + +Device (RTC) +{ + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Scope (\_SB.PCI0.LPCB.RTC) +{ + OperationRegion (CMS0, SystemCMOS, 0, 0x40) + Field (CMS0, ByteAcc, NoLock, Preserve) + { + RTSE, 8, + RTSA, 8, + RTMN, 8, + RTMA, 8, + RTHR, 8, + RTHA, 8, + RTDY, 8, + RTDE, 8 + } +} + +Device (VBPA) +{ + Name (_HID, "INT33D6" /* Intel Virtual Buttons Device */) // _HID: Hardware ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0F) + } + Else + { + Return (0) + } + } + + Name (VBST, 0) + Method (VBDL, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + } + + Method (VGBS, 0, NotSerialized) + { + If ((\_SB_.PCI0.LPCB.EC0.ECOK == 1)) + { + If ((\_SB_.PCI0.LPCB.EC0.CVTS == 0)) + { + VBST = 0x40 + } + Else + { + VBST = 0 + } + } + + Return (VBST) /* \_SB_.VBPA.VBST */ + } +} + +Device (CIND) +{ + Name (_HID, "INT33D3" /* Intel GPIO Buttons */) // _HID: Hardware ID + Name (_CID, "PNP0C60" /* Display Sensor Device */) // _CID: Compatible ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((OSYS >= 0x07DD)) + { + Return (0x0B) + } + Else + { + Return (0) + } + } +} + +Device (GFX0) +{ + Name (_ADR, 0x00020000) // _ADR: Address +} + +Device (B0D4) +{ +Method (PCIC, 1, Serialized) + { + If ((ECR1 == One)) + { + If ((Arg0 == PCIG)) + { + Return (One) + } + } + + Return (Zero) + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If (PCIC (Arg0)) + { + Return (PCID (Arg0, Arg1, Arg2, Arg3)) + } + + Return (Buffer (1) + { + 0x00 // . + }) + } + + Name (_ADR, 0x00040000) // _ADR: Address +} + +Device (ISP0) +{ + Name (_ADR, 0x00050000) // _ADR: Address +} + +Scope (\) +{ + Name (PCIG, ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */) + Name (KBWK, 0) + Name (TPWK, 0) + + Field (GNVS, AnyAcc, Lock, Preserve) + { + ECR1, 8 + } + + OperationRegion (EXBU, SystemMemory, 0x2F822018, 0x3008) + Field (EXBU, AnyAcc, Lock, Preserve) + { + AEAX, 32, + AEBX, 32, + AECX, 32, + AEDX, 32, + AREF, 32, + DAB0, 8, + DAB1, 8, + DAB2, 8, + DAB3, 8, + WBUF, 1024, + TJMX, 8, + FNKY, 8, + CAME, 8, + VTDT, 8, + DPMD, 8, + WLVD, 16, + WLDD, 16, + WLSV, 16, + WLSS, 16, + BTVD, 16, + BTDD, 16, + WWVD, 16, + WWDD, 16, + WMVD, 16, + WMDD, 16, + GPVD, 16, + GPDD, 16, + SMA4, 8, + PMEE, 8, + WSD0, 8, + WSD1, 8, + WSD2, 8, + WSD3, 8, + WAR7, 8, + DBCM, 8, + CPUP, 64, + GPUP, 32, + SYSP, 64, + FANP, 32, + BATP, 32, + HDDP, 32, + CPUT, 8, + GPUT, 8, + SYST, 8, + FANT, 8, + BATT, 8, + TTST, 8, + RTCF, 8, + BODD, 8, + BRTM, 8, + NOCD, 8, + PWVD, 16, + PWDD, 16, + PWSV, 16, + PWSS, 16, + Offset (0x400), + SBUF, 2048 + } + + Method (PCID, 4, Serialized) + { + If ((Arg0 == PCIG)) + { + If ((Arg1 >= 0x03)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0x01, 0x03 // .. + }) + } + + If ((Arg2 == 0x08)) + { + Return (One) + } + + If ((Arg2 == 0x09)) + { + Return (Package (0x05) + { + 0xC350, + Ones, + Ones, + 0xC350, + Ones + }) + } + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl new file mode 100644 index 0000000..e912e04 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/superio.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Scope is \_SB.PCI0.LPCB + +Device (SIO) +{ + Name (_HID, EisaId("PNP0A05")) + Name (_UID, 0) + Name (_ADR, 0) + +#ifdef SIO_EC_ENABLE_PS2K + Device (PS2K) // Keyboard + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0303")) + Name (_CID, EISAID("PNP030B")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {1} + } + EndDependentFn () + }) + } +#endif + +#ifdef SIO_ENABLE_PS2M + Device (PS2M) // Mouse + { + Name (_HID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif + +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl new file mode 100644 index 0000000..d24d05f --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi/tpm.asl @@ -0,0 +1,446 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (_SB.TPM) +{ + Method (_HID, 0, NotSerialized) // _HID: Hardware ID + { + If (TCMF) + { + Return (0x01013469) + } + ElseIf ((TTDP == Zero)) + { + Return (0x310CD041) + } + Else + { + Return ("MSFT0101") + } + } + + Method (_STR, 0, NotSerialized) // _STR: Description String + { + If ((TTDP == Zero)) + { + Return (Unicode ("TPM 1.2 Device")) + } + Else + { + Return (Unicode ("TPM 2.0 Device")) + } + } + + Name (_UID, One) // _UID: Unique ID + Name (CRST, ResourceTemplate () + { + Memory32Fixed (ReadOnly, + 0x00000000, // Address Base + 0x00001000, // Address Length + _Y31) + Memory32Fixed (ReadOnly, + 0xFED70000, // Address Base + 0x00001000, // Address Length + _Y32) + }) + Name (CRSD, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y33) + }) + Name (CRSI, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + _Y34) + }) + Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings + { + If ((AMDT == One)) + { + CreateDWordField (CRST, \_SB.TPM._Y31._BAS, MTFB) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y31._LEN, LTFB) // _LEN: Length + MTFB = TPMB /* \TPMB */ + LTFB = 0x1000 + CreateDWordField (CRST, \_SB.TPM._Y32._BAS, MTFC) // _BAS: Base Address + CreateDWordField (CRST, \_SB.TPM._Y32._LEN, LTFC) // _LEN: Length + MTFC = TPMC /* \TPMC */ + LTFC = 0x1000 + Return (CRST) /* \_SB_.TPM_.CRST */ + } + Else + { + If ((DTPT == One)) + { + CreateDWordField (CRSD, \_SB.TPM._Y33._BAS, MTFE) // _BAS: Base Address + CreateDWordField (CRSD, \_SB.TPM._Y33._LEN, LTFE) // _LEN: Length + MTFE = 0xFED40000 + LTFE = 0x0880 + Return (CRSD) /* \_SB_.TPM_.CRSD */ + } + ElseIf ((TTPF == One)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFD) // _BAS: Base Address + CreateDWordField (CRSI, \_SB.TPM._Y34._LEN, LTFD) // _LEN: Length + MTFD = 0xFED40000 + LTFD = 0x5000 + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + ElseIf ((TTPF == Zero)) + { + CreateDWordField (CRSI, \_SB.TPM._Y34._BAS, MTFF) // _BAS: Base Address + MTFF = TPMM /* \TPMM */ + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + MTFE = Zero + LTFE = Zero + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + Return (CRSI) /* \_SB_.TPM_.CRSI */ + } + + OperationRegion (TMMB, SystemMemory, 0xFED40000, 0x5000) + Field (TMMB, ByteAcc, Lock, Preserve) + { + Offset (0x04), + LCST, 32, + Offset (0x40), + CREQ, 32, + CSTS, 32, + Offset (0x4C), + SCMD, 32 + } + + OperationRegion (CRBD, SystemMemory, TPMM, 0x48) + Field (CRBD, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + HERR, 32, + Offset (0x40), + HCMD, 32, + HSTS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((TTDP == Zero)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + ElseIf ((TTDP == One)) + { + If (TPMF) + { + Return (0x0F) + } + + Return (Zero) + } + + Return (Zero) + } + + Method (STRT, 3, Serialized) + { + OperationRegion (TPMR, SystemMemory, FTPM, 0x1000) + Field (TPMR, AnyAcc, NoLock, Preserve) + { + Offset (0x04), + FERR, 32, + Offset (0x0C), + BEGN, 32 + } + + Name (TIMR, Zero) + If ((ToInteger (Arg0) != Zero)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + TIMR = Zero + If ((AMDT == One)) + { + While (((BEGN == One) && (TIMR < 0x0200))) + { + If ((BEGN == One)) + { + Sleep (One) + TIMR++ + } + } + } + ElseIf ((((HSTS & 0x02) | (HSTS & One) + ) == 0x03)) + { + HCMD = One + } + Else + { + FERR = One + BEGN = Zero + } + + Return (Zero) + } + + } + + Return (One) + } + + Method (CRYF, 3, Serialized) + { + If ((ToInteger (Arg0) != One)){} + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + Name (TPMV, Package (0x02) + { + One, + Package (0x02) + { + One, + 0x20 + } + }) + If ((_STA () == Zero)) + { + Return (Package (0x01) + { + Zero + }) + } + + Return (TPMV) /* \_SB_.TPM_.CRYF.TPMV */ + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + } +} + + + +Scope (_SB.TPM) +{ + OperationRegion (TSMI, SystemIO, SMIA, 0x02) + Field (TSMI, WordAcc, NoLock, Preserve) + { + SMI, 16 + } + + OperationRegion (ATNV, SystemMemory, PPIM, PPIL) + Field (ATNV, AnyAcc, NoLock, Preserve) + { + RQST, 32, + RCNT, 32, + ERRO, 32, + FLAG, 32, + MISC, 32, + OPTN, 32, + SRSP, 32 + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + Case (One) + { + If ((PPIV == Zero)) + { + Return ("1.2") + } + Else + { + Return ("1.3") + } + } + Case (0x02) + { + RQST = DerefOf (Arg3 [Zero]) + SRSP = Zero + FLAG = 0x02 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x03) + { + Name (PPI1, Package (0x02) + { + Zero, + Zero + }) + PPI1 [One] = RQST /* \_SB_.TPM_.RQST */ + Return (PPI1) /* \_SB_.TPM_._DSM.PPI1 */ + } + Case (0x04) + { + Return (TRST) /* \TRST */ + } + Case (0x05) + { + Name (PPI2, Package (0x03) + { + Zero, + Zero, + Zero + }) + SRSP = Zero + FLAG = 0x05 + SMI = OFST /* \OFST */ + PPI2 [One] = RCNT /* \_SB_.TPM_.RCNT */ + PPI2 [0x02] = ERRO /* \_SB_.TPM_.ERRO */ + Return (PPI2) /* \_SB_.TPM_._DSM.PPI2 */ + } + Case (0x06) + { + Return (0x03) + } + Case (0x07) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x07 + OPTN = Zero + If ((RQST == 0x17)) + { + ToInteger (DerefOf (Arg3 [One]), OPTN) /* \_SB_.TPM_.OPTN */ + } + + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Case (0x08) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x08 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + ElseIf ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + Case (One) + { + RQST = DerefOf (Arg3 [Zero]) + FLAG = 0x09 + TMF1 = OFST /* \OFST */ + SRSP = Zero + SMI = TMF1 /* \TMF1 */ + Return (SRSP) /* \_SB_.TPM_.SRSP */ + } + Default + { + } + + } + } + + If ((Arg0 == ToUUID ("cf8e16a5-c1e8-4e25-b712-4f54a96702c8"))) + { + Return (CRYF (Arg1, Arg2, Arg3)) + } + + If ((Arg0 == ToUUID ("6bbf6cab-5463-4714-b7cd-f0203c0368d4"))) + { + Return (STRT (Arg1, Arg2, Arg3)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Method (TPTS, 1, Serialized) + { + Switch (ToInteger (Arg0)) + { + Case (0x04) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + Case (0x05) + { + RQST = Zero + FLAG = 0x09 + SRSP = Zero + SMI = OFST /* \OFST */ + } + + } + } +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/acpi_tables.c diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt new file mode 100644 index 0000000..62be952 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/board_info.txt @@ -0,0 +1,10 @@ +Vendor name: HP +Board name: Spectre 13t-ae000 +Board serial: DAOX33MBAFO +Board URL: https://support.hp.com/us-en/product/HP-Spectre-13-ae000-x360-Convertible-P… +Category: laptop +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2017 diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb new file mode 100644 index 0000000..2bf6b15 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/devicetree.cb @@ -0,0 +1,221 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # Set the Thermal Control Circuit (TCC) activaction value to 95C + # even though FSP integration guide says to set it to 100C for SKL-U + # (offset at 0), because when the TCC activates at 100C, the CPU + # will have already shut itself down from overheating protection. + register "tcc_offset" = "5" # TCC of 95C + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + +# these are probably very wrong + # Enable EC Port 0x68/0x6C + register "gen1_dec" = "0x00040069" + + # EC range is 0x800-0x9ff + register "gen2_dec" = "0x00fc0901" + + # EC range is 0x1610-0x161F + register "gen3_dec" = "0x0001C1611" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "0" # do we actually need this with only nvme? + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "0" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "0" + register "SaGv" = "3" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #| AC LoadLine | 15 mOhm | 5.7 mOhm | 5.2 mOhm | 5.2 mOhm | + #| DC LoadLine | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm | 4.2 mOhm | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(7), + .voltage_limit = 1520, + .ac_loadline = 1500, + .dc_loadline = 1430, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(34), + .voltage_limit = 1520, + .ac_loadline = 570, + .dc_loadline = 483, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 1, + .psi4enable = 1, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(35), + .voltage_limit = 1520, + .ac_loadline = 520, + .dc_loadline = 420, + }" + + # Enable Root Ports 5 and 9 + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[8]" = "1" + + # NVMe for port 9 settings + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "1" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieRpClkSrcNumber[8]" = "1" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port Left + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)" # Type-C Port + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # UHD Graphics 620 + device pci 04.0 on end # Thermal Subsystem DSP + device pci 13.0 on end # Intel Sensor Hub + device pci 14.0 on end # USB 3 Controller + device pci 14.2 on end # Thermal Subsystem DSP + device pci 15.0 on end # I2C Controller + device pci 1c.0 on end # PCIe Root Port 1 + device pci 1c.1 on end # PCIe Root Port 2 + device pci 1c.4 on end # PCIe Root Port 5 + device pci 1d.0 on end # PCIe Root Port 9 + device pci 1e.0 off end # UART + device pci 1e.2 off end # SPI + device pci 1f.0 on end # ISA Bridge + device pci 1f.2 on end # Memory Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + end +end diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl new file mode 100644 index 0000000..d36c960 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x01072009 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h new file mode 100644 index 0000000..42a6287 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/gpio.h @@ -0,0 +1,202 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Matt Parnell <mparnell(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* ------- GPIO group GPP_A ------- */ +/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x18), +/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c19), +/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c1a), +/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c1b), +/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c1c), +/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x1d), +/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x82080102, 0x1f), +/* CLKRUN# */_PAD_CFG_STRUCT(GPP_A8, 0x44000702, 0x20), +/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1021), +/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1022), +/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000300, 0x23), +/* ISH_GP6 */_PAD_CFG_STRUCT(GPP_A12, 0x44000b02, 0x24), +/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x25), +/* GPIO */_PAD_CFG_STRUCT(GPP_A14, 0x44000300, 0x26), +/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3027), +/* GPIO */_PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x28), +/* GPIO */_PAD_CFG_STRUCT(GPP_A17, 0x44000100, 0x29), +/* ISH_GP0 */_PAD_CFG_STRUCT(GPP_A18, 0x44000700, 0x2a), +/* ISH_GP1 */_PAD_CFG_STRUCT(GPP_A19, 0x44000700, 0x2b), +/* ISH_GP2 */_PAD_CFG_STRUCT(GPP_A20, 0x44000700, 0x2c), +/* ISH_GP3 */_PAD_CFG_STRUCT(GPP_A21, 0x44000700, 0x2d), +/* ISH_GP4 */_PAD_CFG_STRUCT(GPP_A22, 0x44000700, 0x2e), +/* ISH_GP5 */_PAD_CFG_STRUCT(GPP_A23, 0x44000502, 0x3f), +/* ------- GPIO Group GPP_B -------*/ +/* GPIO */_PAD_CFG_STRUCT(GPP_B0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x34), +/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x36), +/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x38), +/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000702, 0x39), +/* SRCCLKREQ5# */_PAD_CFG_STRUCT(GPP_B10, 0x44000700, 0x3a), +/* GPIO */_PAD_CFG_STRUCT(GPP_B11, 0x44000300, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_B12, 0x44000300, 0x3c), +/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x3d), +/* SPKR */_PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x103e), +/* GSPI0_CS# */_PAD_CFG_STRUCT(GPP_B15, 0x44000700, 0x3f), +/* GSPI0_CLK */_PAD_CFG_STRUCT(GPP_B16, 0x84000700, 0x40), +/* GSPI0_MISO */_PAD_CFG_STRUCT(GPP_B17, 0x44000700, 0x41), +/* GSPI0_MOSI */_PAD_CFG_STRUCT(GPP_B18, 0x84000700, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_B20, 0x44000300, 0x1044), +/* GPIO */_PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x1045), +/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1046), +/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_C ------- */ +/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x48), +/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1049), +/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x104a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C3, 0x44000201, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C4, 0x44000201, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x4d), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), +/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), +/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000700, 0x50), +/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x51), +/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x52), +/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000700, 0x53), +/* GPIO */_PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x54), +/* GPIO */_PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x55), +/* GPIO */_PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x57), +/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x58), +/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x59), +/* GPIO */_PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x5b), +/* GPIO */_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x5c), +/* GPIO */_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x5d), +/* GPIO */_PAD_CFG_STRUCT(GPP_C22, 0x82880102, 0x105e), +/* GPIO */_PAD_CFG_STRUCT(GPP_C23, 0x80880102, 0x5f), +/* ------- GPIO Group GPP_D ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x60), +/* GPIO */_PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x61), +/* GPIO */_PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x62), +/* GPIO */_PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x63), +/* GPIO */_PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x64), +/* ISH_I2C0_SDA */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x65), +/* ISH_I2C0_SCL */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x66), +/* ISH_I2C1_SDA */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x67), +/* ISH_I2C1_SCL */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x68), +/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x82000102, 0x69), +/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000200, 0x6a), +/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x6b), +/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000200, 0x6c), +/* GPIO */_PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x6d), +/* GPIO */_PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x6e), +/* GPIO */_PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x6f), +/* GPIO */_PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x70), +/* GPIO */_PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x71), +/* GPIO */_PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x72), +/* GPIO */_PAD_CFG_STRUCT(GPP_D19, 0x44000300, 0x73), +/* GPIO */_PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x74), +/* GPIO */_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x75), +/* GPIO */_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x76), +/* GPIO */_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x77), +/* ------- GPIO Group GPP_E ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x84000102, 0x18), +/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x84000102, 0x19), +/* SATAXPCIE2 */_PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x1a), +/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x1b), +/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x84000200, 0x101c), +/* GPIO */_PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x1d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E6, 0x44000300, 0x1e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x1f), +/* GPIO */_PAD_CFG_STRUCT(GPP_E8, 0x44000300, 0x20), +/* GPIO */_PAD_CFG_STRUCT(GPP_E9, 0x44000300, 0x21), +/* GPIO */_PAD_CFG_STRUCT(GPP_E10, 0x44000201, 0x22), +/* GPIO */_PAD_CFG_STRUCT(GPP_E11, 0x80100102, 0x23), +/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x84000201, 0x24), +/* DDPB_HPD0 */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x25), +/* DDPC_HPD1 */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x26), +/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880300, 0x27), +/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000300, 0x28), +/* EDP_HPD */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x29), +/* DDPB_CTRLCLK */_PAD_CFG_STRUCT(GPP_E18, 0x44000702, 0x2a), +/* DDPB_CTRLDATA */_PAD_CFG_STRUCT(GPP_E19, 0x44000702, 0x102b), +/* DDPC_CTRLCLK */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x2c), +/* DDPC_CTRLDATA */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x102d), +/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000300, 0x2e), +/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x102f), +/* ------- GPIO Group GPD ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPD0, 0x4000201, 0x50), +/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000700, 0x51), +/* GPIO */_PAD_CFG_STRUCT(GPD2, 0x4000200, 0x52), +/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3053), +/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x54), +/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x55), +/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x56), +/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x57), +/* GPIO */_PAD_CFG_STRUCT(GPD8, 0x44000300, 0x58), +/* GPIO */_PAD_CFG_STRUCT(GPD9, 0x44000300, 0x59), +/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x44000700, 0x5a), +/* GPIO */_PAD_CFG_STRUCT(GPD11, 0x44000300, 0x5b), +/* ------- GPIO Group GPP_F ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x30), +/* GPIO */_PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x31), +/* GPIO */_PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x32), +/* GPIO */_PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x33), +/* GPIO */_PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x34), +/* GPIO */_PAD_CFG_STRUCT(GPP_F5, 0x44000300, 0x35), +/* GPIO */_PAD_CFG_STRUCT(GPP_F6, 0x44000300, 0x36), +/* GPIO */_PAD_CFG_STRUCT(GPP_F7, 0x44000300, 0x37), +/* GPIO */_PAD_CFG_STRUCT(GPP_F8, 0x44000100, 0x38), +/* GPIO */_PAD_CFG_STRUCT(GPP_F9, 0x44000100, 0x39), +/* I2C5_SDA */_PAD_CFG_STRUCT(GPP_F10, 0x44000702, 0x3a), +/* I2C5_SCL */_PAD_CFG_STRUCT(GPP_F11, 0x44000702, 0x3b), +/* GPIO */_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x3c), +/* GPIO */_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x3d), +/* GPIO */_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x3e), +/* GPIO */_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x3f), +/* GPIO */_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x40), +/* GPIO */_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x41), +/* GPIO */_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x42), +/* GPIO */_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x43), +/* GPIO */_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x44), +/* GPIO */_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x45), +/* GPIO */_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x46), +/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000300, 0x47), +/* ------- GPIO Group GPP_G ------- */ +/* GPIO */_PAD_CFG_STRUCT(GPP_G0, 0x44000102, 0x48), +/* GPIO */_PAD_CFG_STRUCT(GPP_G1, 0x44000102, 0x49), +/* GPIO */_PAD_CFG_STRUCT(GPP_G2, 0x44000100, 0x4a), +/* GPIO */_PAD_CFG_STRUCT(GPP_G3, 0x44000100, 0x4b), +/* GPIO */_PAD_CFG_STRUCT(GPP_G4, 0x44000100, 0x4c), +/* GPIO */_PAD_CFG_STRUCT(GPP_G5, 0x44000100, 0x4d), +/* GPIO */_PAD_CFG_STRUCT(GPP_G6, 0x44000100, 0x4e), +/* GPIO */_PAD_CFG_STRUCT(GPP_G7, 0x44000100, 0x4f), +}; + +#endif + +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c new file mode 100644 index 0000000..c0de990 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <chip.h> +#include <console/console.h> +#include <device/azalia_device.h> +#include <soc/intel/common/hda_verb.h> +#include <soc/pci_devs.h> + +#include "hda_verb.h" + +static void codecs_init(u8 *base, u32 codec_mask) +{ + int i; + + /* Can support up to 4 codecs */ + for (i = 3; i >= 0; i--) { + if (codec_mask & (1 << i)) + hda_codec_init(base, i, cim_verb_data_size, + cim_verb_data); + } + + if (pc_beep_verbs_size) + hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs); +} + +static void mb_hda_codec_init(void *unused) +{ + static struct soc_intel_skylake_config *config; + u8 *base; + struct resource *res; + u32 codec_mask; + struct device *dev; + + dev = SA_DEV_ROOT; + /* Check if HDA is enabled, else return */ + if (dev == NULL || dev->chip_info == NULL) + return; + + config = dev->chip_info; + + /* + * IoBufferOwnership 0:HD-A Link, 1:Shared HD-A Link and I2S Port, + * 3:I2S Ports. In HDA mode where codec need to be programmed with + * verb table + */ + if (config->IoBufferOwnership == 3) + return; + + /* Find base address */ + dev = pcidev_path_on_root(PCH_DEVFN_HDA); + if (dev == NULL) + return; + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + base = res2mmio(res, 0, 0); + printk(BIOS_DEBUG, "HDA: base = %p\n", base); + + codec_mask = hda_codec_detect(base); + + if (codec_mask) { + printk(BIOS_DEBUG, "HDA: codec_mask = %02x\n", codec_mask); + codecs_init(base, codec_mask); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, mb_hda_codec_init, NULL); diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h new file mode 100644 index 0000000..510a9ce --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/hda_verb.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0295, /* Codec Vendor / Device ID: Realtek */ + 0x103c83b9, /* Subsystem ID */ + 0x0000000d, /* Number of NID entries */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x103c83b9 */ + AZALIA_SUBVENDOR(0x0, 0x103c83b9), + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) */ + AZALIA_PIN_CFG(0x0, 0x12, 0xb7a60130), + + /* Pin Complex (NID 0x13) */ + AZALIA_PIN_CFG(0x0, 0x13, 0x40000000), + + /* Pin Complex (NID 0x14) */ + AZALIA_PIN_CFG(0x0, 0x14, 0x411111f0), + + /* Pin Complex (NID 0x16) */ + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + + /* Pin Complex (NID 0x17) */ + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + + /* Pin Complex (NID 0x18) */ + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + + /* Pin Complex (NID 0x19) */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03a11040), + + /* Pin Complex (NID 0x1A) */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x411111f0), + + /* Pin Complex (NID 0x1B) */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x411111f0), + + /* Pin Complex (NID 0x1D) */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40600001), + + /* Pin Complex (NID 0x1E) */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x411111f0), + + /* Pin Complex (NID 0x21) */ + AZALIA_PIN_CFG(0x0, 0x21, 0x03211020), +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c new file mode 100644 index 0000000..462b995 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/mainboard.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Purism SPC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> +#include <string.h> +#include <cbfs.h> + +#define MAX_SERIAL_LENGTH 0x100 + +const char *smbios_mainboard_serial_number(void) +{ + static char serial_number[MAX_SERIAL_LENGTH + 1] = {0}; + struct cbfsf file; + + if (serial_number[0] != 0) + return serial_number; + + if (cbfs_boot_locate(&file, "serial_number", NULL) == 0) { + struct region_device cbfs_region; + size_t serial_len; + + cbfs_file_data(&cbfs_region, &file); + + serial_len = region_device_sz(&cbfs_region); + if (serial_len <= MAX_SERIAL_LENGTH) { + if (rdev_readat(&cbfs_region, serial_number, 0, + serial_len) == serial_len) { + serial_number[serial_len] = 0; + return serial_number; + } + } + } + + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, + MAX_SERIAL_LENGTH); + + return serial_number; +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c new file mode 100644 index 0000000..94f8071 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c new file mode 100644 index 0000000..faf4090 --- /dev/null +++ b/src/mainboard/hp/spectre_x360_13t_ae000/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * Copyright (C) 2017 Purism SPC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + const u16 RcompTarget[5] = { 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t) blk.spd_array[0]; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie744cdccd3d110b4137e0b017b3f8497d23c0497 Gerrit-Change-Number: 34946 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Parnell <mparnell(a)gmail.com> Gerrit-MessageType: newchange

6 57

Change in coreboot[master]: src/mainboard/asus: Add h110m-e_m2 mainboard support
by Pavel Sayekat (Code Review) June 8, 2024

June 8, 2024

Pavel Sayekat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34603 ) Change subject: src/mainboard/asus: Add h110m-e_m2 mainboard support ...................................................................... src/mainboard/asus: Add h110m-e_m2 mainboard support Signed-off-by: Pavel Sayekat <pavelsayekat(a)gmail.com> Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c --- A src/mainboard/asus/h110m-e_m2/6776.txt A src/mainboard/asus/h110m-e_m2/Kconfig A src/mainboard/asus/h110m-e_m2/Kconfig.name A src/mainboard/asus/h110m-e_m2/Makefile.inc A src/mainboard/asus/h110m-e_m2/acpi/dptf.asl A src/mainboard/asus/h110m-e_m2/acpi/ec.asl A src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl A src/mainboard/asus/h110m-e_m2/acpi/superio.asl A src/mainboard/asus/h110m-e_m2/acpi_tables.c A src/mainboard/asus/h110m-e_m2/board_info.txt A src/mainboard/asus/h110m-e_m2/bootblock.c A src/mainboard/asus/h110m-e_m2/cmos.default A src/mainboard/asus/h110m-e_m2/cmos.layout A src/mainboard/asus/h110m-e_m2/data.vbt A src/mainboard/asus/h110m-e_m2/devicetree.cb A src/mainboard/asus/h110m-e_m2/dsdt.asl A src/mainboard/asus/h110m-e_m2/gma-mainboard.ads A src/mainboard/asus/h110m-e_m2/gpio.txt A src/mainboard/asus/h110m-e_m2/hda_verb.c A src/mainboard/asus/h110m-e_m2/include/gpio.h A src/mainboard/asus/h110m-e_m2/mainboard.c A src/mainboard/asus/h110m-e_m2/ramstage.c A src/mainboard/asus/h110m-e_m2/romstage.c 23 files changed, 1,875 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34603/1 diff --git a/src/mainboard/asus/h110m-e_m2/6776.txt b/src/mainboard/asus/h110m-e_m2/6776.txt new file mode 100644 index 0000000..9969ca7 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/6776.txt @@ -0,0 +1,10 @@ +acpi/superio.asl:#define NCT6776_SHOW_PP +acpi/superio.asl:#define NCT6776_SHOW_SP1 +acpi/superio.asl:#define NCT6776_SHOW_KBC +acpi/superio.asl:#define NCT6776_SHOW_HWM +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +acpi/superio.asl:#include <superio/nuvoton/nct6776/acpi/superio.asl> +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig b/src/mainboard/asus/h110m-e_m2/Kconfig new file mode 100644 index 0000000..55a21cf --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig @@ -0,0 +1,53 @@ +if BOARD_ASUS-H110M_E-M2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select GENERIC_SPD_BIN + select SUPERIO_NUVOTON_NCT5539D + select SUPERIO_NUVOTON_NCT5539D_COM_A + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asus/h110m" + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asus/h110m-e_m2/Kconfig.name b/src/mainboard/asus/h110m-e_m2/Kconfig.name new file mode 100644 index 0000000..788594c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_H110M_E-M.2 + bool "H110M_E-M.2" diff --git a/src/mainboard/asus/h110m-e_m2/Makefile.inc b/src/mainboard/asus/h110m-e_m2/Makefile.inc new file mode 100644 index 0000000..ce6cf80 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi/ec.asl b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/ec.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/mainboard.asl diff --git a/src/mainboard/asus/h110m-e_m2/acpi/superio.asl b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asus/h110m-e_m2/acpi_tables.c b/src/mainboard/asus/h110m-e_m2/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/acpi_tables.c diff --git a/src/mainboard/asus/h110m-e_m2/board_info.txt b/src/mainboard/asus/h110m-e_m2/board_info.txt new file mode 100644 index 0000000..23fd8e6 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asus.com/Motherboards/H110M-E-M-2/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2017 diff --git a/src/mainboard/asus/h110m-e_m2/bootblock.c b/src/mainboard/asus/h110m-e_m2/bootblock.c new file mode 100644 index 0000000..eb019c2 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5539d/nct5539d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT5539D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asus/h110m-e_m2/cmos.default b/src/mainboard/asus/h110m-e_m2/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asus/h110m-e_m2/cmos.layout b/src/mainboard/asus/h110m-e_m2/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asus/h110m-e_m2/data.vbt b/src/mainboard/asus/h110m-e_m2/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/data.vbt Binary files differ diff --git a/src/mainboard/asus/h110m-e_m2/devicetree.cb b/src/mainboard/asus/h110m-e_m2/devicetree.cb new file mode 100644 index 0000000..cdc6c2d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/devicetree.cb @@ -0,0 +1,388 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "SkipExtGfxScan" = "0" + register "PrimaryDisplay" = "Display_PEG" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Set params for PEG 0:1:0 + register "Peg0MaxLinkWidth" = "Peg0_x16" + # Configure PCIe clockgen in PCH + # PEG0 uses SRCCLKREQ0 and CLKSRC0 + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct5539d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU + end # superio/nuvoton/nct5539d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asus/h110m-e_m2/dsdt.asl b/src/mainboard/asus/h110m-e_m2/dsdt.asl new file mode 100644 index 0000000..f3e216d --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +-- Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asus/h110m-e_m2/gpio.txt b/src/mainboard/asus/h110m-e_m2/gpio.txt new file mode 100644 index 0000000..3416eee --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/gpio.txt @@ -0,0 +1,580 @@ +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +acpi/superio.asl:#undef NCT6776_SHOW_GPIO +include/gpio.h:#ifndef _GPIO_DVS_H +include/gpio.h:#define _GPIO_DVS_H +include/gpio.h: /* GPIO Group GPP_A */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_B */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_C */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_D */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_E */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_F */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_G */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_H */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +include/gpio.h: /* GPIO Group GPD */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_I */ +include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +include/gpio.h: /* GPIO Group GPP_A */ +devicetree.cb: device pnp 2e.7 off end # GPIO6 +devicetree.cb: device pnp 2e.107 off end # GPIO7 +devicetree.cb: device pnp 2e.207 off end # GPIO8 +devicetree.cb: device pnp 2e.108 off end # GPIO0 +devicetree.cb: device pnp 2e.308 off end # GPIO base +devicetree.cb: device pnp 2e.708 off end # GPIO1 +devicetree.cb: device pnp 2e.9 off end # GPIO2 +devicetree.cb: device pnp 2e.109 off end # GPIO3 +devicetree.cb: device pnp 2e.209 off end # GPIO4 +devicetree.cb: device pnp 2e.309 off end # GPIO5 +devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_H */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPD */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_I */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:devicetree.cb: device pnp 2e.7 off end # GPIO6 +gpio.txt:devicetree.cb: device pnp 2e.107 off end # GPIO7 +gpio.txt:devicetree.cb: device pnp 2e.207 off end # GPIO8 +gpio.txt:devicetree.cb: device pnp 2e.108 off end # GPIO0 +gpio.txt:devicetree.cb: device pnp 2e.308 off end # GPIO base +gpio.txt:devicetree.cb: device pnp 2e.708 off end # GPIO1 +gpio.txt:devicetree.cb: device pnp 2e.9 off end # GPIO2 +gpio.txt:devicetree.cb: device pnp 2e.109 off end # GPIO3 +gpio.txt:devicetree.cb: device pnp 2e.209 off end # GPIO4 +gpio.txt:devicetree.cb: device pnp 2e.309 off end # GPIO5 +gpio.txt:devicetree.cb: device pnp 2e.f off end # GPIO PP/OD +gpio.txt:acpi/superio.asl:#undef NCT6776_SHOW_GPIO +gpio.txt:include/gpio.h:#ifndef _GPIO_DVS_H +gpio.txt:include/gpio.h:#define _GPIO_DVS_H +gpio.txt:include/gpio.h: /* GPIO Group GPP_A */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_B */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_C */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_D */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_E */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_F */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ +gpio.txt:include/gpio.h: /* GPIO Group GPP_G */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ +gpio.txt:include/gpio.h: H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ diff --git a/src/mainboard/asus/h110m-e_m2/hda_verb.c b/src/mainboard/asus/h110m-e_m2/hda_verb.c new file mode 100644 index 0000000..1d1627b --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/hda_verb.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki <naresh.solanki(a)intel.com> for Intel Corp.) + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asus/h110m-e_m2/include/gpio.h b/src/mainboard/asus/h110m-e_m2/include/gpio.h new file mode 100644 index 0000000..a8a4d19 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/include/gpio.h @@ -0,0 +1,266 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_DVS_H +#define _GPIO_DVS_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x44000502, 0x00003023), /* PME# */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x04000100, 0x00001029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x04000100, 0x0000102a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x04000100, 0x0000102b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x04000100, 0x0000102c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x04000100, 0x0000102d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x04000100, 0x0000102e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x04000100, 0x0000102f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x04000100, 0x00001034), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x44000702, 0x00000035), /* SRCCLKREQ0# */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x04000100, 0x00001036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x04000500, 0x00001037), /* SRCCLKREQ2# */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x04000500, 0x00001039), /* SRCCLKREQ4# */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x04000500, 0x0000103a), /* SRCCLKREQ5# */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x84000100, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x84000100, 0x0000103c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x84000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000003e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000200, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000100, 0x00001047), /* GPIO */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x84000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x84000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x84000100, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x84000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x84000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C6, 0x04000102, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C7, 0x04000102, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x04000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x04000100, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x04000100, 0x00001055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x04000100, 0x00001057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x04000100, 0x00001058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x04000100, 0x0000105a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000100, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000100, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x84000100, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x04000100, 0x00001061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x04000100, 0x00001063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x04000100, 0x00001065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x04000100, 0x00001067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x04000100, 0x00001068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000100, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000100, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x04000100, 0x0000106b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x04000102, 0x0000106c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000100, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000102, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x04000100, 0x00001070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x04000100, 0x00001072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x04000100, 0x00001073), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x04000100, 0x00001074), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x04000100, 0x00001077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000100, 0x0000001a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x04000100, 0x0000101b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x44000100, 0x0000001c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x04000100, 0x0000101d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x04000100, 0x0000101e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x04000100, 0x0000101f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x84000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x84000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x84000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x84000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000100, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x04000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x04000100, 0x00001027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x04000100, 0x00001028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000100, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000100, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000100, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000100, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000100, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x84000100, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x04000100, 0x00001030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x04000100, 0x00001031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x04000100, 0x00001032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x04000100, 0x00001033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x84000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000102, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x04000100, 0x00001038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x04000100, 0x00001039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x04000100, 0x0000103a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x04000100, 0x0000103b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x04000100, 0x0000103c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0x04000100, 0x0000103d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0x04000100, 0x0000103e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0x04000100, 0x0000103f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0x04000100, 0x00001040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x04000100, 0x00001041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0x84000100, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0x84000100, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x04000100, 0x00001045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x04000100, 0x00001046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x04000100, 0x00001047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x04000100, 0x00001048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x04000100, 0x00001049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x04000100, 0x0000104a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x84000100, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000100, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x04000100, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x04000100, 0x0000104e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x84000100, 0x0000104f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000100, 0x00001050), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x04000100, 0x00001051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x04000100, 0x00001052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x04000100, 0x00001053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x04000100, 0x00001054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000100, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000702, 0x00000056), /* SRCCLKREQ7# */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000100, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000100, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x04000100, 0x00001059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000100, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x04000100, 0x0000105b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x04000100, 0x0000105c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x44000702, 0x0000005d), /* SRCCLKREQ14# */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x04000100, 0x0000105e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x04000100, 0x0000105f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x04000100, 0x00001060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x44000100, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x84000100, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x04000100, 0x00001064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x84000100, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x04000100, 0x00001066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000100, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000100, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000100, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x84000102, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x84000102, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x84000502, 0x0000001a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x84000502, 0x0000001b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x84000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x84000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000100, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x84000500, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000100, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x84000100, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000102, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000500, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000500, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x04000100, 0x00001071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00000073), + /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000502, 0x00000074), + /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000502, 0x00000075), + /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000100, 0x00000077), /* GPIO */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00000019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000001a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000001b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000001c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x84000100, 0x00001026), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000500, 0x00000027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asus/h110m-e_m2/mainboard.c b/src/mainboard/asus/h110m-e_m2/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/h110m-e_m2/ramstage.c b/src/mainboard/asus/h110m-e_m2/ramstage.c new file mode 100644 index 0000000..c93e84c --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov <max.senia.poliak(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asus/h110m-e_m2/romstage.c b/src/mainboard/asus/h110m-e_m2/romstage.c new file mode 100644 index 0000000..ae5e297 --- /dev/null +++ b/src/mainboard/asus/h110m-e_m2/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Pavel Sayekat <pavelsayekat(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34603 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8fa41ecccaa8dba8dc2158ce62d328c7928e05c Gerrit-Change-Number: 34603 Gerrit-PatchSet: 1 Gerrit-Owner: Pavel Sayekat Gerrit-MessageType: newchange

12 248