October 2015 - coreboot-gerrit

Patch merged into coreboot/master: northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hex
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit b2a1a59ab5e9ed8253249daebe8666baf9876214 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 16:20:56 2015 -0500 northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hex This resolves a Kconfig warning. Change-Id: Ic77c8bf89613c116dfdc73572709aeb354e33b2a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12287 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12287 for details. -gerrit

1 0

New patch to review for coreboot: northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hex
by Timothy Pearson Oct. 31, 2015

Oct. 31, 2015

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12287 -gerrit commit 1119882ab544f50d8f9047b4279771df793b6b40 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 16:20:56 2015 -0500 northbridge/amd/amdfam10: Correct S3_DATA_POS type from int to hex This resolves a Kconfig warning. Change-Id: Ic77c8bf89613c116dfdc73572709aeb354e33b2a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 39d6ecf..3ea1e46 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -95,8 +95,8 @@ config S3_DATA_SIZE depends on (HAVE_ACPI_RESUME) config S3_DATA_POS - int - default 0 + hex + default 0x0 depends on (HAVE_ACPI_RESUME) if DIMM_DDR2

1 0

Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) support
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit babb2e67bc0a7c2da167ac56e26881823c5fad81 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu May 7 01:32:08 2015 -0500 mainboard/asus/kgpe-d16: Add initial Suspend to RAM (S3) support Change-Id: I7da84b064287a445fd75a947e2f96ce1ae30d3de Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11954 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11954 for details. -gerrit

1 0

Patch merged into coreboot/master: northbridge/amd/amdfam10: Update RAM speed table with DDR3 values
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit 160ad6aa75eccf3e15bac3ccc99f5fc4cb36251d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 30 18:53:48 2015 -0500 northbridge/amd/amdfam10: Update RAM speed table with DDR3 values Change-Id: I8ab7b2cd9bf36d53b744a11d32dd40c750149567 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12272 for details. -gerrit

1 0

Patch merged into coreboot/master: southbridge/amd/sb700: Remove acpi_get_sleep_type for early CBMEM
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit 0746452a267c228d396a6a1faec3e9966e232e32 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Oct 30 14:46:18 2015 -0500 southbridge/amd/sb700: Remove acpi_get_sleep_type for early CBMEM The acpi_get_sleep_type function in SB700 ramstage is only needed for boards / CPUs that require late CBMEM initialization. Providing this function in early CBMEM-compatible boards breaks building of the ACPI S3 code due to multiple definitions of acpi_get_sleep_type. Change-Id: Ieebc2640a586812e3e2bfd410987205d64147314 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12267 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12267 for details. -gerrit

1 0

Patch merged into coreboot/master: intel/gma: Return success for Intel int15 VGA set panel type hook
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit 3c47e8a782c21e6d987f670713242397ec01b82a Author: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Date: Sat Jan 24 21:02:19 2015 +0400 intel/gma: Return success for Intel int15 VGA set panel type hook One of the interrupts in intel_vga_int15_handler lacks positive return status. Write correct status to avoid error messages in log. TEST=With this change `int15 call returned error` is not shown anymore on a custom board with Intel Atom CPU, i945GME northbridge and i82801gx southbridge. Change-Id: I740b2df9bd6a7d261d89bef74b924edbb64354aa Signed-off-by: Konstantin Aladyshev <aladyshev(a)nicevt.ru> Reviewed-on: http://review.coreboot.org/12255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/12255 for details. -gerrit

1 0

Patch merged into coreboot/master: util/scripts/no-fsf-addresses.sh: Strip last paragraph
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit ee0028da3bfa648a0ae474b1d05da1562da81c8d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Oct 13 22:11:13 2015 +0200 util/scripts/no-fsf-addresses.sh: Strip last paragraph checkpatch.pl that we inherited from Linux checks for its absence, so it may be easiest to follow their style of not caring for the FSF's address anymore. TEST=visual check that `git diff` and `git diff |grep "^[+-]" | \ grep -v "^--- " |grep -v "^+++ " |sort | uniq -c |sort -n` look reasonable (matching number of removed and added comment terminators */, etc.). Also, `git grep -A3 "You should have received a copy"` only returns license texts, imported files, patches and help strings in applications as remaining copies of that paragraph Change-Id: I7c43860b6fd7ec526983c24b608994539128cfb9 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11887 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/11887 for details. -gerrit

1 0

Patch merged into coreboot/master: tree: drop last paragraph of GPL copyright header
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit a73b93157f2a5ed42bebf9a5948a4e2cedcb4250 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Oct 31 11:55:10 2015 +0100 tree: drop last paragraph of GPL copyright header It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/11888 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support
by gerrit＠coreboot.org Oct. 31, 2015

Oct. 31, 2015

the following patch was just integrated into master: commit 74b13a56166649967a3e9ab0e4ea5c68b518c6b2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 15:00:23 2015 -0500 mainboard/asus/kfsn4-dre_k8: Fix broken dual CPU package support The existing KFSN4-DRE support hung during ramstage while initializing AP #3 if a second CPU package was installed. After analyzing the Sun Ultra 40 M2 support code it became apparent that the K8 code cannot function correctly if sequential RAM training is disabled, and that there were a few other missing calls. This patch adds the missing calls, adjust the CAR space to an appropriate level, and explicitly defines the link numbers and connections in devicetree.cb TEST: Booted ASUS KFSN4-DRE with 2x Opteron 8222 installed. Change-Id: I96178b7367b0c13de5c9d5d90d032fb0c53639c2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12285 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12285 for details. -gerrit

1 0

New patch to review for coreboot: cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10h
by Timothy Pearson Oct. 31, 2015

Oct. 31, 2015

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12286 -gerrit commit 9e679bf63b16ddefb8243a3bd2754c1bdfa634d4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Oct 31 15:21:24 2015 -0500 cpu/amd/model_fxx: Backport PowerNow! core count fix from Family 10h The K8 PowerNow! state generator does not generate _PSS objects for nodes other than the first CPU package. This patch backports the PowerNow! core count fixes for Family 10h to the K8 CPUs. Change-Id: I7b411ab75155dfb4bf51ae04301aa16fb2ae89f3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/model_fxx/powernow_acpi.c | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c index 53330f9..4342d88 100644 --- a/src/cpu/amd/model_fxx/powernow_acpi.c +++ b/src/cpu/amd/model_fxx/powernow_acpi.c @@ -104,6 +104,10 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) u8 cmp_cap, pwr_lmt; u32 power_limit = 0; u8 index; + uint8_t node_count; + uint8_t cores_per_node; + uint32_t total_core_count; + uint32_t dword; msr_t msr; u32 fid_multiplier; static const struct power_limit_encoding TDP[] = { @@ -160,9 +164,18 @@ static void pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP) * cmp_cap : 0x0 SingleCore ; 0x1 DualCore */ printk(BIOS_INFO, "Pstates Algorithm ...\n"); - cmp_cap = - (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) & - 0x3000) >> 12; + + /* Get number of cores */ + dword = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xe8); + cmp_cap = (dword & 0x3000) >> 12; + /* Get number of nodes */ + dword = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x18, 0)), 0x60); + node_count = ((dword & 0x70) >> 4) + 1; + cores_per_node = cmp_cap + 1; + + /* Compute total number of cores installed in system */ + total_core_count = cores_per_node * node_count; + cpuid1 = cpuid(0x80000001); pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14); for (index = 0; index < ARRAY_SIZE(TDP); index++) @@ -364,7 +377,7 @@ write_pstates: (0x0 << 18) | /* MVS */ (0x5 << 11); /* VST */ - for (index = 0; index < (cmp_cap + 1); index++) { + for (index = 0; index < total_core_count; index++) { write_pstates_for_core(Pstate_num, Pstate_feq, Pstate_vid, Pstate_fid, Pstate_power, index, pcontrol_blk, plen, onlyBSP, control);

1 0